CN101740378B - Copper chemical mechanical polishing method - Google Patents
Copper chemical mechanical polishing method Download PDFInfo
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- CN101740378B CN101740378B CN2008102263307A CN200810226330A CN101740378B CN 101740378 B CN101740378 B CN 101740378B CN 2008102263307 A CN2008102263307 A CN 2008102263307A CN 200810226330 A CN200810226330 A CN 200810226330A CN 101740378 B CN101740378 B CN 101740378B
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Abstract
The invention discloses a copper chemical mechanical polishing method so as to remove copper residue which is hard to clean in a metal-dielectric medium-metal (MIM) structure. The method comprises the following steps: firstly, putting a wafer with the MIM structure on a first grinding pad for rough grinding to remove most copper on the surface; secondly, putting the wafer on a second grinding padfor finish grinding to remove residual copper on the surface of the wafer for the first time; thirdly, putting the wafer on a third grinding pad for grinding to remove residues of a barrier layer on the surface of the wafer, and reducing the height difference of a deep step; fourthly, putting the wafer on the first grinding pad or the second grinding pad once again for grinding to remove copper residues on the bottom of the deep step; and finally, putting the wafer on the third grinding pad for final flattening. The method can effectively clean the copper residues in a specific area in the MIM structure, and can remarkably reduce the over grinding phenomenon of the specific area in the MIM structure.
Description
Technical field
The present invention relates to integrated circuit (Integrated Circuit, IC) processing and manufacturing technical field, particularly a kind of improved copper CMP (Cu Chemical Mechanical Polishing, Cu-CMP) method.
Background technology
The device of copper-connection can satisfy the requirement of high frequency, high integration, high-power, big capacity, long service life with respect to traditional aluminium interconnect devices.But, because the etch products of copper in etching process is not volatile, so can't prepare element with plasma etching, then ingenious this problem that solved of dual damascene (DualDamascene) technology of IBM invention.In dual damascene process, at first the medium of oxides layer is carried out etching, produce the groove that is used for mosaic technology; Follow the plated metal barrier layer then, copper seed layer, (Electronic Chemical Plating, ECP) technology is filling up copper in the groove by the electrochemistry plating again.Usually, be subjected to the influence of groove structure and ECP load effect, it is irregular electroplating the copper surface that forms.After this, must adopt the Cu-CMP glossing to realize the copper planarization.
(Chemical Mechanical Polishing, CMP) technology is exactly in the atmospheric environment of dust free room, utilizes mechanical force to the wafer surface effect, produces the power of fracture corrosion at the surface film layer, makes wafer surface be tending towards planarization in chemico-mechanical polishing.And this part must increase its etched efficient by the chemical substance in the lapping liquid by reaction by nationality.Most important two big assemblies are slurry (slurry) and grinding pad (platen) in the CMP processing procedure.The oxide powder that slurry is normally very thin with some is dispersed in the aqueous solution and makes.Grinding pad is to use the porous polyurethane of foaming type to make mostly.In the CMP processing procedure, allow slurry be filled in the space of grinding pad earlier, and high-revolving condition is provided, allow wafer under high speed rotating and the powder effect in grinding pad and the slurry, control other parameters such as pressure that press down simultaneously.And the interaction between slurry, wafer and the grinding pad is the focus that reacts among the CMP.
Existing C u-CMP glossing comprises three process of lapping: the first step, carry out roughing grind on first grinding pad (Platen1), (Material Removal rate MRR) removes a large amount of copper and forms preliminary planarization by bigger material removing rate; Second goes on foot, carries out fine finishining on second grinding pad (Platen2) grinds, in order accurately to control grinding endpoint, remove remaining copper with less relatively MRR, when arriving grinding endpoint,, the copper on all dielectric surfaces reaches the isolation purpose in order to ensure all being removed, also to carry out excessive polishing (over polish, OP) processing of certain hour; The 3rd goes on foot, grinds on the 3rd grinding pad (Platen3), removes barrier layer (barrier) and a certain amount of oxide dielectric with further raising flattening surface degree, reduces defective.The paste composition that each step is adopted determines its effectiveness.Wherein, the main purpose of first two steps is to remove remaining copper, and is then very little for the contribution of removing oxide; The 3rd step was then mainly removed barrier layer and oxide.
For metal-insulator medium-metal (metal-insulator-metal, MIM) such device architecture, particularly single damascene structure (single damascene fabrication sequence) after above-mentioned first two steps, is difficult to remove fully the residue of plane of crystal copper.At having the process that mim structure element (for example capacitor) carries out the Cu-CMP polishing, the way of taking usually is constantly to prolong wafer and interactional time of the 3rd grinding pad (Platen3), for example milling time is brought up to about 400 seconds.But this can bring a series of serious problems: for example extremely low output consumption rate; Cause the impaired risk of wafer surface to improve greatly owing to cross long-time the grinding.
Summary of the invention
In view of this, the embodiment of the invention proposes a kind of copper chemical mechanical polishing method, comprises the steps:
The wafer that will have metal-dielectric-metal structure places for the first time and carries out the roughing grinding on first grinding pad, removes the most copper of wafer surface; Again described wafer is placed for the first time and carry out the fine finishining grinding on second grinding pad, remove the remaining copper of wafer surface;
Described wafer placed on the 3rd grinding pad for the first time grind, residual and reduce the difference in height of dark step in metal-dielectric-metallic region with the barrier layer of removing wafer surface; Place described first grinding pad or the second time to place on described second grinding pad for the second time described wafer and grind, residual with the copper of removing dark step bottom in metal-dielectric-metal structure;
Described wafer placed on described the 3rd grinding pad for the second time grind.
Preferably, described wafer being placed for the first time the milling time scope of grinding on the 3rd grinding pad is 100 seconds to 120 seconds.
Preferably, described wafer being placed for the second time on described first grinding pad or place the milling time scope on described second grinding pad for the second time is 30 seconds to 60 seconds.
The embodiment of the invention also proposes another kind of copper chemical mechanical polishing method, and the wafer that will have metal-dielectric-metal structure places for the first time and carries out the roughing grinding on first grinding pad, removes the most copper of wafer surface; Again described wafer is placed for the first time and carry out the fine finishining grinding on second grinding pad, remove the remaining copper of wafer surface;
Described wafer placed on the 3rd grinding pad for the first time grind, residual and reduce the difference in height of dark step in metal-dielectric-metallic region with the barrier layer of removing wafer surface; Earlier described wafer is placed on described first grinding pad for the second time and grind, described wafer is placed on described second grinding pad for the second time grind again, residual with the copper of removing dark step bottom in metal-dielectric-metal structure;
Described wafer placed on described the 3rd grinding pad for the second time grind.
As can be seen from the above technical solutions, after wafer grinds on the 3rd grinding pad for the first time, the barrier layer planarization of wafer surface, the degree of depth of the dark step on wafer surface barrier layer significantly reduces, and the copper remnants that are in dark step bottom originally just come out.Processing grinding on first grinding pad and second grinding pad just can be removed this part copper remnants effectively so for the second time.The present invention program can significantly reduce the slurry loss, and alleviates the wearing and tearing of marginal portion in the MIM zone.
Description of drawings
Fig. 1 for wafer through after the electroplating processes, prepare to enter the Cu-CMP glossing stage before the tangent plane schematic diagram;
Fig. 2 is in existing C u-CMP glossing, the tangent plane schematic diagram of wafer shown in Figure 1 after grinding by grinding table 2;
Fig. 3 is in existing C u-CMP glossing, the tangent plane schematic diagram of wafer shown in Figure 1 after grinding by grinding table 3;
Fig. 4 is the flow chart of the Cu-CMP glossing of embodiment of the invention proposition;
Fig. 5 is in the Cu-CMP glossing that the embodiment of the invention proposes, the tangent plane schematic diagram after wafer shown in Figure 1 was handled in the phase I;
Fig. 6 is in the Cu-CMP glossing that the embodiment of the invention proposes, the tangent plane schematic diagram of wafer shown in Figure 1 after second stage is handled.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is further elaborated below in conjunction with accompanying drawing.
Fig. 1 to Fig. 3 shows the wafer tangent plane schematic diagram in existing each stage of Cu-CMP glossing respectively.Fig. 1 shows wafer through the situation after the electroplating processes, before preparing to enter the Cu-CMP glossing stage.This wafer has single damascene structure, between two adjacent MIM capacitor parts, sizable interval that is made of the barrier layer is arranged, can form dark step (high step height) at the interval with certain depth, often be referred to as " dark step effect " dark step in the industry, shown in oval marks among Fig. 1, this can increase the difficulty of removing copper in the CMP technology.Fig. 2 shows the situation after wafer grinds by the second step grinding table 2.Because grinding table 1 and grinding table 2 are mainly used in removal copper, but very little for the effect of removing the barrier layer, slurry is difficult to enter the dark step that forms in the electrochemistry plating, and the copper in the therefore dark step is difficult to be removed.
Fig. 3 shows the situation after wafer grinds by the 3rd step grinding table 3.Grinding table 3 is mainly used in removes the barrier layer, thereby can significantly reduce the degree of depth of dark step, so the slurry on the grinding table 3 can touch the copper remnants in the dark step.But it is relatively poor that the slurry of grinding table 3 is removed the effect of copper, in order to remove the unnecessary copper in surface, the 3rd step was adopted long milling time, for example about 400 seconds, this partly causes comparatively serious wearing and tearing can for Waffer edge, shown in the oval marks among Fig. 3, also can cause the output loss ratio not high simultaneously.
Fig. 4 shows embodiment of the invention scheme with Cu-CMP glossing process.Specifically be divided into two stages.Phase I comprises:
Step 1: wafer placed carry out first time roughing on first grinding pad and grind, remove the residue of the most copper of wafer surface;
Step 2: described wafer placed carry out first time fine finishining on second grinding pad and grind, remove the remaining copper of wafer surface; But the special area in metal-dielectric-metal structure, because dark step effect makes the copper in the bottom be difficult to be eliminated totally;
Step 3: described wafer placed on the 3rd grinding pad for the first time grind, residual with the barrier layer of removing wafer surface, and reduce the difference in height of above-mentioned dark step, its milling time is less than the milling time of wafer on the 3rd grinding pad in the existing technology.
The milling time of step 3 can not be too short, and the too short effect of removing the barrier layer that then can make is bad, can not significantly reduce the difference in height of dark step, influences follow-up step; Milling time also can not be long, and the long process efficiency that then can cause descends, and may damage wafer.Preferably, milling time can be set to 100 seconds to 120 seconds, much smaller than 400 seconds of the prior art.
Through after the above step, the second stage that enters the Cu-CMP glossing:
Step 4: described wafer placed carry out second time roughing on described first grinding pad and grind;
Step 5: described wafer placed carry out second time fine finishining on described second grinding pad and grind;
Step 6: described wafer placed on described the 3rd grinding pad for the second time grind.
Preferably, the milling time scope that the described roughing second time is ground or fine finishining is for the second time ground is 30 seconds to 60 seconds.
Because the grinding in the second stage on first grinding pad or second grinding pad all be for the copper of removing dark step bottom residual, be assigned on two planten is in order to make process time balance more, in fact can only to grind the effect that can reach same on the grinding pad in first grinding pad or second grinding pad.
Because the process of lapping of step 3 makes the barrier layer planarization of wafer surface, the degree of depth of dark step significantly reduces, originally the copper remnants that are in dark step bottom just come out, and it is residual that the copper of dark step bottom in the MIM zone can be easier removed in the grinding of second stage first grinding pad and/or second grinding pad; Last again wafer being placed carried out last planarization on the 3rd grinding pad.Wafer tangent plane after also handling with electrochemistry plating shown in Figure 1 is an example, and through after the processing of embodiment of the invention phase I, its tangent plane as shown in Figure 4.Step 4 just can be removed this part copper remnants effectively to step 5 like this.Wafer tangent plane after final the processing as shown in Figure 5.Compare with Fig. 3, the wearing and tearing of the Waffer edge part among Fig. 5 significantly alleviate, and the loss of slurry also reduces greatly than prior art in the whole C u-CMP glossing process of the embodiment of the invention.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. copper chemical mechanical polishing method, the wafer that will have metal-dielectric-metal structure place for the first time and carry out roughing on first grinding pad and grind, and remove the most copper of wafer surface; Again described wafer is placed for the first time and carry out the fine finishining grinding on second grinding pad, remove the remaining copper of wafer surface; It is characterized in that, after above-mentioned steps, comprise the steps:
Described wafer placed on the 3rd grinding pad for the first time grind, residual and reduce the difference in height of dark step in metal-dielectric-metallic region with the barrier layer of removing wafer surface; Place described first grinding pad or the second time to place on described second grinding pad for the second time described wafer and grind, residual with the copper of removing dark step bottom in metal-dielectric-metal structure;
Described wafer placed on described the 3rd grinding pad for the second time grind.
2. copper chemical mechanical polishing method according to claim 1 is characterized in that, it is 100 seconds to 120 seconds that described wafer is placed the milling time scope of grinding on the 3rd grinding pad for the first time.
3. copper chemical mechanical polishing method according to claim 1 is characterized in that, described wafer is placed on described first grinding pad for the second time or places the milling time scope on described second grinding pad for the second time is 30 seconds to 60 seconds.
4. copper chemical mechanical polishing method, the wafer that will have metal-dielectric-metal structure place for the first time and carry out roughing on first grinding pad and grind, and remove the most copper of wafer surface; Again described wafer is placed for the first time and carry out the fine finishining grinding on second grinding pad, remove the remaining copper of wafer surface; It is characterized in that, after above-mentioned steps, comprise the steps:
Described wafer placed on the 3rd grinding pad for the first time grind, residual and reduce the difference in height of dark step in metal-dielectric-metallic region with the barrier layer of removing wafer surface; Earlier described wafer is placed on described first grinding pad for the second time and grind, described wafer is placed on described second grinding pad for the second time grind again, residual with the copper of removing dark step bottom in metal-dielectric-metal structure;
Described wafer placed on described the 3rd grinding pad for the second time grind.
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| CN2008102263307A CN101740378B (en) | 2008-11-13 | 2008-11-13 | Copper chemical mechanical polishing method |
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| CN2008102263307A CN101740378B (en) | 2008-11-13 | 2008-11-13 | Copper chemical mechanical polishing method |
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| CN101740378B true CN101740378B (en) | 2011-07-20 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103943558B (en) * | 2014-04-28 | 2016-09-21 | 华进半导体封装先导技术研发中心有限公司 | Use the method that the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer is planarized by CMP |
| CN103985668B (en) * | 2014-05-13 | 2018-02-23 | 上海集成电路研发中心有限公司 | The preparation method of copper-connection |
| CN105513961B (en) * | 2014-09-22 | 2020-09-29 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical polishing method |
| CN114473859A (en) * | 2020-11-11 | 2022-05-13 | 中国科学院微电子研究所 | Wafer polishing apparatus and wafer polishing method |
| CN113327852B (en) * | 2021-05-27 | 2022-07-29 | 上海芯物科技有限公司 | Chemical mechanical polishing method for wafer surface |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1618569A (en) * | 2003-11-17 | 2005-05-25 | 台湾积体电路制造股份有限公司 | Cmp process and process for polishing copper layer oxide on base |
| US7201784B2 (en) * | 2003-06-30 | 2007-04-10 | Intel Corporation | Surfactant slurry additives to improve erosion, dishing, and defects during chemical mechanical polishing of copper damascene with low k dielectrics |
| CN101124662A (en) * | 2004-11-10 | 2008-02-13 | 英诺普雷股份有限公司 | Methods for fabricating one or more metal damascene structures in a semiconductor wafer |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7201784B2 (en) * | 2003-06-30 | 2007-04-10 | Intel Corporation | Surfactant slurry additives to improve erosion, dishing, and defects during chemical mechanical polishing of copper damascene with low k dielectrics |
| CN1618569A (en) * | 2003-11-17 | 2005-05-25 | 台湾积体电路制造股份有限公司 | Cmp process and process for polishing copper layer oxide on base |
| CN101124662A (en) * | 2004-11-10 | 2008-02-13 | 英诺普雷股份有限公司 | Methods for fabricating one or more metal damascene structures in a semiconductor wafer |
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