CN112247825B - Chip grinding method - Google Patents
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- CN112247825B CN112247825B CN202010924347.0A CN202010924347A CN112247825B CN 112247825 B CN112247825 B CN 112247825B CN 202010924347 A CN202010924347 A CN 202010924347A CN 112247825 B CN112247825 B CN 112247825B
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- 238000000227 grinding Methods 0.000 title claims abstract description 413
- 238000000034 method Methods 0.000 title claims abstract description 201
- 230000008569 process Effects 0.000 claims abstract description 162
- 239000004020 conductor Substances 0.000 claims abstract description 145
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000005498 polishing Methods 0.000 claims description 49
- 238000007517 polishing process Methods 0.000 claims description 35
- 230000004888 barrier function Effects 0.000 claims description 23
- 239000006227 byproduct Substances 0.000 claims description 18
- 238000004140 cleaning Methods 0.000 claims description 10
- 238000001514 detection method Methods 0.000 description 12
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- 239000002184 metal Substances 0.000 description 6
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention provides a chip grinding method, which comprises the following steps: providing a substrate to be ground, the grinding substrate comprising: a dielectric layer; the connecting groove and the additional groove are positioned in the dielectric layer; the conductive material layer is positioned inside the connecting groove and the additional groove and on the top surface of the dielectric layer; grinding and removing the conductive material layer higher than the top surface of the dielectric layer by adopting a first grinding process; grinding the dielectric layer on the side part of the additional groove by adopting a second grinding process, so that the conductive material layer in the additional groove area protrudes out of the dielectric layer; and removing the conductive material layer in the additional groove area by adopting a third grinding process. The chip grinding method can reduce the loss degree of the conductive material layer in the connecting groove.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a chip grinding method.
Background
A radio frequency chip (RF chip) refers to an electronic component that converts radio signal communication into a certain radio signal waveform and transmits the radio signal waveform through antenna resonance. In chip design, an mim (metal isolation metal) structure is introduced into a radio frequency chip to form a large capacitor structure, so as to transmit and receive radio frequency signals, thereby realizing a radio frequency function. The MIM structure is a sandwich structure consisting of three thin films of metal, insulator and metal.
The MIM structures are embedded into the dielectric layer, additional grooves are formed between the two MIM structures, connecting grooves are formed in the MIM structures, and after conducting conductive material deposition, conductive material layers are formed in the additional grooves, the connecting grooves and the top surface of the dielectric layer. Subsequently, the structure needs to be polished by a polishing process to remove the conductive material layer in the additional grooves. The polishing process is generally performed by Chemical Mechanical Polishing (CMP). The basic principle of chemical mechanical polishing is that under a certain pressure and the existence of grinding liquid, a workpiece to be polished rotates relative to a polishing pad, and the conductive material layer in the additional groove is removed by means of the mechanical grinding of abrasive particles and the corrosion of chemical oxidant, so that a smooth surface is obtained.
However, the conventional polishing method causes a large loss of the conductive material layer in the connecting groove.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defect of the conventional chip grinding method that the conductive material layer in the connecting groove is damaged to a greater extent, thereby providing a chip grinding method.
Therefore, the invention provides a chip grinding method, which comprises the following steps:
providing a substrate to be ground, the grinding substrate comprising: a dielectric layer; the connecting groove and the additional groove are positioned in the dielectric layer; the conductive material layer is positioned inside the connecting groove and the additional groove and on the top surface of the dielectric layer;
grinding and removing the conductive material layer higher than the top surface of the dielectric layer by adopting a first grinding process;
grinding the dielectric layer on the side part of the additional groove by adopting a second grinding process, so that the conductive material layer in the additional groove area protrudes out of the dielectric layer;
and removing the conductive material layer in the additional groove area by adopting a third grinding process.
Optionally, the chip grinding method further includes: and after the third grinding process is carried out, removing the medium layers with partial thicknesses on the two sides of the connecting groove by adopting a fourth grinding process, so that the top surface of the conductive material layer in the connecting groove is flush with the top surface of the medium layer, or the top surface of the conductive material layer in the connecting groove is higher than the top surface of the medium layer.
Optionally, the grinding pressure applied to the substrate to be ground by the third grinding process is less than or equal to the grinding pressure applied to the substrate to be ground by the first grinding process.
Optionally, the second grinding process has a grinding rate of
The grinding time is 60-300 s;
the third grinding process has a grinding rate of
The grinding time is 20s to 150 s.
Optionally, the first polishing process includes a first sub-polishing process and a second sub-polishing process, which are sequentially performed, and a polishing rate of the second sub-polishing process is smaller than a polishing rate of the first sub-polishing process.
Optionally, in the second sub-grinding process, the grinding pressure applied to the substrate to be ground is smaller than the grinding pressure applied to the substrate to be ground in the first sub-grinding process.
Optionally, the grinding pressure of the first sub-grinding process is 2.5PSI-4 PSI; and the grinding pressure applied in the second sub-grinding process is 1PSI-3 PSI.
Optionally, the overpolishing time of the first grinding process is 5s to 50 s.
Optionally, the chip grinding method further includes: and cleaning the by-products on the surface of the grinding pad during the first grinding process, the second grinding process and the third grinding process.
Optionally, the abrasive substrate further comprises: the barrier layers are positioned on the side walls and the bottom surfaces of the connecting grooves, the side walls and the bottom surfaces of the additional grooves and the top surface of the dielectric layer, and the conductive material layer is positioned on the barrier layers;
the first grinding process grinds the conductive material layer until the barrier layer on the top surface of the dielectric layer is exposed;
the second grinding process also removes the barrier layer on the side wall of the additional groove;
the fourth grinding process also removes the barrier layer at the bottom of the additional trench region.
Optionally, the chip is a radio frequency chip; the substrate to be ground further comprises: MIM structure located at the bottom of the dielectric layer, the connecting groove is located above the MIM structure, and the additional groove is located at the top region of the dielectric layer between the adjacent MIM structures.
The technical scheme of the invention has the following advantages:
1. the chip grinding method provided by the invention comprises the steps of firstly removing the conductive material layer higher than the top surface of the dielectric layer through a first grinding process, then enabling the conductive material layer filled in the additional groove to protrude out of the dielectric layer through a second grinding process, enabling the top area of the conductive material layer inside the connecting groove to correspondingly protrude out of the dielectric layer after the second grinding process is completed, and then removing the conductive material layer in the additional groove area through a third grinding process. Since the conductive material layer in the additional groove protrudes from the dielectric layer before the third polishing process, during the third polishing process, the polishing pressure can be directly applied to the conductive material layer in the additional groove, the polishing pad is in sufficient contact with the conductive material layer, so that the third grinding process simultaneously plays a role in chemical etching and mechanical grinding in the process of removing the conductive material layer in the additional groove, the defect of weak mechanical grinding effect caused by the fact that the conductive material layer in the additional groove cannot be directly contacted with the grinding pad in the conventional grinding method is avoided, the grinding speed of the conductive material layer in the additional groove is improved, and the third grinding process can grind the top surface and the side wall of the conductive material layer in the additional groove at the same time, so that the conductive material layer in the additional groove can be removed easily, and the grinding time of the conductive material layer in the additional groove is shortened. Because the top region of the conductive material layer in the connecting groove protrudes out of the medium layer before the third grinding process, in the process of the third grinding process, grinding pressure can be directly applied to the conductive material layer in the connecting groove, the grinding pad is in full contact with the conductive material layer, so that in the process of removing the conductive material layer in the connecting groove in the third grinding process, the top surface of the conductive material layer in the connecting groove is ground, the side wall of the conductive material layer in the connecting groove is also ground, the grinding rate of the edge region of the conductive material layer in the connecting groove is close to that of the central region, and excessive depression of the central region relative to the edge region is avoided. Because the time for removing the conductive material layer in the additional groove is short, and the conductive material layer in the connecting groove is prevented from being sunken, the loss degree of the conductive material layer in the connecting groove can be reduced.
2. According to the chip grinding method provided by the invention, after the third grinding process is carried out, the medium layers with partial thicknesses on the two sides of the connecting groove are removed by adopting a fourth grinding process, so that the top surface of the conductive material layer in the connecting groove is flush with the top surface of the medium layer, or the top surface of the conductive material layer in the connecting groove is higher than the top surface of the medium layer, so that the conductive material layer in the connecting groove is fully contacted with other structures to be electrically connected, the conductive material layer in the connecting groove is favorably electrically connected with other structures, and the phenomenon of broken circuit is avoided.
3. According to the chip grinding method provided by the invention, in the process of carrying out the first grinding process, the first sub-grinding process is used for removing most of the thickness of the conductive material layer higher than the top surface of the dielectric layer at a high grinding speed, and then the second sub-grinding process is used for removing the rest conductive material layer higher than the top surface of the dielectric layer at a low grinding speed, so that the average grinding speed of the first grinding process is improved, the grinding time of the first grinding process is shortened, and the grinding efficiency is improved; meanwhile, the lower grinding rate of the second sub-grinding process is beneficial to controlling the grinding endpoint.
4. According to the chip grinding method provided by the invention, the grinding pressure exerted on the substrate to be ground in the second sub-grinding process is limited to be smaller than the grinding pressure exerted on the substrate to be ground in the first sub-grinding process, so that the grinding rate of the second sub-grinding process is smaller than that of the first sub-grinding process; meanwhile, the first sub-grinding process is carried out at a higher grinding pressure to enable different areas of the substrate to be ground to have smaller thickness difference, and then the second sub-grinding process is carried out at a lower grinding pressure to enable the grinding surface of the substrate to be ground to have lower roughness, namely, the first sub-grinding process and the second sub-grinding process are matched with each other to obtain the grinding surface with higher grinding precision and higher flatness, so that the grinding effect of the subsequent grinding process is favorably ensured.
5. According to the chip grinding method provided by the invention, the conductive material layer in each area of the surface of the top of the dielectric layer in the substrate to be ground can be completely removed by grinding for 5-50 s in the first grinding process, so that the overall grinding effect of the substrate to be ground and the flatness of the ground substrate to be ground are improved.
6. The chip grinding method provided by the invention is going onIn the first grinding process, the second grinding process and the third grinding process, the grinding byproducts on the surface of the grinding pad are cleaned, so that the stability of the grinding rate is ensured, the problems of reduction of the grinding rate and instability of the grinding rate caused by the fact that the grinding byproducts fill the holes of the grinding pad and are deposited on the surface of the grinding pad are solved, and the thickness difference of the same substrate to be ground can be controlled to be within the range
Therefore, the flatness of the substrate to be ground after grinding is improved.
7. According to the chip grinding method provided by the invention, the grinding pressure of the third grinding process is less than or equal to the grinding pressure of the second sub-grinding process. And performing a third grinding process at a lower grinding pressure to make the surfaces of the conductive material layers inside the connecting groove and the additional groove have lower roughness and reduce the loss degree of the conductive material layers inside the connecting groove.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIGS. 1 and 2 are schematic views of a structure in a chip grinding process;
FIG. 3 is a schematic flow chart illustrating a method for polishing a wafer according to an embodiment of the present invention;
fig. 4 to 9 are schematic structural diagrams of a chip grinding process according to an embodiment of the invention.
Detailed Description
A method of grinding a chip, comprising: referring to fig. 1, there is provided a radio frequency chip including: the lower dielectric layer 9 ', a plurality of lower conductive material layers 7 ' embedded into the lower dielectric layer 9 ', a lower barrier layer 8 ' arranged between the lower dielectric layer 9 ' and the lower conductive material layers 7 ', an MIM structure 1 ' and a dielectric layer 2 ' arranged on the lower conductive material layer 7 ', a connecting groove 3 ' arranged on the MIM structure 1 ', an additional groove 4 ' arranged between adjacent MIM structures 1 ', a conductive material layer 5 ' arranged inside the connecting groove 3 ' and the additional groove 4 ' and on the top surface of the dielectric layer 2 ', and the MIM structure 1 ' comprises a conductive upper polar plate 11 ', a middle dielectric layer 12 ' and a conductive lower polar plate 13 ' which are arranged in a stacked mode; referring to fig. 2, the conductive material layer is polished at a certain polishing rate, and after the conductive material layer higher than the top surface of the dielectric layer is removed, the conductive material layer in the additional groove in the rf chip is removed completely by continuing the polishing for a certain time.
In the preparation process of the radio frequency chip, firstly, the MIM structures 1 ' are formed on the lower conductive material layer 7 ', and a groove is formed between the adjacent MIM structures 1 ', so that an additional groove 4 ' located in the top region of the dielectric layer is formed between the two MIM structures 1 ' after the subsequent dielectric layer is deposited, and then, after the conductive material layer is deposited, the additional groove is also filled with the conductive material layer.
The research finds that, because the materials of the dielectric layer and the conductive material layer are different, in the process of grinding the conductive material layer in the additional groove, the grinding rate of the dielectric layer is far less than that of the conductive material layer, even the dielectric layer is not ground basically, so that the conductive material layer in the additional groove is not flush with the surface of the adjacent dielectric layer, and the conductive material layer in the additional groove cannot be in effective contact with the grinding pad due to the blocking of the dielectric layer. Secondly, in the process of grinding the conductive material layer in the additional groove, part of the conductive material layer in the connecting groove is also ground together, and when the conductive material layer in the additional groove is completely removed, the conductive material layer in the connecting groove forms a deeper groove due to the lifting defect. The longer grinding time and the disturbing defect of the conductive material layer in the connection groove cause a larger degree of loss of the conductive material layer in the connection groove.
On the basis, the invention provides a chip grinding method, and with reference to fig. 3, the method comprises the following steps:
s1: providing a substrate to be ground, the grinding substrate comprising: a dielectric layer; the connecting groove and the additional groove are positioned in the dielectric layer; the conductive material layer is positioned inside the connecting groove, inside the additional groove and on the top surface of the dielectric layer;
s2: grinding and removing the conductive material layer higher than the top surface of the dielectric layer by adopting a first grinding process;
s3: grinding the medium layer positioned on the side part of the additional groove by adopting a second grinding process, so that the conductive material layer in the area of the additional groove protrudes out of the medium layer;
s4: and removing the conductive material layer in the area of the additional groove by adopting a third grinding process.
According to the chip grinding method, the conductive material layer higher than the top surface of the dielectric layer is removed through a first grinding process, then the conductive material layer filled in the additional groove protrudes out of the dielectric layer through a second grinding process, after the second grinding process is completed, the top area of the conductive material layer inside the connecting groove correspondingly protrudes out of the dielectric layer, and then the conductive material layer in the additional groove area is removed through a third grinding process. Since the conductive material layer in the additional groove protrudes from the dielectric layer before the third polishing process, during the third polishing process, the polishing pressure can be directly applied to the conductive material layer in the additional groove, the polishing pad is in sufficient contact with the conductive material layer, so that the third grinding process simultaneously plays a role in chemical etching and mechanical grinding in the process of removing the conductive material layer in the additional groove, the defect of weak mechanical grinding effect caused by the fact that the conductive material layer in the additional groove cannot be directly contacted with the grinding pad in the conventional grinding method is avoided, the grinding speed of the conductive material layer in the additional groove is improved, and the third grinding process can grind the top surface and the side wall of the conductive material layer in the additional groove at the same time, so that the conductive material layer in the additional groove can be removed easily, and the grinding time of the conductive material layer in the additional groove is shortened. Because the top region of the conductive material layer in the connecting groove protrudes out of the medium layer before the third grinding process, in the process of the third grinding process, grinding pressure can be directly applied to the conductive material layer in the connecting groove, the grinding pad is in full contact with the conductive material layer, so that in the process of removing the conductive material layer in the connecting groove in the third grinding process, the top surface of the conductive material layer in the connecting groove is ground, the side wall of the conductive material layer in the connecting groove is also ground, the grinding rate of the edge region of the conductive material layer in the connecting groove is close to that of the central region, and excessive depression of the central region relative to the edge region is avoided. Because the time for removing the conductive material layer in the additional groove is short, and the conductive material layer in the connecting groove is prevented from being sunken, the loss degree of the conductive material layer in the connecting groove can be reduced.
Referring to fig. 4 to 9, a chip grinding process according to an embodiment of the present invention will be described in detail.
Referring to fig. 5, a substrate to be ground is provided. The substrate to be ground includes: a dielectric layer 2; a connecting groove 3 (refer to fig. 4) and an additional groove 4 (refer to fig. 4) in the dielectric layer 2; a layer of conductive material 5 located inside the connection trenches, inside the additional trenches and on the top surface of the dielectric layer.
The forming process of the substrate to be ground comprises the following steps: referring to fig. 4, a dielectric layer 2 and a connection groove 3 and an additional groove 4 in the dielectric layer 2 are formed; referring to fig. 5, a layer of conductive material 5 is formed inside the connecting trenches, inside the additional trenches and on the top surface of the dielectric layer.
The chip of the embodiment is a radio frequency chip; the substrate to be ground further comprises: MIM structures 1 located at the bottom of dielectric layer 2, connection trenches 3 located above MIM structures 1, and additional trenches 4 located in the top region of the dielectric layer between adjacent MIM structures 1.
Specifically, the structure of the substrate to be ground comprises the following structures:
a lower dielectric layer 9;
a plurality of lower conductive material layers 7, wherein the lower conductive material layers 7 are embedded into the lower dielectric layer 9;
the lower barrier layer 8 is arranged between the lower dielectric layer 9 and the lower conductive material layer 7;
the MIM structure 1 is arranged on the lower conductive material layer 7, and the MIM structure 1 comprises a conductive upper polar plate 11, a middle dielectric layer 12 and a conductive lower polar plate 13 which are arranged in a stacked mode.
A dielectric layer 2 disposed on the lower conductive material layer 7 and embedded with the MIM structure 1, the dielectric layer 2 being made of materials including but not limited to SiO2、SiOC、SiON。
The connecting groove 3 is positioned in the dielectric layer 2 and positioned on the MIM structure 1;
and the additional groove 4 is positioned in the dielectric layer 2 and between two adjacent MIM structures 1, and the depth of the additional groove 4 is smaller than that of the connecting groove 3.
And a conductive material layer 5 located inside the connecting trench 3, inside the additional trench 4 and on the top surface of the dielectric layer 2, wherein the material of the conductive material layer 5 includes but is not limited to copper.
In addition, the abrasive substrate may further include: and the barrier layer 6 is positioned on the side wall and the bottom surface of the connecting groove 3, the side wall and the bottom surface of the additional groove 4 and the top surface of the dielectric layer 2, the conductive material layer 5 is positioned on the barrier layer 6, and the material of the barrier layer 6 comprises but is not limited to Ta, TaN, Co and TiN.
Referring to fig. 6, the conductive material layer 5 above the top surface of the dielectric layer 2 is removed by a first polishing process. When the polishing substrate further includes the barrier layer 6, the first polishing process polishes the conductive material layer until the barrier layer on the top surface of the dielectric layer is exposed.
The first grinding process adopts an end point detection method to obtain the grinding end point of the conductive material layer on the top surface of the dielectric layer, and the grinding is continued for 5-50 s after the conductive material layer is ground to the grinding end point. The end point detection method can detect the grinding degree of a certain area of the top surface of the dielectric layer so as to judge whether the conductive material layer in the area is completely removed, namely the grinding end point when the conductive material layer is completely removed, and the conductive material layer in each area of the top surface of the dielectric layer in the substrate to be ground can be completely removed by continuously grinding for 5-50 s after the conductive material layer is ground to the grinding end point, so that the overall grinding effect of the substrate to be ground and the flatness of the ground substrate after grinding are improved. In some embodiments, the over-grinding time may be 5s, 10s, 15s, 20s, 25s, 30s, 35s, 40s, 45s, 50s, and the endpoint detection method may be one of a motor current endpoint detection method, an eddy current endpoint detection method, and a comprehensive endpoint detection method.
The parameters of the first grinding process include: the grinding pressure is 1PSI-3PSI, the relative rotating speed of the grinding disc and the grinding head is 2-10 r/min, wherein the rotating speed of the grinding disc is 80-120 r/min, the rotating speed of the grinding head is 80-120 r/min, and the rotating directions of the grinding disc and the grinding head are the same; in some specific embodiments, the first grinding process may be performed with the following parameters: the rotation speed of the grinding disc is 93 revolutions per minute, the rotation speed of the grinding head is 87 revolutions per minute, and the grinding pressure is 2.5PSI pressure.
As a preferred embodiment, the first polishing process includes a first sub-polishing process and a second sub-polishing process sequentially performed, and the polishing rate of the second sub-polishing process is smaller than that of the first sub-polishing process. Firstly, removing most of the thickness of the conductive material layer on the top surface of the dielectric layer by a first sub-grinding process at a high grinding rate, and then removing the residual conductive material layer on the top surface of the dielectric layer by a second sub-grinding process at a low grinding rate, so that the average grinding rate of the first grinding process is improved, the grinding time of the first grinding process is shortened, and the grinding efficiency is improved; meanwhile, the lower grinding rate of the second sub-grinding process is beneficial to controlling the grinding end point, so that the excessive polishing degree is avoided. Specifically, the first sub-grinding process grinds away 85% of the total thickness of the conductive material layer on the top surface of the dielectric layer, when the total thickness of the conductive material layer on the top surface of the dielectric layer is
Then, the first sub-grinding process is ground off
The second sub-grinding process grinds away the rest
The relative rotating speeds of the grinding disc and the grinding head in the first sub-grinding process and the second sub-grinding process are the same, and the grinding pressure applied to the substrate to be ground in the second sub-grinding process is smaller than the grinding pressure applied to the substrate to be ground in the first sub-grinding process, so that the grinding rate of the second sub-grinding process is smaller than that of the first sub-grinding process; meanwhile, the first sub-grinding process is carried out on the substrate to be ground at a higher grinding pressure to enable different areas of the substrate to be ground to have smaller thickness difference, and the second sub-grinding process is carried out at a lower grinding pressure to enable the grinding surface of the substrate to be ground to have lower roughness, namely, the first sub-grinding process and the second sub-grinding process are matched with each other to obtain the grinding surface with higher grinding precision and higher flatness, and the grinding effect of the subsequent grinding process is favorably ensured.
Furthermore, the grinding pressure of the first sub-grinding process is 2.5PSI-4PSI, the grinding pressure applied in the second sub-grinding process is 1PSI-3PSI, the relative rotating speed of the grinding disc and the grinding head in the first sub-grinding process and the second sub-grinding process is 2-10 revolutions/min, the rotating speed of the grinding disc is 80-120 revolutions/min, the rotating speed of the grinding head is 80-120 revolutions/min, and the rotating directions of the grinding disc and the grinding head are the same. In some embodiments, in the first sub-polishing process and the second sub-polishing process, the rotation speed of the polishing disc is 93 rpm, the rotation speed of the polishing head is 87 rpm, the polishing pressure of the first sub-polishing process is 3.5PSI, and the polishing pressure of the second sub-polishing process is 2.5 PSI.
When the conductive material layer 5 is made of metal, the first sub-grinding process can monitor the grinding end point through an electromagnetic end point detection system; the second sub-grinding process can monitor the grinding end point through one of optical end point detection, motor current end point detection, eddy current end point detection and comprehensive end point detection methods, and when the conductive material layer 5 is made of metal, the result of monitoring the grinding end point through the optical end point detection is more accurate.
In addition, the method also comprises a step of cleaning the grinding byproducts on the surface of the grinding pad in the process of carrying out the first grinding process. By cleaning the by-product, the stability of the grinding rate is ensured to avoid the problem of the by-productThe problems of low grinding rate and unstable grinding rate caused by the grinding by-products filling the holes of the grinding pad and depositing on the surface of the grinding pad can control the thickness difference of the same substrate to be ground to be equal to
Therefore, the flatness of the substrate to be ground after grinding is improved. Specifically, the first grinding process may use a non-woven fabric polishing pad with low hardness, and the polishing pad is combed (carded in advance) with a brush before grinding, and the polishing pad is washed with high pressure water for 10s to 30s every 30s to 60s of grinding.
Referring to fig. 7, the dielectric layer 2 at the side of the additional groove 4 is polished using a second polishing process such that the conductive material layer 5 in the additional groove region protrudes from the dielectric layer 2. When the grinding substrate further comprises the barrier layer 6, the second grinding process also removes the barrier layer of the additional trench sidewalls.
The second grinding process has a grinding rate of
The grinding time of the second grinding process is 60-300 s. And obtaining the preset grinding time of the second grinding process according to the depth of the additional groove 4 and the preset grinding rate of the second grinding process, grinding at the preset grinding rate of the second grinding process, timing, and stopping grinding when the actual grinding time is equal to the preset grinding time.
Further, the parameters of the second grinding process include: the grinding pressure is 1PSI-3PSI, the relative rotating speed of the grinding disc and the grinding head is 2-10 r/min, wherein the rotating speed of the grinding disc is 80-120 r/min, the rotating speed of the grinding head is 80-120 r/min, and the rotating directions of the grinding disc and the grinding head are the same.
In addition, the second grinding process also comprises a step of cleaning grinding byproducts on the surface of the grinding pad. By cleaning the by-products, the stability of the grinding rate is ensured, so that the reduction of the grinding rate and the instability of the grinding rate caused by the fact that the grinding by-products fill the holes of the grinding pad and are deposited on the surface of the grinding pad are avoidedThe thickness difference of the same substrate to be ground can be controlled to
Therefore, the flatness of the substrate to be ground after grinding is improved. Specifically, the second polishing process may use a polyurethane polishing pad having a slightly higher hardness, place the polishing pad on a diamond polishing disk, and perform carding (insitu, synchronous carding) while polishing with a carding tool provided on a machine table, and simultaneously wash the polishing pad with high-pressure water for 10s to 30s every 30s to 60s of polishing.
Referring to fig. 8, a third grinding process is used to remove the conductive material layer 5 in the region of the additional grooves 4. When the polishing substrate further comprises the barrier layer 6, the third polishing process polishes the layer of conductive material until the barrier layer at the bottom of the additional trench region is exposed.
The third grinding process has a grinding rate of
The grinding time of the third grinding process is 20-150 s. And obtaining the preset grinding time of the third grinding process according to the depth of the conductive material layer 5 in the additional groove and the preset grinding rate of the third grinding process, grinding at the preset grinding rate of the third grinding process, timing, and stopping grinding when the actual grinding time is equal to the preset grinding time.
In addition, the grinding pressure exerted by the third grinding process on the substrate to be ground is less than or equal to the grinding pressure exerted by the first grinding process on the substrate to be ground. Specifically, the grinding pressure exerted by the third grinding process on the substrate to be ground is less than or equal to the grinding pressure exerted by the second sub-grinding process on the substrate to be ground. The third grinding process at a lower grinding pressure causes the surfaces of the conductive material layer 5 inside the connecting groove 3 and inside the additional groove 4 to have a lower roughness and reduces the degree of loss of the conductive material layer 5 inside the connecting groove 3.
Further, the parameters of the third grinding process include: the grinding pressure is 1PSI-3PSI, the relative rotating speed of the grinding disc and the grinding head is 2-10 r/min, wherein the rotating speed of the grinding disc is 80-120 r/min, the rotating speed of the grinding head is 80-120 r/min, and the rotating directions of the grinding disc and the grinding head are the same. In some embodiments, the parameters of the third polishing process include: the rotation speed of the grinding disc is 93 revolutions per minute, the rotation speed of the grinding head is 87 revolutions per minute, and the grinding pressure is 2.5PSI pressure.
In addition, the third polishing process further comprises a step of cleaning the polishing by-products on the surface of the polishing pad. By cleaning the by-products, the stability of the grinding rate is ensured, the problems of reduction of the grinding rate and instability of the grinding rate caused by filling the grinding by-products into the holes of the grinding pad and depositing the grinding by-products on the surface of the grinding pad are solved, and the thickness difference of the same substrate to be ground can be controlled to the range from
Therefore, the flatness of the substrate to be ground after grinding is improved. Specifically, the third grinding process may use a non-woven fabric polishing pad with a lower hardness, and the polishing pad is carded (previously carded) with a brush before grinding, and the polishing pad is washed with high pressure water for 10s to 30s every 30s to 60s of grinding.
Referring to fig. 9, the chip grinding method provided in this embodiment further includes: after the third grinding process is carried out, the dielectric layers 2 with partial thicknesses on two sides of the connecting groove are removed by adopting a fourth grinding process, so that the top surface of the conductive material layer 5 in the connecting groove 3 is higher than that of the dielectric layers 2, the conductive material layer in the connecting groove is fully contacted with other structures to be electrically connected, the conductive material layer in the connecting groove is favorably electrically connected with other structures, and the phenomenon of broken circuit is avoided. When the ground substrate further comprises the barrier layer 6, the fourth grinding process also removes the barrier layer at the bottom of the additional trench region.
It should be understood that the fourth polishing process may also make the top surface of the conductive material layer in the connecting groove flush with the top surface of the dielectric layer, so that the conductive material layer 5 in the connecting groove is fully contacted with other structures to be electrically connected, thereby facilitating the electrical connection between the conductive material layer in the connecting groove and other structures and avoiding causing open circuit.
Grinding by the fourth grinding processAt a rate of
The grinding time of the fourth grinding process is 60-150 s, and the grinding thickness of the medium layer 2 is
And obtaining the preset grinding time of the fourth grinding process according to the preset grinding thickness of the medium layer and the preset grinding rate of the fourth grinding process, grinding at the preset grinding rate of the fourth grinding process, timing, and stopping grinding when the actual grinding time is equal to the preset grinding time. In some embodiments, the fourth polishing process polishes the dielectric layer 2 to a thickness of
Further, the parameters of the fourth grinding process include: the grinding pressure is 1PSI-3PSI, the relative rotating speed of the grinding disc and the grinding head is 2-10 r/min, wherein the rotating speed of the grinding disc is 80-120 r/min, the rotating speed of the grinding head is 80-120 r/min, and the rotating directions of the grinding disc and the grinding head are the same.
In addition, the fourth polishing process further includes a step of cleaning polishing by-products on the surface of the polishing pad. By cleaning the by-products, the stability of the grinding rate is ensured, the problems of reduction of the grinding rate and instability of the grinding rate caused by filling the grinding by-products into the holes of the grinding pad and depositing the grinding by-products on the surface of the grinding pad are solved, and the thickness difference of the same substrate to be ground can be controlled to the range from
Therefore, the flatness of the substrate to be ground after grinding is improved. Specifically, the fourth polishing process may use a polyurethane polishing pad with a slightly higher hardness, place the polishing pad on a diamond polishing disk, and perform carding (insitu, synchronous carding) while polishing with a carding tool provided on a machine table, and simultaneously wash the polishing pad with high-pressure water for 10s to 30s every 30s to 60s of polishing.
In other embodiments, the fourth grinding process may not be performed.
It should be understood that the grinding method provided in the present embodiment is not only applicable to rf chips, but other types or structures of chips may also use the grinding method.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. A chip grinding method is characterized by comprising the following steps:
providing a substrate to be ground, the grinding substrate comprising: a dielectric layer; the connecting groove and the additional groove are positioned in the dielectric layer; the conductive material layer is positioned inside the connecting groove and the additional groove and on the top surface of the dielectric layer;
grinding and removing the conductive material layer higher than the top surface of the dielectric layer by adopting a first grinding process;
grinding the dielectric layer on the side part of the additional groove and the dielectric layer with partial thickness on the side part of the connecting groove by adopting a second grinding process, so that the conductive material layer of the additional groove area and the top area of the conductive material layer of the connecting groove area protrude out of the dielectric layers;
and removing the conductive material layer of the additional groove region by adopting a third grinding process, wherein the connecting groove region protrudes out of the conductive material layer of the dielectric layer after the second grinding process.
2. The chip grinding method according to claim 1, further comprising: and after the third grinding process is carried out, removing the medium layers with partial thicknesses on the two sides of the connecting groove by adopting a fourth grinding process, so that the top surface of the conductive material layer in the connecting groove is flush with the top surface of the medium layer, or the top surface of the conductive material layer in the connecting groove is higher than the top surface of the medium layer.
3. The wafer polishing method according to claim 1, wherein the polishing pressure applied to the substrate to be polished by the third polishing process is equal to or less than the polishing pressure applied to the substrate to be polished by the first polishing process.
4. The chip grinding method according to claim 1,
the second grinding process has a grinding rate of
The grinding time is 60-300 s;
the third grinding process has a grinding rate of
The grinding time is 20s-150 s.
5. The method for grinding the chip according to claim 1, wherein the first grinding process comprises a first sub-grinding process and a second sub-grinding process which are sequentially performed, and the grinding rate of the second sub-grinding process is smaller than that of the first sub-grinding process.
6. The wafer polishing method according to claim 5, wherein the polishing pressure applied to the substrate to be polished in the second sub-polishing process is smaller than the polishing pressure applied to the substrate to be polished in the first sub-polishing process.
7. The method for grinding chips according to claim 1, wherein the first grinding process has an overpolish time of 5s to 50 s.
8. The chip grinding method according to claim 1, further comprising: and cleaning the by-products on the surface of the grinding pad during the first grinding process, the second grinding process and the third grinding process.
9. The chip grinding method according to claim 2,
the abrasive substrate further comprises: the barrier layers are positioned on the side walls and the bottom surfaces of the connecting grooves, the side walls and the bottom surfaces of the additional grooves and the top surface of the dielectric layer, and the conductive material layer is positioned on the barrier layers;
the first grinding process grinds the conductive material layer until the barrier layer on the top surface of the dielectric layer is exposed;
the second grinding process also removes the barrier layer on the side wall of the additional groove;
the fourth grinding process also removes the barrier layer at the bottom of the additional trench region.
10. The chip grinding method according to any one of claims 1 to 9, wherein the chip is a radio frequency chip; the substrate to be ground further comprises: MIM structure located at the bottom of the dielectric layer, the connecting groove is located above the MIM structure, and the additional groove is located at the top region of the dielectric layer between the adjacent MIM structures.
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Address after: 100176 101, floor 2, building 2, No. 1, Taihe Third Street, economic and Technological Development Zone, Daxing District, Beijing Patentee after: Beijing Jingyi Precision Technology Co.,Ltd. Address before: No.1, Taihe Third Street, economic and Technological Development Zone, Daxing District, Beijing, 100176 Patentee before: Beijing ShuoKe precision electronic equipment Co.,Ltd. |