Summary of the invention
The invention provides a kind of method and tungsten plug manufacture method of chemical mechanical polishing of tungsten, the present invention can reduce the defective of depression when making tungsten plug.
A kind of tungsten chemical mechanical polishing method provided by the invention comprises:
Semiconductor structure with dielectric layer is provided, in described dielectric layer, has opening, on described opening neutralization medium layer, have metal barrier and tungsten metal level successively;
Carry out the phase I cmp, remove the tungsten metal level of the segment thickness on the described dielectric layer;
Carry out the second stage cmp, remove remaining tungsten metal level and metal barrier on the described dielectric layer;
Carry out the phase III cmp, remove the dielectric layer of segment thickness.
Optionally, described phase I cmp, second stage cmp and phase III cmp carry out on similar and different abrasive disk.
Optionally, carry out the phase I during cmp, control remaining tungsten metal layer thickness on the described dielectric layer by the time.
Optionally, finish the phase I cmp after, remaining tungsten metal layer thickness is the sixth to ten 4/5ths of tungsten metal layer thickness before this phase I cmp on the described dielectric layer.
Optionally, the lapping liquid of described phase I cmp is W2585.
Optionally, the time of described phase I cmp is 35 to 45s.
Optionally, the lapping liquid of described second stage cmp is identical with the lapping liquid of phase I cmp.
Optionally, the time of described phase III cmp is 5 to 15s.
Optionally, described metal barrier is a kind of or combination in titanium, titanium nitride, tantalum, the tantalum nitride.
Optionally, also have hard mask layer on the described dielectric layer, under the metal barrier, after finishing the second stage cmp, carry out before the phase III cmp, carrying out the grinding technics of removing hard mask layer.
Optionally, further comprise: after finishing the phase III cmp, the surface of described Semiconductor substrate is cleaned.
The present invention also provides a kind of manufacture method of tungsten plug, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, has dielectric layer;
In described dielectric layer, form contact hole;
On described contact hole neutralization medium layer, form metal barrier;
On described metal barrier, form the tungsten metal level;
Carry out the phase I cmp, remove the tungsten metal level of the segment thickness on the described dielectric layer;
Carry out the second stage cmp, remove remaining tungsten metal level and metal barrier on the described dielectric layer;
Carry out the phase III cmp, remove the dielectric layer of segment thickness.
Optionally, carry out the phase I during cmp, control remaining tungsten metal layer thickness on the described dielectric layer by the time.
Optionally, finish the phase I cmp after, remaining tungsten metal layer thickness is the sixth to ten 4/5ths of tungsten metal layer thickness before this phase I cmp on the described dielectric layer.
Optionally, the lapping liquid of described phase I cmp is W2585.
Optionally, the time of described phase I cmp is 35 to 45s.
Optionally, the lapping liquid of described second stage cmp is identical with the lapping liquid of phase I cmp.
Optionally, the time of described phase III cmp is 5 to 15s.
Optionally, described metal barrier is a kind of or combination in titanium, titanium nitride, tantalum, the tantalum nitride.
Optionally, further comprise:
Before forming contact hole, on dielectric layer, form hard mask layer;
And after finishing the second stage cmp, before the phase III cmp, carry out the grinding technics of removing hard mask layer.
Compared with prior art, technique scheme has the following advantages:
Among the present invention, will carry out at twice, promptly in the phase I chemical mechanical milling tech, needn't remove the tungsten metal level on the described dielectric layer fully, but keep certain thickness T the grinding of tungsten metal level
2The tungsten metal level, this T
2When waiting until the second stage cmp, removes the tungsten metal level of thickness, and pressure is less during the second stage cmp, can in metal barrier, not form the defective of depression, and then behind the second stage cmp removal metal barrier, can not form depression yet, thereby after finishing the phase III cmp, can in dielectric layer, not form the defective of depression, thereby the problem that the plain conductor that has reduced or eliminated tungsten plug and back layer opens circuit has improved the stability of the device that forms.
The specific embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 9 is the flow chart of the embodiment of tungsten chemical mechanical polishing method of the present invention.Figure 10 to Figure 13 is the relevant cross-sectional view of each step of embodiment with tungsten chemical mechanical polishing method of the present invention.
As shown in Figure 9, step S100 provides the semiconductor structure with dielectric layer, has opening in described dielectric layer, has metal barrier and tungsten metal level successively on described opening neutralization medium layer.
Figure 10 is the cross-sectional view with semiconductor structure of dielectric layer.
Please in conjunction with shown in Figure 10, semiconductor structure 100 is provided, described semiconductor structure 100 has dielectric layer 102, in described dielectric layer 102, has opening 103, on described opening 103 inwalls and described dielectric layer 102, has metal barrier 104, be coated with tungsten metal level 106 on described metal barrier 104, the tungsten metal level fills up opening 103 at least.
Wherein, has Semiconductor substrate (figure do not show) and be positioned at semiconductor devices (scheming not show) on the described Semiconductor substrate in the described semiconductor structure 100;
The material of described Semiconductor substrate can be a kind of in monocrystalline silicon, polysilicon, the non-crystalline silicon, also can be silicon Germanium compound, can also have silicon on the insulating barrier (Silicon On Insulator, SOI) epitaxial layer structure on structure or the silicon;
Described semiconductor devices is the metal oxide semiconductor device with grid, source electrode and drain electrode.
Described dielectric layer 102 is a kind of in the dielectric materials such as silica, silicon nitride, silicon oxynitride, carbon oxygen silicon compound, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass.
Described opening 103 is contact hole (contact hole) or attachment plug (via), if described opening 103 is a contact hole, source electrode or the grid or the drain electrode of metal oxide semiconductor device exposed in the bottom of then described opening 103; If described opening 103 is an attachment plug, the metal interconnecting wires of these dielectric layer 102 lower floors is exposed in the bottom of then described opening 103, and this metal interconnecting wires can be copper or aluminium or aluminium copper.
The method that forms described opening 103 is a chemical wet etching technology, and its key step is as follows: spin coating photoresist layer on described dielectric layer 102 (figure does not show), and graphical described photoresist layer forms patterns of openings; The dielectric layer 102 of the described patterns of openings of etching bottom is transferred to described patterns of openings in the dielectric layer 102, forms opening 103; Remove described photoresist layer.
Described metal barrier 104 is a kind of in titanium, tantalum nitride, titanium and titanium nitride, tantalum, tantalum nitride, tantalum and the tantalum nitride.Described metal barrier 104 is used for stoping follow-up tungsten in opening 103 depositions to spread in described dielectric layer 102, and improves the adhesiveness between tungsten and the dielectric layer 102.
The method that forms described metal barrier 104 is a physical vapour deposition (PVD).
Described tungsten metal level 106 fills up described opening 103 at least.The method that forms described tungsten metal level 106 is a low-pressure chemical vapor deposition.
The thickness of the tungsten metal level 106 on described dielectric layer 102 is T
1
Step S110 carries out the phase I cmp, removes the tungsten metal level of the segment thickness on the described dielectric layer.
Figure 11 is to the cross-sectional view behind the structure execution phase I cmp shown in Figure 10.
As shown in figure 11, described tungsten metal level 106 is carried out the phase I cmp, remove the tungsten metal level of described dielectric layer 102 top thickness, and on described dielectric layer 102, keep T
2The tungsten metal level 106a of thickness; Wherein, control the removed thickness of described tungsten metal level by milling time.
Wherein, the thickness T of reservation
2Can not be too thin, approached very much the defective that is easy to generate depression, can not be too thick, the too thick time that can increase follow-up second stage cmp.Among the embodiment therein, described T
2Be T
1Sixth to ten 4/5ths.
Among the embodiment therein, the lapping liquid of described phase I cmp is W2585, and milling time is 35 to 45s.
Step S120 carries out the second stage cmp, removes remaining tungsten metal level and metal barrier on the described dielectric layer.
Figure 12 is to the cross-sectional view behind the structure execution second stage cmp shown in Figure 10.
As shown in figure 12, described remaining tungsten metal level 106a and metal barrier 104 are carried out the second stage cmp, remove remaining tungsten metal level 106a and metal barrier 104 on the described dielectric layer 102.
Remove on the described dielectric layer 102 behind the remaining tungsten metal level 106a and metal barrier 104, keep metal barrier 104a and tungsten metal level 106b in the described opening 103, formation comprises the tungsten plug of metal barrier 104a and tungsten metal level 106b, and this connector can be attachment plug or contact plunger.
In described second stage chemical mechanical milling tech, at first with described metal barrier 104 as the grinding endpoint detection layers, remove remaining tungsten metal level 106a on the described dielectric layer 102 by grinding, continue then to grind described metal barrier 104, the metal barrier on described dielectric layer 102 is removed.
Wherein, described second stage cmp is identical with the lapping liquid of phase I cmp, described lapping liquid has different grinding rates to tungsten metal level and metal barrier, and the tungsten metal level is had grinding rate faster, and metal barrier is had slower grinding rate.Slower grinding rate helps to control the thickness that grinds removal, thereby can reduce to form the defective of depression.
For example, the lapping liquid of described second stage cmp and phase I cmp is W2585.
Described second stage cmp and phase I cmp can carry out on identical or different grinding pad.To grind on different grinding pads is example, milling apparatus with first grinding pad and second grinding pad is provided, at first, with semiconductor structure 100 place first grinding pad on first grinding head on, first grinding head adsorbs the back side of described semiconductor structure 100, and exert pressure downwards, make tungsten metal level 106 contact the surface of first grinding pad downwards, feeding lapping liquid at described tungsten metal level 106 surfaces and first grinding pad, rotate described first grinding head and first grinding pad, grind described tungsten metal level 106 by lapping liquid, the corrosiveness of chemical composition in the mechanism of the middle particle by lapping liquid and the lapping liquid, make the thickness of described tungsten metal level 106 reduce, control the tungsten metal level 106 remaining thickness of wanting on the described dielectric layer 102 by control grinding rate and milling time;
After finishing the phase I cmp, unload this semiconductor structure 100 by first grinding head, and this semiconductor structure 100 placed on second grinding head on second grinding pad, the method same with the phase I cmp, described residue tungsten metal level 106a and metal barrier 104 are carried out the second stage cmp, in this second stage cmp formula, the pressure that puts on described second grinding head is less than the pressure that puts on first grinding head.
Because in the phase I chemical mechanical milling tech, the pressure that puts on grinding head is bigger, thereby, for avoiding this grinding head when being ground to metal barrier, the metal barrier overmastication is formed depression, will the grinding of tungsten metal level be carried out at twice, promptly in the phase I chemical mechanical milling tech, needn't remove the tungsten metal level on the described dielectric layer 102 fully, but keep certain thickness T
2The tungsten metal level, this T
2When waiting until the second stage cmp, removes the tungsten metal level of thickness, and pressure is less during the second stage cmp, can in metal barrier, not form the defective of depression, and then behind the second stage cmp removal metal barrier, can not form depression yet, thereby after finishing the phase III cmp, can in dielectric layer, not form the defective of depression, thereby the problem that the plain conductor that has reduced or eliminated tungsten plug and back layer opens circuit has improved the stability of the device that forms.
Step S130 carries out the phase III cmp, removes the dielectric layer of segment thickness.
Figure 13 is to the cross-sectional view behind the structure execution phase III cmp shown in Figure 10.
As shown in figure 13,, remove the dielectric layer 102 of segment thickness,, can make tungsten metal level 106b and dielectric layer 102 have more smooth surface by the phase III cmp by the phase III cmp.
In described phase III chemical mechanical milling tech, control the thickness of the dielectric layer of removing 102 by milling time.
Among the embodiment therein, the time of the cmp of described phase III is 5s to 15s.
Described phase III chemical grinding grinds and can carry out on the identical abrasive disk or carry out on different abrasive disks with second stage.
Described phase III cmp, second stage cmp and phase I cmp can carry out on identical or different abrasive disk.
In other enforcement, also have hard mask layer on the described dielectric layer, under the metal barrier, silicon nitride layer for example, thereby after finishing the second stage cmp, also need to remove this hard mask layer, and then carry out the phase III chemical mechanical milling tech by cmp.
Further, finish the phase III cmp after, need clean the surface of described semiconductor structure, described cleaning comprises that ultrasonic wave cleans and washed with de-ionized water.
The present invention also provides a kind of manufacture method of tungsten plug.In the manufacture method of the tungsten plug of inventing, at first in dielectric layer, form contact hole, form among metal barrier and tungsten metal level and the contact hole then and dielectric layer on, then tungsten metal level on the described dielectric layer and metal barrier are carried out first, second and phase III chemical mechanical milling tech, wherein, in carrying out the phase I chemical mechanical milling tech, remove the part tungsten metal level on the dielectric layer; In the second stage chemical mechanical milling tech, remove remaining tungsten metal level and metal barrier on the described dielectric layer; In the phase III chemical mechanical milling tech, remove the part dielectric layer.
Figure 14 is the flow chart of embodiment of the manufacture method of tungsten plug of the present invention.Figure 15 to Figure 20 is the generalized section with each step corresponding structure of the embodiment of the manufacture method of tungsten plug of the present invention.
As shown in figure 14, step S200 provides Semiconductor substrate, has dielectric layer on described Semiconductor substrate.
Sectional structure chart as shown in figure 15, Semiconductor substrate 200 is provided, has shallow trench isolation in the described Semiconductor substrate 200 from (figure does not show), on described Semiconductor substrate 200, has grid oxygen 203, on described grid oxygen 203, has grid 204, have side wall layer 206 in described grid 204 both sides, in the Semiconductor substrate 200 of described grid 204 both sides, have source electrode 202a and drain electrode 202b.
Also have dielectric layer 208 on described Semiconductor substrate 200, described dielectric layer 208 can be dielectric materials such as silica, silicon nitride, silicon nitride, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass.
Described dielectric layer 208 covers described grid 204 and source electrode 202a and drain electrode 202b.
Step S210 forms contact hole in described dielectric layer.
As shown in figure 16, form contact hole 210 in described dielectric layer 208, described source electrode 202a or drain electrode 202b or grid 204 are exposed in the bottom of described contact hole 210, and source electrode 202a is exposed in contact hole 210 bottoms shown in Figure 16.
The technology that forms contact hole 210 is as follows: at first, and spin coating photoresist layer on described dielectric layer 208, and by exposure imaging formation contact hole pattern; Then, the dielectric layer 208 of the described contact hole pattern of etching bottom is transferred to described contact hole pattern in the described dielectric layer, forms contact hole 210; Then, remove described photoresist layer by plasma ashing and wet-cleaning.
Step S220 forms metal barrier on described contact hole neutralization medium layer.
Step S230 forms the tungsten metal level on described metal barrier.
As shown in figure 17, form metal barrier 212 on described contact hole 210 neutralization medium layers 208, described metal barrier 212 is a kind of in titanium, tantalum nitride, titanium and titanium nitride, tantalum, tantalum nitride, tantalum and the tantalum nitride.Described metal barrier 212 is used for stoping follow-up tungsten in contact hole 210 depositions to spread in described dielectric layer 208, and improves the adhesiveness between described tungsten and the dielectric layer 208.
The method that forms described metal barrier 212 is a physical vapour deposition (PVD).
Then, form tungsten metal level 214 on described metal barrier 212, described tungsten metal level 214 fills up described contact hole 210 at least, and the method that forms tungsten metal level 214 is a low-pressure chemical vapor deposition.The thickness of the tungsten metal level 214 on described dielectric layer 208 is T
1
Step S240 carries out the phase I cmp, removes the tungsten metal level of the segment thickness on the described dielectric layer.
As shown in figure 18, described tungsten metal level 214 is carried out the phase I cmp, remove the tungsten metal level of described dielectric layer 208 top thickness, and on described dielectric layer 208, keep T
2The tungsten metal level 214a of thickness wherein, controls the removed thickness of described tungsten metal level by milling time.
Wherein, the thickness T of reservation
2Can not be too thin, approached very much the defective that is easy to generate depression, can not be too thick, the too thick time that can increase follow-up second stage cmp.Among the embodiment therein, described T
2Be T
1Sixth to ten 4/5ths.
Among the embodiment therein, the lapping liquid of described phase I cmp is W2585, and milling time is 35 to 45s.
Step S250 carries out the second stage cmp, removes remaining tungsten metal level and metal barrier on the described dielectric layer.
As shown in figure 19, described remaining tungsten metal level 214a and metal barrier 212 are carried out the second stage cmp, remove remaining tungsten metal level 214a and metal barrier 212 on the described dielectric layer 208.
Remove on the described dielectric layer 102 behind the remaining tungsten metal level 106a and metal barrier 104, keep metal barrier 212a and tungsten metal level 214b in the described contact hole 210, formation comprises the tungsten plug of metal barrier 212a and tungsten metal level 214b, and this connector can be attachment plug or contact plunger.
In described second stage chemical mechanical milling tech, at first with described metal barrier 212 as the grinding endpoint detection layers, remove remaining tungsten metal level 214a on the described dielectric layer 208 by grinding, continue then to grind described metal barrier 212, the metal barrier on described dielectric layer 208 is removed.
Wherein, described second stage cmp is identical with the lapping liquid of phase I cmp, described lapping liquid has different grinding rates to tungsten metal level and metal barrier, and the tungsten metal level is had grinding rate faster, and metal barrier is had slower grinding rate.Slower grinding rate helps to control the thickness that grinds removal, thereby can reduce to form the defective of depression.
For example, the lapping liquid of described second stage cmp and phase I cmp is W2585.
Described second stage cmp and phase I cmp can carry out on identical or different grinding pad.To grind on different grinding pads is example, milling apparatus with first grinding pad and second grinding pad is provided, at first, with Semiconductor substrate 200 place first grinding pad on first grinding head on, first grinding head adsorbs the back side of described Semiconductor substrate 200, and exert pressure downwards, make tungsten metal level 214 contact the surface of first grinding pad downwards, feeding lapping liquid at described tungsten metal level 214 surfaces and first grinding pad, rotate described first grinding head and first grinding pad, grind described tungsten metal level 214 by lapping liquid, the corrosiveness of chemical composition in the mechanism of the middle particle by lapping liquid and the lapping liquid, make the thickness of described tungsten metal level 214 reduce, control the tungsten metal level 214 remaining thickness of wanting on the described dielectric layer 208 by control grinding rate and milling time;
After finishing the phase I cmp, unload this Semiconductor substrate 200 by first grinding head, and this Semiconductor substrate 200 placed on second grinding head on second grinding pad, the method same with the phase I cmp, described residue tungsten metal level 214a and metal barrier 212 are carried out the second stage cmp, in this second stage cmp formula, the pressure that puts on described second grinding head is less than the pressure that puts on first grinding head.
Because in the phase I chemical mechanical milling tech, the pressure that puts on grinding head is bigger, thereby, for avoiding this grinding head when being ground to metal barrier, the metal barrier overmastication is formed depression, will the grinding of tungsten metal level be carried out at twice, promptly in the phase I chemical mechanical milling tech, needn't remove the tungsten metal level on the described dielectric layer 208 fully, but keep certain thickness T
2The tungsten metal level, this T
2When waiting until the second stage cmp, removes the tungsten metal level of thickness, and pressure is less during the second stage cmp, can in metal barrier, not form the defective of depression, and then behind the second stage cmp removal metal barrier, can not form depression yet, thereby after finishing the phase III cmp, can in dielectric layer, not form the defective of depression, thereby the problem that the plain conductor that has reduced or eliminated tungsten plug and back layer opens circuit has improved the stability of the device that forms.
Step S260 carries out the phase III cmp, removes the dielectric layer of segment thickness.
As shown in figure 20,, remove the dielectric layer 208 of segment thickness, so that the surface of described tungsten metal level 214b equals or a little more than the surface of described dielectric layer 208 by the phase III cmp.
In described phase III chemical mechanical milling tech, control the thickness of the dielectric layer of removing 208 by milling time.
Among the embodiment therein, the time of the cmp of described phase III is 5s to 15s.
Described phase III chemical grinding grinds and can carry out on the identical abrasive disk or carry out on different abrasive disks with second stage.
Described phase III cmp, second stage cmp and phase I cmp can carry out on identical or different abrasive disk.
In other enforcement, before forming contact hole, on dielectric layer, form hard mask layer, and after finishing the second stage cmp, before the phase III cmp, carry out the grinding technics of removing hard mask layer, and then carry out the 3rd chemical mechanical milling tech.
Further, finish the 3rd cmp after, need clean the surface of described semiconductor structure, described cleaning comprises that ultrasonic wave cleans and washed with de-ionized water.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.