CN103943558B - Use the method that the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer is planarized by CMP - Google Patents

Use the method that the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer is planarized by CMP Download PDF

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CN103943558B
CN103943558B CN201410174849.0A CN201410174849A CN103943558B CN 103943558 B CN103943558 B CN 103943558B CN 201410174849 A CN201410174849 A CN 201410174849A CN 103943558 B CN103943558 B CN 103943558B
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copper
cmp
dielectric layer
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CN103943558A (en
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李婷
顾海洋
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National Center for Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics

Abstract

The present invention proposes a kind of method that the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer is planarized by CMP of employing, the method uses three steps to grind copper and barrier layer is removed and the surface planarisation of polymer (such as Polyimide or BCB): the copper on surface removed by first TSV copper lapping liquid, then remove barrier layer with barrier layer lapping liquid, finally use colloidal grinding liquid that polymeric layer is carried out planarization process.The invention have the advantage that and utilize polymer to replace silicon as keyset substrate, the processing step of CVD deposition dielectric layer can be saved, directly carry out process costs at polymer surfaces and be substantially reduced；Using cmp (CMP) that polymer surfaces carries out planarization process and can improve surface uniformity, make the little live width of follow-up high density is integrated into possibility.

Description

Use the method that the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer is planarized by CMP
Technical field
The present invention relates to a kind of method that the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer is planarized by CMP of employing, belong to technical field of manufacturing semiconductors.
Background technology
The copper cash interconnection that Damascus technics is widely used in during quasiconductor manufactures and designs.Common Damascus technics flow process is as follows: generate dielectric layer at silicon substrate, then etches deep hole, generates barrier layer, utilizes the method for PVD to deposit copper in deep hole.And the Damascus technics that is applied in TSV keyset is slightly different, first generates copper seed layer with PVD, then fills up etched hole by copper electroplating technology.Damascus technics is finally required for applying the copper on CMP removal surface to expose dielectric layer and completes the making of copper conductor.
The most common dielectric layer is all the oxide skin(coating) generated by CVD, its Technology relative maturity, and surface uniformity is good, and internal empty paddy is easily controllable, but cost is high.And the multiple Damascus technics with polymer as dielectric layer is poor due to polymer surfaces flatness, therefore can be only applied to the multiple wiring technique (RDL) of large scale live width, it is impossible to realize the superintegrated product requirement of little live width.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, one is provided to use the CMP method to carrying out planarization process with the post-depositional surface of copper in the polymer (such as polyimide or the BCB) Damascus technics as dielectric layer, to obtain good surface uniformity, reduce process costs simultaneously.
The technical scheme provided according to the present invention, the method that the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer is planarized by described employing CMP, comprise the following steps:
1) polymer as dielectric layer needs to carry out reasonable curing, to reach certain imidization degree.Polymer surfaces contact angle (contact after solidificationangle) < 70 degree, under the effect of CMP lapping liquid, be easier to hydrolysis, keep higher grinding rate.
2) complete step 1) polymer surfaces etching deep hole generate barrier layer, then generate copper seed layer, and complete copper deposition by plating；
3) use CMP to completing step 2) surface carry out planarization process, be carried out in three steps:
3.1) on the first grinding pad, remove the copper that surface is whole, stop over the barrier layer；
3.2) on the second grinding pad, remove surface barrier, stop on polymer dielectric layer；
3.3) being ground polymer on the 3rd grinding pad, adjust polymer surfaces flatness, in making wafer, uniformity WIW reaches < 1%；
4) finally the wafer after grinding is carried out.
Further, above-mentioned polymer is polyimides or benzocyclobutene.
The material on barrier layer described in step 1 is silicon nitride, silicon oxide, titanium or tantalum.
Step 3.1 selects grinding rate >=1um/min, select than (copper: polymer) the TSV copper lapping liquid of=200:1, abrasive grains selects SiO2, CeO2Or Al2O3, PH is 3 ~ 7；Select the gash depth of picture on surface in 2mils ~ 200mils, hardness >=50 The grinding pad of shore D.
Step 3.2 selects the lapping liquid for barrier layer, grinding rate > 500 / min, selects than (copper: polymer) < 3:1；Abrasive grains selects SiO2, CeO2Or Al2O3, PH is 3 ~ 7, selects the gash depth of picture on surface in 2mils ~ 200mils, hardness > and the grinding pad of=50 shore D.
Step 3.3 selects the grinding rate to polymer > 500nm/min, selecting than (copper: polymer) is 1:1, the lapping liquid of PH > 7, and its abrasive grains selects SiO2, CeO2Or Al2O3, should be containing the viscosity stabilized material at 18～300 mPa s (such as: glycerol) under 20 ~ 80 degree of process environments in lapping liquid；The additive of interpolation increase Polymer surfactants in last lapping liquid: deionized water DIW, potassium hydroxide KOH, or Tetramethylammonium hydroxide THAM；The gash depth of the grinding pad picture on surface selected is at 2mils ~ 200mils, and hardness is between 40 ~ 50shore D, and gash depth is between 2mils ~ 200mils.
Lapping liquid described in step 3, wherein abrasive grains size is 5 ~ 160 In the range of nm, abrasive grains hardness is in the range of 30 ~ 90 shore D, and in lapping liquid, the content of abrasive grains is in the range of 0.01wt% ~ 20wt%.Microvoid polyurethane material density used by grinding pad is 0.13 ~ 1.6g/cm3。
The invention have the advantage that
One, utilizing polymer to substitute conventional chemical deposition and can apply in multiple product as the dielectric layer in Damascus technics, its technique is easily controllable, and cost is relatively low；
Two, using cmp (CMP) that polymer surfaces carries out planarization process and can improve surface uniformity, make the little live width of follow-up high density is integrated into possibility.
Accompanying drawing explanation
Fig. 1 is the substrate using polymer as dielectric layer.
Fig. 2 is the surface after polymer dielectric layer etching deep hole.
Fig. 3 is the surface after generating barrier layer.
Fig. 4 is the surface after copper deposition.
Fig. 5 is the surface after cmp planarization.
Detailed description of the invention
The invention will be further described with embodiment below in conjunction with the accompanying drawings.
On the substrate of silicon or other materials, spin on polymers (such as Polyimide or BCB) is as inter-level dielectric (dielectric), but its surface uniformity is poor.Substrate 1 after spin on polymers is as shown in Figure 1.The present invention proposes to use three steps to grind make a return journey copper removal and barrier layer, completes the surface planarisation of polymer (such as Polyimide or BCB): first TSV copper lapping liquid (copper slurry) removes the copper on surface, then with barrier layer lapping liquid (Barrier Slurry) remove barrier layer (Barrier), finally use colloidal grinding liquid (colloidal Slurry) coordinate additive that polymeric layer is carried out planarization process.Specific as follows:
1) carry out polymer dielectric layer solidifying pretreatment.Toasting about 30min ~ 60min under the conditions of 150 ~ 250 degree celsius temperature, < 70 degree, now polymer imidization degree is good, it is easy to be hydrolyzed under CMP lapping liquid effect, keeps higher grinding rate to make polymer surfaces contact angle.
2) deep hole is etched according to technological requirement at polymer surfaces, as shown in Figure 2.
3) barrier layer 2 is generated, as shown in Figure 3.The effect on barrier layer 2 is typically prevent metal (copper) electron transfer (electro-migration) and increase adhesion (adhesion) between metal and polymer, can coordinate simultaneously and carry out CMP end point determination.The alternative material as barrier layer includes silicon nitride (PECVD Silicon nitride), silicon oxide (PECVD silicon Dioxide), titanium (Titan), tantalum (tantalum) etc..
4) copper seed layer growth and copper plating, as shown in Figure 4, deposited atop copper seed layer and copper electrodeposited coating 3.
5) use cmp (CMP) that surface is carried out planarization process.Grinding technics is carried out in three steps:
The first step, removes the copper that surface is whole on the first grinding pad, and technique is parked on barrier layer (Barrier).Consumptive material is selected as follows:
The TSV copper lapping liquid of (a) high grinding rate (copper removal rate >=1um/min) high selectivity simultaneously (copper: polymer >=200:1).Abrasive grains can be selected for following material: Si oxide (SiO2), seleno oxide (CeO2) and aluminum oxide (Al2O3) etc..PH is 3 ~ 7.The different morphologies such as abrasive grains size controls in the range of 5 ~ 160 nm, and the pattern of abrasive grains can select circle according to technological requirement, pointed shape, abrasive grains hardness is at 30 ~ 90 shore D.The content of abrasive grains controls in the range of 0.01wt% ~ 20wt%.
B the groove on () grinding pad (pad) surface can need to be designed as various pattern (groove according to technique Pattern), gash depth (groove depth) is at 2mils ~ 200mils;Grinding pad hardness (pad hardness)>=50 shore D;Microvoid polyurethane material (microcellular used by grinding pad Polyurethane) density should be 0.13 ~ 1.6g/cm3。
C () present invention utilizes endpoint Detection (EPD), including Real-time process control system (RTPC), optical end point detection (Fullscan).
Second step, removes surface barrier (Barrier) on the second grinding pad, is parked on polymer (Polyimide or BCB) layer.Consumptive material is selected as follows:
A lapping liquid that () is ground for barrier layer and designed, grinding rate>500/min, select than (copper: polymer)<lapping liquid of 3:1.Abrasive grains can be selected for following material: Si oxide (SiO2), seleno oxide (CeO2) and aluminum oxide (Al2O3) etc..The different morphologies such as abrasive grains size controls in the range of 5 ~ 160 nm, and the pattern of abrasive grains can select circle according to technological requirement, pointed shape, abrasive grains hardness is in the range of 30 ~ 90 shore D.The content of abrasive grains controls in the range of 0.01wt% ~ 20wt%.
B the groove on () grinding pad surface can need to be designed as various pattern (groove pattern) according to technique, gash depth (groove depth) is at 2mils ~ 200mils; Grinding pad hardness >=50 shore D;Microvoid polyurethane material density used by grinding pad should be 0.13 ~ 1.6g/cm3。
C () present invention utilizes EPD technology, including optical end point detection technique (Fullscan).
3rd step, is ground polymer on the 3rd grinding pad, adjusts polymer surfaces flatness (uniformity), and in making wafer, uniformity WIW reaches < 1%.Consumptive material is selected as follows:
A the lapping liquid (colloidal slurry) of () low selection ratio, such as grinding rate > 100nm/min, select to include SiO than (copper: polymer) close to 1:1, abrasive grains2, CeO2And Al2O3Deng, PH lapping liquid between 7 ~ 10.Abrasive grains includes all size (5 ~ 160 nm etc.), various patterns (select circle according to technological requirement, the different morphologies such as pointed shape), and the material granule of various hardness (30 ~ 90 shore D), the content of abrasive grains, should be containing viscosity stabilized (> 18 under 20 ~ 80 degree of process environments in lapping liquid in the range of 0.01wt% ~ 20wt% MPa s and < 300 mPa s) material (such as: glycerol).
B () can increase the additive (such as: deionized water DIW, potassium hydroxide KOH, Tetramethylammonium hydroxide THAM) of Polymer surfactants.
C () grinding pad includes various surface groove pattern (groove pattern) and gash depth (groove Depth), if the gash depth of grinding pad picture on surface is at 2mils ~ 200mils;Grinding pad hardness is at 40 ~ 50shore D;Microvoid polyurethane material density used by grinding pad should be 0.13 ~ 1.6g/cm3)。
Finally, complete according to cleaning (clean post CMP) point four steps after conventional grinding:
The first step, utilizes ultrasound wave (Megasonic) and ultra-pure water (DIW) to remove the larger particles being attached to silicon chip surface.
Second step, immerses silicon chip (wafer) in suitable chemical reagent (such as: CX100, SC1, SC2 etc.), utilizes the soft brush of polyvinyl alcohol (PVA) to rotate the granule sticked by silicon chip surface and remove under silicon slice rotating state.
3rd step, repeats second step operation in new rinse bath, removes the granule of surface adhesion further.
4th step, uses isopropanol (IPA) and mechanical force jointly to act on dry silicon chip.
The silicon chip obtained is as shown in Figure 5.

Claims (8)

1. the method using CMP to planarize the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer, is characterized in that, comprise the following steps:
1) polymer surfaces is carried out cured, make polymer surfaces contact angle < 70 degree；
2) etch deep hole at polymer surfaces and generate barrier layer, then carrying out copper seed layer growth and plating；
3) use cmp that substrate surface is carried out planarization process, be carried out in three steps:
3.1) on the first grinding pad, remove the copper that surface is whole, stop over the barrier layer；
3.2) on the second grinding pad, remove surface barrier, stop on polymer dielectric layer；
3.3) being ground polymer on the 3rd grinding pad, adjust polymer surfaces flatness, in making wafer, uniformity WIW reaches < 1%；
4) finally the wafer after grinding is carried out；
Step 3.1 selects grinding rate >=1um/min, select copper: polymer > the TSV copper lapping liquid of=200:1, abrasive grains selects SiO2, CeO2Or Al2O3, pH is 3 ~ 7；Select the gash depth of picture on surface in 2mils ~ 200mils, hardness > grinding pad of=50 shore D.
2. the method using CMP to planarize the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer as claimed in claim 1, is characterized in that, described polymer is polyimides or benzocyclobutene.
3. the method using CMP to planarize the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer as claimed in claim 1, is characterized in that, the material on barrier layer described in step 1 is silicon nitride, silicon oxide, titanium or tantalum.
4. use the method that the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer is planarized by CMP as claimed in claim 1, it is characterized in that, step 3.2 selects the lapping liquid for barrier layer, grinding rate>500/min, selection copper: polymer<3:1；Abrasive grains selects SiO2, CeO2Or Al2O3, pH is 3 ~ 7, selects the gash depth of picture on surface in 2mils ~ 200mils, hardness > and the grinding pad of=50 shore D.
5. use the method that the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer is planarized by CMP as claimed in claim 1, it is characterized in that, step 3.3 selects the grinding rate to polymer > 500nm/min, select copper: polymer is 1:1, the lapping liquid of pH > 7, its abrasive grains selects SiO2, CeO2Or Al2O3, should be containing viscosity stabilized 18～300 under 20 ~ 80 degree of process environments in lapping liquid The material of mPa s；The additive of interpolation increase Polymer surfactants in last lapping liquid: deionized water DIW, potassium hydroxide KOH, or Tetramethylammonium hydroxide THAM；The gash depth of the grinding pad picture on surface selected is at 2mils ~ 200mils, and hardness is between 40 ~ 50shore D, and gash depth is between 2mils ~ 200mils.
6. such as claim 1, the method that the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer is planarized by CMP is used described in 4 or 5, it is characterized in that, described abrasive grains size is in the range of 5 ~ 160 nm, abrasive grains hardness is in the range of 30 ~ 90 shore D, and in lapping liquid, the content of abrasive grains is in the range of 0.01wt% ~ 20wt%.
7. the method using CMP to planarize the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer as described in claim Isosorbide-5-Nitrae or 5, is characterized in that, the microvoid polyurethane material density used by described grinding pad is 0.13 ~ 1.6g/cm3。
8. the method using CMP to planarize the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer as claimed in claim 5, is characterized in that, in lapping liquid described in step 3.3, contained viscosity stabilized material is glycerol.
CN201410174849.0A 2014-04-28 2014-04-28 Use the method that the post-depositional surface of copper in the Damascus technics with polymer as dielectric layer is planarized by CMP Active CN103943558B (en)

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CN105817991A (en) * 2015-01-06 2016-08-03 中芯国际集成电路制造(上海)有限公司 Chemical mechanical grinding method
US9892970B2 (en) 2016-06-02 2018-02-13 Globalfoundries Inc. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
US9929085B2 (en) 2016-06-02 2018-03-27 Globalfoundries Inc. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same

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CN101740378A (en) * 2008-11-13 2010-06-16 中芯国际集成电路制造(北京)有限公司 Copper chemical mechanical polishing method

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CN101740378A (en) * 2008-11-13 2010-06-16 中芯国际集成电路制造(北京)有限公司 Copper chemical mechanical polishing method

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