CN101728427B - Semiconductor transistor - Google Patents
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- CN101728427B CN101728427B CN2009101375704A CN200910137570A CN101728427B CN 101728427 B CN101728427 B CN 101728427B CN 2009101375704 A CN2009101375704 A CN 2009101375704A CN 200910137570 A CN200910137570 A CN 200910137570A CN 101728427 B CN101728427 B CN 101728427B
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
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Abstract
A semiconductor transistor device includes one or more conductive base regions, a first semiconductor barrier region, a second semiconductor barrier region, a conductive emitter region, and a conductive collector region. The first semiconductor barrier region or the second semiconductor barrier region has a dimension smaller than the interface of the first semiconductor barrier region and the conductive base regions. A second Schottky barrier junction is formed at the interface of the second semiconductor barrier region and the one or more conductive base regions. A third Schottky barrier junction is formed at the interface of the conductive emitter region and the first semiconductor barrier region. A fourth Schottky barrier junction is formed at the interface of the conductive collector region and the second semiconductor barrier region.
Description
Technical field
The present invention refers to be applicable to the semiconductor transistor of simulation and digital circuit especially relevant for semiconductor subassembly.
Background technology
40 years in the past, IC industry taked to dwindle size of components and the development course that increases chip area, made the usefulness and all theatrical significantly lifting of function of chip.Per just had the assembly of new generation just so-called Moore's Law to occur in 2 to 3 years.Compared to the last generation, the assembly of each new generation, its transistorized size dwindles 30% approximately, and the usefulness of circuit promotes 40% approximately, the doubled in density of logical circuit, and memory capacity is also grown into 4 times.Continual progress like this leads out a kind of expectation, is exactly more powerful chip of the faster and usefulness of speed, will be in a foreseeable future, and the release that continues according to this time-histories table.
Metal oxide semiconductcor field effect transistor (MOSFET) is the basic module of semiconductor technology.The success of MOS transistor, can give the credit to its size can constantly be dwindled, and can also increase its circuit performance simultaneously, and reduces manufacturing cost.Why CMOS can become the main flow framework of integrated circuit, and the usefulness that is CMOS also can reduce the consumption of energy simultaneously when continuing improvement.Dwindle the transistorized size of CMOS, become the principal element that strengthens microprocessor usefulness.Progressive so fast in the past in order to continue, the size of how actively to dwindle the MOS transistor assembly becomes the harsh challenge that semiconductor industry is faced at present.Industry it has been generally acknowledged that within 10 years of future MOSFET will run into the restriction of the obstacle and the basic physics of key technology aspect dimension shrinks.Main challenge comprise power controlling how consumption, reduce leakage current, promote drive current, obtain to have the gate insulation layer (Gate Insulator) of high-k, the metal gate with suitable work function (Work Function), ultra shallow source/drain engage (Source/Drain Junctions), reduce dead resistance/electric capacity, reduce the inequality that doping content distributes and the uniformity of lifting subassembly characteristic.
The power consumption increase is the biggest obstacle of dwindling size of components.Just became 2 times in per 3.3 years in the power density of chip surface.The main cause that causes power consumption to increase fast is the underswing of supply voltage minimizing and the positive increase of transistor density.Frequency of operation and number of transistors like fruit chip are kept present growth trend, and the power consumption of high performance microprocessor will reach 10KW in the several years, and the hot output power of chip surface will reach 1000W/cm
2Take the object of other heating to do comparison, the power density of filament is about 100W/cm
2, rocket nozzle is 1000W/cm
2, sun surface is 6000W/cm
2In addition, we know that from the speed of surface radiating be limited.See through heat loss through conduction, (T from the silicon surface
Max＜400 ° of K) maximum rate of heat radiation is about 1000W/cm
2
Along with the physics limit of its microminiaturization of traditional planar body type (Planar Bulk) silicon CMOS transistor convergence, people must consider to adopt the modular construction and the material of innovation, in the hope of continuing the historical in the past brilliant progress of transistor.What people were positive does some variations on conventional MOS FET structure; Comprise that (Silicon-on-Insulator, SOI) MOSFET, many gates MOSFET (for example FinFET and Tri-Gate), Schottky can hinder how rice band transistor of metal oxide semiconductcor field effect transistor (SB-MOSFET), carbon nanotube transistor (CNT) and graphene for the silicon insulation of ultra-thin body (UTB).These atypical its purposes of design of MOSFET structure mainly are to improve short-channel effect, therefore have better contractibility than planar body type MOSFET.Yet, these atypical assemblies, structurally they are still MOSFET, are faced with similar challenges with the MOSFET of planar body type, and for example the increase of power consumption and usefulness is saturated.Continuing the trend that transistor is grown up, continue to promote chip speed and function, is very difficult as far as MOSFET.Semiconductor technology must have sizable innovation, just can overcome the challenge of transistor microminiaturization, with the track of continuity past semiconductor progress.Therefore people need new transistor with accentuator usefulness, increase chip functions and reduction manufacturing cost, make the progressive trend in transistor past to continue.
When the microminiaturization of MOSFET approached its physics limit, people also will consider other modular construction, in the hope of continuing the trend of microminiaturization.This paper will discuss two kinds of convention assemblies at this: tunnel assembly (Resonant Tunneling Devices) is worn in metal base transistor (MBT) and resonance, and the operation principle of these two kinds of assemblies all is the quantum-mechanical tunneling effect of utilization.
Metal base transistor is a kind ofly to engage transistor than two-carrier (Bipolar JunctionTransistor BJT) also has the early stage trial of better usefulness for reaching.Metal base transistor has three kinds of different modular constructions, but all is used as base stage with metal.First kind of modular construction is the structure of metal-insulating body-metal-insulant-metal (MIMIM).Fig. 1 a shows this kind MIMIM structure and energy band diagram thereof.When this assembly added suitable bias voltage, electronics can hinder layer directive base stage from the thin insulating that emitter-base bandgap grading passes between emitter-base bandgap grading and the base stage.These electronics of injecting are called as hot electron, because their energy exceeds several kT than the fermi level (Fermi Level) in base stage.This MIMIM assembly also is a kind of hot electron transistor (Hot-Electron Transistor) and ballistic injection transistor (Ballistic InjectionTransistor).These hot electrons if with ing in base stage by reorganization (Recombine), then might continue across base stage and collect can hinder and arrive and collect the utmost point between the utmost point.Second kind of modular construction of metal base transistor is to engage (Schottky Junction) with metal-semiconductor Schottky to replace the mim structure of base stage to the collection utmost point.Fig. 1 b shows this kind metal-insulating body-metal-semiconductor (MIMS) structure and energy band diagram thereof.The third modular construction of metal base transistor is with metal-semiconductor schottky junctions conjunction generation two mim structures.Fig. 1 c shows this kind semiconductor-metal-semiconductor (SMS) structure and energy band diagram thereof.At this SMS modular construction, because the height that can hinder that Schottky engages is little than mim structure, hot electron is with thermionic emission (Thermionic Emission) by emitter-base bandgap grading to base stage but not wears the tunnel injection.Early stage metal base transistor is main because two following problems: (one) base width is big, causes base stage to transmit factor-alpha
TBad, (two) are difficult for forming the single-crystal semiconductor material of good quality on metal, make transistorized usefulness unclear, also rare in recent years progress and breakthrough.
Resonance wear the tunnel assembly utilize quantum effect produce negative difference resistance (Negative DifferentialResistance, NDR).This assembly has the structure of dual intensity resistance quantum well (Double Barrier Quantum Well), and normally the different joint (Heterojunction) by the III-V compound semiconductor with discontinuous conduction band (Conduction Band) (for example GaAs GaAs and Aluminum gallium arsenide AlGaAs) constitutes.Electron energy in quantum well is by quantization.Fig. 2 a shows that both-end dual intensity resistance Aluminum gallium arsenide/GaAs/the tunnel diode is worn in Aluminum gallium arsenide's resonance, and (Resonant Tunneling Diode RTD) wears the energy band diagram under the tunnel bias voltage in resonance.When the energy of injecting electronics meets the energy of the accurate bound state in quantum well, covibration will take place, and wear the tunnel electric current and reach maximum this moment.When discontinuous in electron energy departs from quantum well can rank, wear the tunnel electric current and then diminish.On the I-V characteristic, this has caused negative difference resistance.This effect can be used as the generation and the amplification of microwave.On the I-V performance plot, the maximum of electric current and the ratio of minimum value are the important parameters that the tunnel diode is worn in resonance.
Fig. 2 b shows that three ends resonance wears tunnel transistor (Resonant Tunneling Transistor, energy band diagram RTT).The band gap of emitter-base bandgap grading (Band Gap) is big than base stage, can stop the electric hole that flows to emitter-base bandgap grading from base stage.Compare with the two ends assembly, three end assemblies provide insulation preferable between input and the output, higher circuit gain, with bigger fan out capability.Under some bias condition, resonance is worn the transistorized I-V characteristic of tunnel and is presented negative difference resistance.Collected current has a series of crest, the resonance of different-energy state in corresponding the quantum well.Basically, resonance is worn the tunnel assembly because have multi-mode characteristic, compares with the traditional MOSFET circuit design, can use less transistor, therefore can reduce the complexity of circuit.
Next cooperate graphic and figure number; Lift a preferred embodiment simultaneously and do further explanation, your juror the phase can make this creation is had more detailed understanding, and only the following stated person is merely the preferred embodiment that is used for explaining this creation; Be not that attempt is done any pro forma restriction to this creation according to this; Therefore every under the creation spirit of this creation, the modification of any pattern of doing or change all must belong to the category that this creation intention is protected.
Summary of the invention
The present invention can comprise with the next item down or multinomial narration.The present invention is relevant for a kind of semiconductor transistor, and it comprises one or more conductions base region, first semiconductor energy resistance district, second semiconductor energy resistance district, conduction emitter region and conduction collector region.This conduction base region is connected to the first electronics end.This first semiconductor energy resistance district's contact should the conduction base region.First Schottky can hinder and engage the interface that is formed at this first semiconductor energy resistance district and this conduction base region.This second semiconductor energy resistance district's contact should the conduction base region.Second Schottky can hinder and engage the interface that is formed at this second semiconductor energy resistance district and this conduction base region.This first semiconductor energy resistance district of this conduction emitter region contact.The 3rd Schottky can hinder and engage the interface that is formed at this conduction emitter region and this first semiconductor energy resistance district.This conduction emitter region is connected to the second electronics end.This second semiconductor energy resistance district of this conduction collector region contact.The 4th Schottky can hinder and engage the interface that is formed at this conduction collector region and this second semiconductor energy resistance district.This conduction collector region is connected to the 3rd electronics end.At least the size in this first semiconductor energy resistance district or this second semiconductor energy resistance district is less than
On the other hand, the present invention is relevant for a kind of semiconductor transistor, and it comprises one or more conductions base region, first semiconductor energy resistance district, second semiconductor energy resistance district, conduction emitter region and conduction collector region.This first semiconductor energy resistance district's contact should the conduction base region.First Schottky can hinder and engage the interface that is formed at this first semiconductor energy resistance district and this conduction base region.This second semiconductor energy resistance district's contact should the conduction base region.Second Schottky can hinder and engage the interface that is formed at this second semiconductor energy resistance district and this conduction base region.This first semiconductor energy resistance district of this conduction emitter region contact.The 3rd Schottky can hinder and engage the interface that is formed at this conduction emitter region and this first semiconductor energy resistance district.This second semiconductor energy resistance district of this conduction collector region contact.The 4th Schottky can hinder and engage the interface that is formed at this conduction collector region and this second semiconductor energy resistance district.When suitable voltage is added in this conduction base region, can produces and wear the tunnel electric current, through this first semiconductor energy resistance district and this second semiconductor energy resistance district.
On the other hand, the present invention is relevant for a kind of semiconductor transistor, and it comprises one or more conductions base region, first semiconductor energy resistance district, second semiconductor energy resistance district, conduction emitter region and conduction collector region.This first semiconductor energy resistance district's contact should the conduction base region.First Schottky can hinder and engage the interface that is formed at this first semiconductor energy resistance district and this conduction base region.This second semiconductor energy resistance district's contact should the conduction base region.Second Schottky can hinder and engage the interface that is formed at this second semiconductor energy resistance district and this conduction base region.This first semiconductor energy resistance district of this conduction emitter region contact.The 3rd Schottky can hinder and engage the interface that is formed at this conduction emitter region and this first semiconductor energy resistance district.This second semiconductor energy resistance district of this conduction collector region contact.The 4th Schottky can hinder and engage the interface that is formed at this conduction collector region and this second semiconductor energy resistance district.This conduction emitter region, this conduction base region maybe this conduction collector region comprise one or more metal, silicide (Silicide), germanide (Germanide) and metallic compound.This first semiconductor energy resistance district comprises the ground floor between this conduction base region and this conduction emitter region.This second semiconductor energy resistance district comprises the second layer between this conduction base region and this conduction collector region.The thickness of this ground floor and this second layer comprises silicon less than
this ground floor or this second layer.This ground floor is parallel to (100) or (110) crystal face.This conduction base region between this first semiconductor energy resistance district and this second semiconductor energy resistance district forms a quantum well.When suitable voltage is added in this conduction base region, can produces and wear the tunnel electric current, through this first semiconductor energy resistance district and this second semiconductor energy resistance district.
On the other hand, the present invention is relevant for a kind of three dimensional integrated circuits, and it comprises:
A) plate base;
B) the first semiconductor transistor assembly, it comprises:
I) the first conductive bottom electrode layer, it is positioned on this substrate;
Ii) first semiconductor energy resistance layer, it contact this first conductive bottom electrode layer, and wherein first Schottky can hinder joint and is formed at this first semiconductor energy and hinders layer the interface with this first conductive bottom electrode layer;
The iii) first conduction base layer, it contacts this first semiconductor energy resistance layer, and wherein second Schottky can hinder to engage and be formed at the interface that this first conduction base layer and this first semiconductor energy hinder layer;
Iv) second semiconductor energy resistance layer, it contacts this first conduction base layer, wherein the 3rd Schottky can hinder engage be formed at this second semiconductor energy resistance layer with this first conduct electricity base layer the interface; And
The v) first conductive tip electrode layer, it contacts this second semiconductor energy resistance layer, and wherein the 4th Schottky can hinder to engage and be formed at the interface that this first conductive tip electrode layer and this second semiconductor energy hinder layer;
C) first insulating barrier; And
D) the second semiconductor transistor assembly, it comprises:
I) the second conductive bottom electrode layer, it is positioned on this first insulating barrier;
Ii) the 3rd semiconductor energy resistance layer, it contact this second conductive bottom electrode layer, and wherein the 5th Schottky can hinder joint and is formed at the 3rd semiconductor energy and hinders layer the interface with this second conductive bottom electrode layer;
The iii) second conduction base layer, its contact the 3rd semiconductor energy resistance layer, wherein the 6th Schottky can hinder to engage and be formed at the interface that this second conduction base layer and the 3rd semiconductor energy hinder layer;
Iv) the 4th semiconductor energy resistance layer, it contacts this second conduction base layer, wherein the 7th Schottky can hinder engage be formed at the 4th semiconductor energy resistance layer with this second conduct electricity base layer the interface; And
The v) second conductive tip electrode layer, its contact the 4th semiconductor energy resistance layer, wherein the 8th Schottky can hinder to engage and be formed at the interface that this second conductive tip electrode layer and the 4th semiconductor energy hinder layer;
Wherein this first semiconductor energy resistance layer, this first conduction base layer and this second semiconductor energy resistance layer form first dual intensity resistance quantum well; Wherein the 3rd semiconductor energy resistance layer, this second conduction base layer and the 4th semiconductor energy resistance layer form second dual intensity resistance quantum well; Wherein be added in the voltage of this first conduction base layer, control is worn the tunnel electric current through this first dual intensity resistance quantum well.
Execution mode of the present invention possibly comprise following one or more characteristics.This first semiconductor energy resistance district can comprise the ground floor between this conduction base region and this conduction emitter region; Wherein the thickness of this ground floor comprises silicon less than
this ground floor, and wherein this ground floor is parallel to (100) or (110) crystal face.This second semiconductor energy resistance district can comprise the second layer between this conduction base region and this conduction collector region, wherein the thickness of this second layer less than
this first semiconductor energy resistance distinguish or this second semiconductor energy hinders and distinguishes that a kind of semi-conducting material can be arranged is silicon, germanium, carbon or III-V compound semiconductor.At least this first semiconductor energy resistance district or this second semiconductor energy resistance district comprise a layer structure; Its thickness is this conduction base region between this first semiconductor energy resistance district and this second semiconductor energy resistance district less than
, forms a quantum well.When suitable voltage is added in this conduction base region, can produces and wear the tunnel electric current, through this first semiconductor energy resistance district and this second semiconductor energy resistance district.Hinder the conduction band edge (Conduction Band Edge) in district or this second semiconductor energy resistance district near this first semiconductor energy when the working function (Work Function) of this conduction base region; And during away from its valence band edge (ValenceBand Edge), this main carrier (Carriers) of wearing the tunnel electric current is an electronics.The voltage that wherein imposes on this conduction base region possibly be positive with respect to emitter voltage.Wherein conduct electricity the base region possibly comprise a layer thickness less than
Nickel disilicide (NiSi
2).This nickel disilicide layer is parallel to (100) crystal face.When working function of this conduction base region near the valence band edge in this first semiconductor energy resistance district or this second semiconductor energy resistance district, and during away from its conduction band edge, this main carrier of wearing the tunnel electric current is electric hole.The voltage that wherein imposes on this conduction base region possibly born with respect to emitter voltage.Wherein this conduction base region possibly comprise a layer thickness less than
Cobalt disilicide (CoSi
2).This cobalt disilicide layer is parallel to (100) crystal face.At least this first semiconductor energy resistance district or second semiconductor energy resistance district can not be doped.This conduction emitter region, this conduction base region maybe this conduction collector region can comprise one or more metal, silicide, germanide and metallic compound.At least this first semiconductor energy resistance district or this second semiconductor energy resistance district can comprise the different connected structure of silicon/germanium.The combination thickness of the different connected structure of this silicon/germanium can comprise that less than
this conduction base region the first conduction base region, a semiconductor base stage can hinder the district and the second conduction base region; Wherein this first semiconductor energy resistance of this first conduction base region contact is distinguished; Wherein this semiconductor base stage can hinder this first conduction base region of contact, district, wherein this second semiconductor energy resistance district of this second conduction base region contact.
Execution mode of the present invention possibly comprise following one or more advantage.The Schottky that this specification discloses can hinder quantum well resonance and wear tunnel transistor (SBQWRTT), breaks through the physical restriction that the traditional MOSFET assembly is faced, and to following assembly microminiaturization answer is provided.SBQWRTT in this exposure has simpler modular construction and better contractibility than traditional MOSFET.Need not use little shadow (Photolithography) processing procedure to define its critical size at the SBQWRTT of this exposure.Brilliant method (Epitaxy) of heap of stone forms active layers (Active Layers) with accurate THICKNESS CONTROL.Its modular construction does not have required shallow joint of MOSFET and thin gate insulation layer.The variation of its component characteristic is little than MOSFET also; Because influence two main sources that the MOSFET component characteristic changes; (Line EdgeRoughness LER) is not present in SBQWRTT for statistics doping fluctuating (Statistical Dopant Fluctuation) and line edge roughness.SBQWRTT has less transistor size and bigger current densities.SBQWRTT can operate with fast speeds, because the operation principles of its assembly is based on quantum-mechanical tunnel and the ballistic transport (Ballistic Transport) of wearing.Because SBQWRTT has less subcritical swing (Subthreshold Swing) and starts ability faster, so can under lower supply voltage, operate and consume less energy.Its base layer has only the thickness of several atomic layers, does not but have the puzzlement of similar MOSFET short-channel effect (Short-Channel Effect).The processing procedure of SBQWRTT is comparatively simple and production cost is lower; Because it uses less photograph light shield step, and need not use complicated and expensive processing procedures such as ultra shallow joint, height-k metal gate heap (High-k Metal-GateStack), embedded silicon Germanium source/drain joint and dual stressed layers (Dual Stressor Layers).Therefore, to following assembly microminiaturization, SBQWRTT has more contractibility than MOSFET.
The SBQWRTT chip that this specification discloses is than compatible CMOS chip consumption electric power still less.SBQWRTT can operate under lower supply voltage than MOSFET, for example 0.2V or lower.Less subcritical swing is a key of obtaining low VCC, makes SBQWRTT in less voltage range, to start and to close.Conductive mechanism is that tunnel is worn in resonance.High-penetration coefficient during resonance (Transmission Coefficient) significantly promotes drive current.If the energy of injection carrier is the deviation resonance energy a little, then penetrating coefficient can descend with progression.Less subcritical swing and startup ability faster give the credit to the resonance tunneling effect.Because short-channel effect, the subcritical swing meeting of MOSFET is along with gate length is dwindled and variation.As far as the MOSFET and the SBQWRTT of identical carrier transmission range (promptly be source electrode-to-drain or emitter-base bandgap grading-to the distance of-collection utmost point) are arranged, SBQWRTT has less subcritical swing than MOSFET.
The SBQWRTT that this specification discloses has littler dead resistance than MOSFET.Small electric power is wasted in parasitic element, so the exportable high drive current of SBQWRTT.As far as MOSFET, source/drain is extended (Source/Drain Extensions) must be shallow joint, with effective control short-channel effect.When depth of engagement (Junction Depth) and contact size (ContactSize) when diminishing, source/drain series resistance and contact resistance also increase thereupon.The dead resistance that increases significantly reduces drive current, and consumes more power.Ultra shallow joint is difficult to reduce its sheet resistor (Sheet Resistance).Emitter-base bandgap grading/base stage of SBQWRTT/collection utmost point is made up of low-resistance metal or silicide.Therefore emitter-base bandgap grading/collector series resistance of SBQWRTT is much smaller than the source/drain series resistance of MOSFET.Emitter-base bandgap grading/base stage of SBQWRTT/collection utmost point contact resistance, its value is much smaller than the source/drain contact resistance of MOSFET, because the former is the contact resistance of metal to metal or metal pair silicide, and the latter is that silicide is to semi-conductive contact resistance.
The SBQWRTT that present disclosure discloses can be at working at high speed, because the ballistic transport of its low dead resistance, little base width, quantum-mechanical tunneling effect, carrier and big drive current.The penetrating of SBQWRTT/base/collector region is constituted with low-resistance metal or silicide, can significantly reduce its series resistance.Semiconductor is penetrated/is collected the utmost point and can hinder the district and can be free from admixture and mix, thereby eliminates impurity collision (ImpurityScattering).With the assembly of tunneling effect running, be born with and occupy the advantage on the speed in the sky, and its speed is far above the assembly that is used for operating with drift (Drift) or diffusion (Diffusion), for example FET or BJT.Aspect high-speed applications, SBQWRTT has attracting advantage.As far as MOSFET, when the depth of engagement of source/drain and contact size diminished, it is big that the series resistance of source/drain and contact resistance become thereupon.Common way is to improve the doping content of passage, with the compacting short-channel effect.The dead resistance and the passage doping content that increase have significantly reduced drive current.Dwindle gate length though borrowing, component speed is slightly improved, and the improvement of usefulness has become slow at these several years.Dead resistance causes the delay on the speed, can play the part of more and more important role in future.Present way is to improve V
DD(its cost be increase power consumption) and be stressed in silicon crystal lattice, with drive current that improves MOSFET and the mobility (Carrier Mobility) that promotes carrier, and then raising speed.We think will lose effect in future soon by these two kinds of strategies.
The SBQWRTT that this specification discloses has less transistor size and higher packed bulk density than MOSFET.The minimum dimension of SBQWRTT depends on little shadow and the etch process distance between minimum contact size and contact being provided and contacting basically.SBQWRTT is three end assemblies, is rectangle usually on layout.Use the different p type assembly that is bonded on of silicon/germanium, more can balance n and the drive current of p type SBQWRTT.N can occupy identical service area (ActiveArea) with p type SBQWRTT, and repeatedly on another, this has further improved packed bulk density for one of them.Traditional planar body type MOSFET is four end assemblies, and its 4th end is a substrate contacts.Design rule also requires source/drain to keeping a safe distance between the gate.The layout of MOSFET has irregular shape usually because gate elongated end (Poly End Cap) contacts with gate pole.The size of mosfet transistor is bigger than SBQWRTT usually.
The SBQWRTT that present disclosure discloses is general purpose transistor.Though the operating mechanism of SBQWRTT and MOSFET and BJT differ widely, the I-V characteristic of SBQWRTT and the transmission curve of inverter (Transfer Curve) are similar with them.SBQWRTT is fit to the circuit application of numeral and simulation.In digital application, transistor is to be one three end-grain cutting parallel operation, and wherein the electrical conductivity between the two ends depends on the 3rd end.Because I
CBe V
BExponential function, the I-V characteristic of SBQWRTT depends on V
B, so SBQWRTT is fit to low-power and application at a high speed.Aspect board design, SBQWRTT is similar a bit with traditional BJT board design, because the I of two kinds of assemblies
CWith V
BBetween all be index relation.
The SBQWRTT that present disclosure discloses can be made on the silicon substrate, reducing cost, and compatible with the semiconductor fabrication of today.The SBQWRTT processing procedure is simpler and cost is lower than CMOS processing procedure, because need less micro-image light cover step.Shallow source/drain that SBQWRTT does not need high doping content engages.SBQWRTT does not need the thin lock insulator of high-k, low electric leakage and low interface state density (Interface State Density).SBQWRTT does not need thin silicon body (for example UTB MOSFET is used on SOI) or thin silicon fin (for example FinFET is used) yet.SBQWRTT need not utilize stress technique, promotes the mobility of particle.Its working lining is under the environment of ultra high vacuum (UHV), with the molecular beam epitaxy method (Molecular Beam Epitaxy, MBE) or atom lamination method (Atomic Layer Deposition ALD) builds crystals growth.If modular construction is with crystals growth of heap of stone, and its critical size is in vertical direction, and is more more accurate than the horizontal size that defines with micro-photographing process.ALD has been used on the advanced CMOS processing procedure at present, in order to the gate insulation layer of deposition high-k, so the silicon manufacturing technology of SBQWRTT processing procedure and today is compatible.
The SBQWRTT that present disclosure discloses can be made on the same chip with other traditional components (for example MOSFET and BJT).Wherein, MOSFET and BJT can be used for the application (for example I/O assembly) and the high simulation application (for example induction amplifier) of precision of high voltage, high electric current.SBQWRTT can be used for core logic or low V
CCThe application of high-speed figure.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 a is the metal base transistor that the MIMIM structure is arranged, its modular construction and energy band diagram.
Fig. 1 b is the metal base transistor that the MIMS structure is arranged, its modular construction and energy band diagram.
Fig. 1 c is the metal base transistor that the SMS structure is arranged, its modular construction and energy band diagram.
Fig. 2 a has the resonance of dual intensity resistance Aluminum gallium arsenide/GaAs/Aluminum gallium arsenide's quantum well to wear the tunnel diode, wears the energy band diagram under the bias condition of tunnel in resonance.
Fig. 2 b has the resonance of discontinuous emitter-base bandgap grading and dual intensity resistance Aluminum gallium arsenide/GaAs/Aluminum gallium arsenide's quantum well base stage to wear the tunnel transistor, wears the energy band diagram under the bias condition of tunnel in resonance.
Fig. 3 has the sketch map of the SBQWRTT of metal-semiconductor-metal-semiconductor-metal structure for the present invention.
Fig. 4 a-e is n type SBQWRTT, the energy band diagram under different bias condition.
Fig. 5 a is for being presented at n type SBQWRTT, the relation of its penetrating coefficient and electron energy.
Fig. 5 b is for being presented at n type SBQWRTT, its exemplary current-voltage characteristic curve.
Fig. 6 a works as W for being presented at n type SBQWRTT
EB=W
CB=13,19,25 atomic layers, its electronics and electricity pierce tunnel electric current (J
TnAnd J
Tp) and base voltage V
BRelation.
Fig. 6 b works as W for being presented at n type SBQWRTT
EB=W
CB=13,19,25 atomic layer and V
B=0V, the relation of its penetration of electrons coefficient and energy.
Fig. 6 c is for being presented at n type SBQWRTT, its subcritical swing and electrons tunnel electric current J
TnWith the relation that can hinder layer thickness, wherein W
EB=W
CB
Fig. 7 a works as W for being presented at n type SBQWRTT
B=1,2,3 atomic layers, its electronics and electricity pierce tunnel electric current (J
TnAnd J
Tp) and base voltage V
BRelation.
Fig. 7 b works as W for being presented at n type SBQWRTT
B=1,2,3 atomic layer and V
B=0V, the relation of its penetration of electrons coefficient and energy.
Fig. 7 c is for being presented at n type SBQWRTT, its subcritical swing and electrons tunnel electric current J
TnWith W
BRelation.
Fig. 8 a is for being presented at n type SBQWRTT, as q Φ
Bn=0.24,0.4,0.56eV, its electronics and electricity pierce tunnel electric current (J
TnAnd J
Tp) and base voltage V
BRelation.
Fig. 8 b is for being presented at n type SBQWRTT, as q Φ
Bn=0.24,0.4,0.56eV and V
B=0V, the relation of its penetration of electrons coefficient and energy.
Fig. 8 c is for being presented at n type SBQWRTT, its subcritical swing and electrons tunnel electric current J
TnWith q Φ
BnRelation.
Fig. 9 a is the energy band diagram that is presented at the p type SBQWRTT under the thermal equilibrium condition, and wherein to hinder be that homosphere by non-impurity-doped semiconductor constitutes for the emitter-base bandgap grading and the collection utmost point.
Fig. 9 b is the energy band diagram that is presented at the p type SBQWRTT under the thermal equilibrium condition, and wherein to hinder be to be made up of silicon/germanium/different connected structure of silicon for the emitter-base bandgap grading and the collection utmost point.
Fig. 9 c is for showing the p type SBQWRTT shown in Fig. 9 b, the energy band diagram when the resonance bias voltage, and wherein to hinder be to be made up of silicon/germanium/different connected structure of silicon for the emitter-base bandgap grading and the collection utmost point.
Figure 10 a works as W for being presented at p type SBQWRTT
EB=W
CB=15 atomic layers and q Φ
Bp=0.2,0.3,0.4eV, its electric hole and electrons tunnel electric current (J
TpAnd J
Tn) and base voltage V
BRelation.
Figure 10 b works as W for being presented at p type SBQWRTT
EB=W
CB=11,15,19 atomic layers, its subcritical swing and q Φ
BpRelation.
Figure 10 c works as W for being presented at p type SBQWRTT
EB=W
CB=11,15,19 atomic layers, in the time of in off position, its J
Tp/ J
TnRatio and q Φ
BpRelation.
Figure 11 a works as W for being presented at p type SBQWRTT
Si, 2=6,9,12 atomic layers, when conducting state, its electricity pierces tunnel electric current J
TpWith W
GeRelation.
Figure 11 b works as W for being presented at p type SBQWRTT
Si, 2=6,9,12 atomic layers, its subcritical swing and W
GeRelation.
Figure 11 c works as W for being presented at p type SBQWRTT
Si, 2=6,9,12 atomic layers, in the time of in off position, its J
Tp/ J
TnRatio and W
GeRelation.
Figure 12 a works as W for being presented at p type SBQWRTT
Ge=10,14,18 atomic layers, when conducting state, its electricity pierces tunnel electric current J
TpWith W
Si, 2Relation.
Figure 12 b works as W for being presented at p type SBQWRTT
Ge=10,14,18 atomic layers, its subcritical swing and W
Si, 2Relation.
Figure 12 c works as W for being presented at p type SBQWRTT
Ge=10,14,18 atomic layers, in the time of in off position, its J
Tp/ J
TnRatio and W
Si, 2Relation.
Figure 13 a works as W for being presented at p type SBQWRTT
Ge=10,14,18 atomic layers, its electric hole and electrons tunnel electric current (J
TpAnd J
Tn) and V
BRelation.
Figure 13 b works as W for being presented at p type SBQWRTT
Ge=10,14,18 atomic layer and V
B=0V, its electricity pierces the relation of coefficient and energy.
Figure 14 a works as W for being presented at p type SBQWRTT
Si, 2=6,9,12 atomic layers, its electric hole and electrons tunnel electric current (J
TpAnd J
Tn) and V
BRelation.
Figure 14 b works as W for being presented at p type SBQWRTT
Si, 2=6,9,12 atomic layer and V
B=0V, its electricity pierces the relation of coefficient and energy.
Figure 15 a is for showing 2 different V
C, at the electrons tunnel electric current J of n type SBQWRTT
TnThe electricity that reaches at p type SBQWRTT pierces tunnel electric current J
TpWith V
BRelation.
Figure 15 b is for showing the J of n type SBQWRTT and p type SBQWRTT
t-V
CCharacteristic.
Figure 15 c is the transmission curve and the circuit diagram of SBQWRTT inverter.
Figure 16 is by a n type SBQWRTT and the inverter circuit that p type SBQWRTT is formed, the vertical view of its layout.
Figure 17 a is the SBQWRTT inverter of Figure 16, after crystalline substance of heap of stone and oxidate, and the cross-sectional figure of its layer structure.
Figure 17 b is the cross-sectional figure along the SBQWRTT inverter of B-B ' the tangent line institute intercepting of Figure 16.
Figure 17 c is the cross-sectional figure along the SBQWRTT inverter of C-C ' the tangent line institute intercepting of Figure 16.
Figure 17 d is the cross-sectional figure along the SBQWRTT inverter of D-D ' the tangent line institute intercepting of Figure 16.
Figure 18 is its energy band diagram of n type SBQWRTT that the superlattice base structure is arranged.
Figure 19 a is the n type SBQWRTT that shows the superlattice base structure, its subcritical swing and electrons tunnel electric current J
TnWith W
SRelation.
Figure 19 b works as W for showing n type SBQWRTT
S=8,12,16 atomic layers, its electronics and electricity pierce tunnel electric current (J
TnAnd J
Tp) and V
BRelation.
The primary clustering symbol description:
30 SBQWRTT, 31 emitter regions
32 emitter-base bandgap gradings can hinder 33 base regions, district
34 base stages can hinder district's 35 collector regions
36 emitter-base bandgap gradings, 37 base stages
The 38 collection utmost points
41～44 electronic energies resistance height, 45～48 electric holes can hinder height
90 emitter-base bandgap gradings can hinder district's 91 collection utmost points can hinder the district
92,94 silicon fimls, 93,96 germanium films
95,97 silicon fimls, 98 conductive strips skew
99 valence band offset, 1601 n service areas
1602 n base area, 1611 p service areas
1612 p base area, 1621 ground
1622 inputs, 1623 outputs
1624 VCC, 1631 n emitter-base bandgap grading contacts
1632 n base contacts, 1633 n collector dots
1641 p emitter-base bandgap grading contacts, 1642 p base contacts
1643 p collector dots, 1701 Silicon Wafers
1702 calcirm-fluoride films, 1703 silicon buffer films
1704 cobalt disilicide film, 1705 silicon/germanium/silicon composite membrane
1706 cobalt disilicide film, 1707 silicon/germanium/silicon composite membrane
1708 cobalt disilicide film, 1709 silicon buffer films
1710 calcirm-fluoride films, 1711 silicon buffer films
1712 nickel disilicide films, 1713 silicon fimls
1714 nickel disilicide films, 1715 silicon fimls
1716 nickel disilicide films, 1717 silicon dioxide films
1722 n base portion tablelands, 1721 n top electrodes tablelands
1724 p base portion tablelands, 1723 p top electrodes tablelands
1731 layers of border dielectric layer 1741 sidewall spacer body
1742 sidewall spacer bodies, 1743 haptic elements
1751 dielectric layer 1752 metals-1 layer
Embodiment
The present invention will provide detailed reference data that preferred embodiment is described, and provide icon as example.Though borrowing these embodiment that the present invention is described, be not that intention limits the invention to these embodiment.On the contrary, the claim of the application's book will define marrow of the present invention and scope, principle according to this, and the present invention should be contained other various replacement schemes, modification and equivalent method.In addition, in the narration below the present invention, for enabling thoroughly to understand content of the present invention, with numerous specific being described in detail are provided.Yet the personage who in this field, has ordinary skill is all clear, desires embodiment of the present invention, and need not these details.On the other hand, method, program, assembly and the circuit of general convention do not add at this and to be described in detail, and are not that intention is hidden content of the present invention.
Schottky can hinder quantum well resonance, and to wear tunnel transistor (SBQWRTT) be a kind of three end assemblies that metal-semiconductor-metal-semiconductor-metal (MSMSM) structure is arranged.Fig. 3 shows the sketch map of a SBQWRTT30.That three end is emitter-base bandgap grading 36, base stage 37 and the collection utmost point 38.This MSMSM structure by emitter region 31, emitter-base bandgap grading can hinder district 32, base region 33, the collection utmost point can hinder distinguish 34 and 35 of collector regions form.Emitter region 31, base region 33 and collector region 35 are to be made up of metal, metallic compound, metal silicide or the germanium metal Chemistry and Physics Institute.Emitter-base bandgap grading can hinder district 32 and the collection utmost point can hinder that to distinguish 34 be to be made up of semiconductor, the semi-conductive different connected structure that it can be the individual layer semiconductor or different band gaps are arranged.These semiconductor layers can not be doped (to reduce the inequality of particle to the collision and the distribution of reduction doping content of impurity) or are doped.In this structure, there are 4 Schottky can hinder joint.Metal (or metal silicide) can hinder joint with the semi-conductive tight generation Schottky that contacts.W
BBe the width (or thickness) of base region, W
EBBe the width (or thickness) that emitter-base bandgap grading can hinder district 32, W
CBIt is the width (or thickness) that the collection utmost point can hinder district 34.When making this structure with brilliant method of heap of stone, so-called width, that is be the thickness on the vertical direction.Therefore, the width in zone, the also thickness of presentation layer sometimes.Emitter region 31, emitter-base bandgap grading can hinder district 32, base region 33, the collection utmost point and can hinder district 34 and collector region 35 and also can be called as emitter layer, emitter-base bandgap grading respectively and can hinder layer, base layer, the collection utmost point and can hinder layer and collect utmost point layer.Emitter region 31, base region 33 and the collector region 35 of conduction also can be collectively referred to as electrode layer.In this specification, " end " (Terminal), " electronics end " (Electrical Terminal) or " electrode " (Electrode) represent to be used for an electronic contact zone of semiconductor subassembly is connected to an external circuit.Electric conducting material, for example metal can be used to form terminal.
SBQWRTT can be symmetry or asymmetric assembly.For instance, emitter-base bandgap grading can hinder district 32 and the collection utmost point and can hinder and distinguish 34 identical or different width, doping content or semi-conducting material can be arranged.Emitter region 31 and collector region 35 can be made with identical or different metal or silicide.When SBQWRTT was symmetric component, its emitter-base bandgap grading 36 was interchangeable on circuit design with the collection utmost point 38.
Fig. 4 a～4e shows the energy band diagram of a n type SBQWRTT under different bias condition: condition (a) is a heat balance, that is V
E=V
B=V
C=0V, condition (b-d) is V
B＞0V, V
C=V
CCAnd V
E=0V, condition (e) is V
C=V
CCAnd V
E=V
B=0V.E
CBe conduction band edge, E
VBe valence band edge, E
FBe fermi level, V
CCIt is supply voltage.Four Schottky can hinder (emitter-base bandgap grading can hinder the district-to-emitter-base bandgap grading, emitter-base bandgap grading can hinder district-to-base stage, the collection utmost point can hinder district-extremely-base stage and collect the utmost point can hinder district-extremely-the collect utmost point), can hinder highly q Φ to electronics
Bn(Schottky Barrier Height SBH), puts on 41,42,43 and 44 respectively.Four Schottky can hinder (emitter-base bandgap grading can hinder the district-to-emitter-base bandgap grading, emitter-base bandgap grading can hinder district-to-base stage, the collection utmost point can hinder district-extremely-base stage and collect the utmost point can hinder district-extremely-the collect utmost point), can hinder highly q Φ to electric hole
Bp, put on 45,46,47 and 48 respectively.This SBQWRTT can be called " H transistor " for short because in Fig. 4 a the energy band diagram of dumbbell shape, look like English alphabet " H ".
This SBQWRTT has two kinds of complementary component types, that is n type and p type.At n type SBQWRTT, its main carrier is an electronics, and at p type SBQWRTT, its main carrier is electric hole.In circuit design, need two kinds of complementary component types, to reduce power consumption.The CMOS technology is very successful so far, and partly cause is that it has two kinds of complementary component types, thereby reduces power consumption.At n type SBQWRTT, can hinder height q Φ to the Schottky of electronics
Bn41-44 can hinder height q Φ less than the Schottky to electric hole usually
Bp45-48.At p type SBQWRTT, can hinder height q Φ to the Schottky in electric hole
Bp45-48 can hinder height q Φ less than the Schottky to electronics usually
Bn41-44.
Schottky junctions is combined in conductive strips and valence band produces discontinuous.Schottky engages and can be used to set up different connected structure, is similar to the different connected structure that the III-V compound semiconductor by different band gaps is constituted.Both operation principles all can be according to quantum-mechanical effect.The conductive strips of SBQWRTT form the dual intensity resistance quantum well shown in Fig. 4 a.The fermi level of base stage is lower than emitter-base bandgap grading can hinder and collect the conductive strips ability rank that the utmost point can hinder, and differs the Φ into electronics SBH q
Bn42 and 43.If the width W of base stage
B(that is thickness of quantum well) less than the De Buluoyi wavelength, then electronics in quantum well, engage the motion of vertical direction with Schottky will be by quantization.Electronics can only have discontinuous ability rank value in quantum well.E
1It is the ground state energy (Ground State Energy) in quantum well.E
1Depend primarily on W
B, basically with W
EBAnd W
CBIrrelevant.
In Fig. 4 b-d, improve base voltage gradually, and still keep V
E=0V and V
C=V
CCOn energy band diagram, the ability rank in the quantum well are because of V
BImprove and descend.Fig. 5 a shows that electronics is by the penetrating coefficient (Transmission Coefficient) and the relation of injecting the energy of electronics of emitter-base bandgap grading to the collection utmost point.Fig. 5 b shows the current-voltage characteristic curve of n type SBQWRTT.Separate one dimension Schroedinger equation, can obtain penetrating coefficient.Wear the tunnel electric current and be proportional to the vague and general probability that occupies probability and collector region that penetrating coefficient multiply by the emitter region.Correspond to three kinds of different bias condition in Fig. 4 b-d respectively in three working points that are denoted as B, C and D in Fig. 5 b.
In Fig. 4 b, the fermi level in emitter-base bandgap grading is lower than E
1The time, only there is energy to equal E
1High-energy electron can penetrate dual intensity resistance.The relation of electron density and energy is followed Fermi-MICHAEL DRAKE distribution (Fermi-Dirac Distribution).Along with V
BIncrease, will have its energy of more electronics to equal E
1So, wear tunnel electric current and V
BThe relation that presents the index direct ratio.In theory, at room temperature, can obtain minimum subcritical swing is KT/qln (10)=60mV/dec, and it is limited by Fermi-MICHAEL DRAKE and distributes.
When base voltage continues to increase fermi level in the emitter-base bandgap grading and E
1In the time of quite, shown in Fig. 4 c.If the energy of incident electron equal in the quantum well discontinuous one of them that can rank, then it can penetrate this dual intensity resistance quantum well fully, penetrating coefficient can reach 100%, shown in Fig. 5 a.This phenomenon is called resonance, maximum electric current is arranged through this structure this moment.In Fig. 5 b, this peak current is denoted as C.
When base voltage further increased, along with energy E departs from discontinuous ability rank, penetrating coefficient reduced rapidly.Penetrate in emitter-base bandgap grading, having the ability for the electronics of dual intensity resistance, the vague and general attitude of identical energy must be arranged in the collection utmost point.If E
1Be lower than the fermi level of the collection utmost point, shown in Fig. 4 d, the vague and general attitude in the collection utmost point will be seldom.The electron amount that can wear tunnel will reduce, and cause less valley point current, shown in Fig. 5 b.
Fig. 4 e shows a kind of bias condition, V
C=V
CCAnd V
E=V
B=0V, this moment, this assembly had the base stage leakage current.33 li electronic energy penetrates the collection utmost point and can hinder and distinguish 34 and arrive collector region 35 in the base region.Because of quantum-mechanical restriction, in quantum well, have only discontinuous can the existence on rank.In the two-dimentional system of quantum well, (Density of States) is very low for state density, so the base stage leakage current is very little.
As far as the n type SBQWRTT shown in Fig. 4 a, can hinder layer width (W
EBAnd W
CB), base width (W
B), Schottky can hinder the height (q Φ
Bn41-44 and q Φ
Bp45-48) all be important design parameter.In following paragraph, we will be with n type symmetry SBQWRTT, at supply voltage V
CC=0.2V running is discussed these design parameters for example, how to influence its component characteristic, for example drive current, subcritical swing and leakage current.
To n type symmetry SBQWRTT in following condition: emitter-base bandgap grading can hinder district 32 and collect the utmost point and can hinder and distinguish 34 and constitute W by undoped (100) silicon
EB=W
CB, emitter region 31, base region 33 and collector region 35 constitute W by (100) nickel disilicide
B=2 atomic layers (Monolayers, ML), V
E=0V, V
C=0.2V.Engage its electronic energy resistance height q Φ with Schottky between (100) silicon between (100) nickel disilicide
BnBe 0.4eV.Fig. 6 a shows that electronics and electricity pierce tunnel electric current (J
TnAnd J
Tp) and base voltage V
BRelation, W wherein
EB=W
CB=13,19,25 atomic layers.J
TnThe electrons tunnel electric current of expression from emitter-base bandgap grading to the collection utmost point, J
TpThe electricity of expression from the collection utmost point to emitter-base bandgap grading pierces the tunnel electric current.Electronics and electricity pierce the tunnel electric current all along with hindering layer thickness (W
EBWith W
CB) reduce and increase.As far as n type SBQWRTT, electronics is main carrier, and electric hole current then is a leakage current.
Because of tunnel is worn in resonance, all phenomenons of appearance of negative difference resistance are flowed in electron stream and electric hole.Wear the tunnel assembly for resonance, negative difference resistance can be used for the generation of microwave and the application of amplification.Yet for general purpose transistor, the negative difference electricresistance effect is understood serious reduction drive current and is influenced subcritical swing.This assembly must operate under suitable bias voltage, so that negative difference resistance can not occur when normal circuit operation.In the situation of Fig. 6 a, the negative difference electricresistance effect occurs in V
B＞0.23V.If supply voltage V
CCBe located at 0.2V, then the negative difference electricresistance effect will not occur in normal circuit running.
Fig. 6 b shows penetrating coefficient and the relation of energy, the wherein W of electronics
EB=W
CB=13,19,25 atomic layer and V
B=0V.When the energy that injects electronics equals E
1When (about 0.23eV), penetrating coefficient reaches its maximum 100%.We find, E
1Basically with can hinder layer thickness (W
EBAnd W
CB) irrelevant.When energy deviation resonance energy, penetrating coefficient then descends rapidly.If it is thicker to hinder layer, this phenomenon is then obvious more especially.If can hinder layer attenuation, dual intensity resistance quantum well becomes to carrier and is easy to penetrate.Resonance in the penetrating coefficient curve is worn the tunnel spike and is become more fuzzy.
Fig. 6 c shows that subcritical swing is (between V
B=0 and 0.2V between) and the electrons tunnel electric current J during conducting state
Tn(work as V
B=0.2V) with can hinder the relation of layer thickness, W wherein
EB=W
CBReduce along with hindering layer thickness, electrons tunnel current stabilization ground increases.Work as W
EB=W
CB=19 atomic layers, subcritical swing has minimum value 73.2mV/dec.In the time hindering layer thickness and be greater than or less than 19 atomic layers, it is big that subcritical swing becomes.Work as W
EBWith W
CBDuring all less than 12 atomic layers, it is big that subcritical swing promptly becomes.When hindering layer thickness too hour, can hinder layer and can not be limited in the quantum state in the dual intensity resistance quantum well.Dual intensity resistance quantum well becomes transparent for carrier, and the resonance tunneling effect thickens.At this moment, the on/off current ratio diminishes, and subcritical swing becomes big.The resistance thickness W of Canon
EB=W
CB=19 atomic layers, it is worth much smaller than the average free flight distance of the electronics of undoped silicon (MeanFree Path), so electronic energy penetrate can hinder the layer and do not collide.Emitter-base bandgap grading can hinder district 32 and the collection utmost point and can hinder the district and 34 preferably undope, with coulomb collide (the Coulomb Scattering) that reduces that inequality that doping content distributes and ionized impurity cause.
Base width W
BMust be little, reach transistor switch speed apace to reach high current gain.Injecting the energy of electronics of 33 li of base regions, comparable 33 li fermi level exceeds several kT in the base region, and wherein k is a Boltzmann's constant, and T is a lattice temperature.These electronics are called as hot electron, because they and lattice are not in heat balance.These hot electrons are to pass through base region 33 at a high speed, so can obtain short transmission time and big current gain.Electron density in the metal is very high.Inject the electronics of base region 33, because of not flexible electronics and electron collision have high energy loss probability.Therefore the average free flight distance of electronics of metal is much smaller than semiconductor.In the metal at room temperature, to the electronics of its energy about 0.4eV more than fermi level, the mean free time between its carrier collision is about 10 to 100fs, and this average free flight distance that corresponds to is about 10 and arrives
(suppose that carrier speed is about 10
7Cm/s).Distance between the emitter-base bandgap grading and the collection utmost point can be followed ballistic trajectory less than average free flight distance from the hot electron of emitter injection, apace through dual intensity resistance and quantum well, arrives the collection utmost point.
Component characteristic depends on base width W consumingly
BN type symmetry SBQWRTT is in following condition: emitter-base bandgap grading can hinder district 32 and collect the utmost point and can hinder and distinguish 34 and constitute W by undoped (100) silicon
EB=W
CB=19 atomic layers, emitter region 31, base region 33 and collector region 35 constitute V by (100) nickel disilicide
E=0V, and V
C=0.2V.Engage its electronic energy resistance height q Φ with Schottky between (100) silicon between (100) nickel disilicide
BnBe 0.4eV.Fig. 7 a shows that electronics and electricity pierce tunnel electric current (J
TnAnd J
Tp) and base voltage V
BRelation, W wherein
B=1,2,3 atomic layers.Fig. 7 b shows the relation of penetration of electrons coefficient and energy, wherein W
B=1,2,3 atomic layers, V
B=0V.Fig. 7 c shows that subcritical swing is (between V
B=0 and 0.2V between) and electrons tunnel electric current J
Tn(work as V
B=0.2V) and W
BRelation.Shown in Fig. 7 b, resonance energy is along with W
BIncrease and reduce.Shown in Fig. 7 c, work as W
BIncrease to 2 atomic layers from 1 atomic layer, electrons tunnel electric current J
TnIncrease.Shown in Fig. 7 b, work as W
BIncrease to 3 atomic layers, E from 2 atomic layers
1Become less than 0.2eV.If the negative difference electricresistance effect occurs in V
CCWithin the operational range, then can reduce drive current and increase subcritical swing.Less W
BCan obtain bigger E
1And wider V
CCOperational range.Yet, if E
1Much larger than V
CC, then drive current maybe be big inadequately.Therefore, E
1Must be greater than V
CC, but can not be too big.Show W like Fig. 7 c
BHave an optimum value, so that drive current is maximum and subcritical swing is minimum.
Component characteristic also depends on that Schottky can hinder height.N type symmetry SBQWRTT is in following condition: emitter-base bandgap grading can hinder district 32 and collect the utmost point and can hinder and distinguish 34 and constitute W by undoped (100) silicon
EB=W
CB=19 atomic layers, emitter region 31, base region 33 and collector region 35 are made up of W identical metal
B=2 atomic layers, V
E=0V, and V
C=0.2V.Suppose that this metal engages with the Schottky of (100) silicon, its electronic energy resistance highly is q Φ
BnFig. 8 a shows that electronics and electricity pierce tunnel electric current (J
TnAnd J
Tp) and base voltage V
BRelation, q Φ wherein
Bn=0.24,0.4,0.56eV.Fig. 8 b shows the relation of penetration of electrons coefficient and energy, wherein q Φ
Bn=0.24,0.4,0.56eV, and V
B=0V.Fig. 8 c shows that subcritical swing is (between V
B=0 and 0.2V between) and electrons tunnel electric current J
Tn(work as V
B=0.2V) with q Φ
BnRelation.As q Φ
BnDuring reduction, E
1Can reduce, and J
TnCan raise.As q Φ
BnDuring=0.32eV, E
1=0.2eV, J at this moment
TnReach its peak value.If q Φ
BnFurther reduce, then J
TnCan begin to reduce, swing then can significantly increase, because at V
CCNegative difference resistance phenomenon takes place in the working range of=0.2V.
To component design, it highly is an important parameter that Schottky can hinder.Schottky can hinder and highly depend on working metal function, crystallization direction and surface condition.Schottky for most metal/silicon and silicide/silicon engages, and the fermi level of silicon face is usually located at E near middle band gap (Mid Band Gap)
iIn the scope of ± 0.4eV, E wherein
iFermi level when being non-impurity-doped.In theory, SBQWRTT can be dipole elements (Ambipolar Device), can be taken as the n type or the p transistor npn npn is operated, and depends on bias condition.Dipole elements can significantly be simplified processing procedure, because need only make one type assembly.In dipole elements, available metal of the same race constitutes different conducting positions, for example emitter region 31, base region 33 and collector region 35.Though electronics has higher effective Jason Richardson constant (Effective Richardson Constant) and less effective mass than electric hole, if q is Φ
BnBe slightly larger than q Φ
Bp, then dipole elements can have the drive current of symmetry, promptly is J
Tn=J
TpYet, show like Fig. 8 c, if q Φ
BnGreater than 0.56eV (half of silicon band gap), then drive current will be less than 10
4A/cm2.Though dipole elements has better simply processing procedure, its usefulness is not best.For making n type and p type assembly all can reach best usefulness, various assembly should independently carry out optimized design individually.
In theory, the structure of p type SBQWRTT can be similar to the structure of the n type SBQWRTT shown in Fig. 4 a, but the fermi level of its metal is than the valence band edge near silicon.The energy band diagram of p type SBQWRTT when Fig. 9 a is presented at heat balance.This p type SBQWRTT has following characteristic: emitter-base bandgap grading can hinder district 32 and the collection utmost point and can hinder and distinguish 34 and constitute W by undoped (100) silicon
B=2 atomic layers.It highly is q Φ that electric hole Schottky between emitter region 31, base region 33 and collector region 35 and (100) silicon can hinder
BpThe bias voltage of this p type SBQWRTT is V
E=0V and V
C=-0.2V.Figure 10 a shows electric hole and electrons tunnel electric current (J
TpAnd J
Tn) and base voltage V
BRelation, W wherein
EB=W
CB=15 atomic layers and q Φ
Bp=0.2,0.3,0.4eV.As q Φ
BpDuring minimizing, E
1Also can and then reduce, negative difference resistance phenomenon can appear at less base voltage.Because there are less effective Jason Richardson's constant and bigger effective mass in electric hole than electronics, so q Φ
BpMust be less than 0.3eV, with drive current that promotes electric hole and the leakage current that reduces electronics.Figure 10 b shows that subcritical swing is (between V
B=0 and-0.2V between) with q Φ
BpRelation, W wherein
EB=W
CB=11,15,19 atomic layers.Figure 10 c demonstration, in the time of in off position, the ratio J of electric hole and electronic leakage current
Tp/ J
TnWith q Φ
BpRelation, W wherein
EB=W
CB=11,15,19 atomic layers.Reduce q Φ
Bp, help to improve J
Tp/ J
TnRatio.For obtaining rational J
Tp/ J
TnRatio, for example greater than 1, q Φ
BpMust be less than 0.25eV.Yet, as q Φ
BpToo hour, because negative difference resistance phenomenon, subcritical swing will be seriously influenced.Bigger can hinder layer width W
EBAnd W
CBPerhaps can improve J a little
Tp/ J
TnRatio, but can reduce drive current.
The emitter-base bandgap grading of this p type SBQWRTT can hinder district 32 and the collection utmost point and can hinder and distinguish 34 and can adopt different connected structure, with the awkward situation of solution drive current and subcritical swing.The energy band diagram of p type SBQWRTT when Fig. 9 b is presented at heat balance.It is that (its thickness is W by silicon fiml 92 that emitter-base bandgap grading can hinder district 90
Si, 1), (its thickness is W to germanium film 93
Ge) and silicon fiml 94 (its thickness is W
Si, 2) constitute.It is that (its thickness is W by silicon fiml 95 that the collection utmost point can hinder district 91
Si, 1), (its thickness is W to germanium film 96
Ge) and silicon fiml 97 (its thickness is W
Si, 2) constitute.In the different conductive strips skew that engages 98 of silicon and germanium and valence band offset 99 is respectively 0.28 and 0.74eV.Fig. 9 c shows the energy band diagram of p type SBQWRTT when the resonance bias voltage, and the energy that wherein injects electric hole approximates ability rank E
1, this moment, penetrating coefficient was maximum.
The p type SBQWRTT of modular construction shown in Fig. 9 b, its characteristic also depends on the thickness (W of silicon fiml and germanium film
Si, 1, W
GeAnd W
Si, 2).Suppose that a p type SBQWRTT has following characteristic: emitter-base bandgap grading can hinder district 90 and the collection utmost point can hinder that to distinguish 91 be the different connected structure of silicon/germanium/silicon, W
Si, 1=2 atomic layers, emitter region 31, base region 33 and collector region 35 are constituted W by (100) cobalt disilicide
B=2 atomic layers, V
E=0V, and V
C=-0.2V.Engage with Schottky between (100) silicon between (100) cobalt disilicide, its electric hole Schottky can hinder height q Φ
BpBe 0.38eV.Figure 11 a shows that when conducting state, electricity pierces tunnel electric current J
TpWith W
GeRelation, W wherein
Si, 2=6,9,12 atomic layers.Figure 11 b shows that subcritical swing is (between V
B=0 and-0.2V between) and W
GeRelation, W wherein
Si, 2=6,9,12 atomic layers.Figure 11 c demonstration, in the time of in off position, current ratio J
Tp/ J
TnWith W
GeRelation, W wherein
Si, 2=6,9,12 atomic layers.Shown in Figure 11 a, drive current J
TpTwo spikes are arranged, appear at W generally
Ge=5 and 15 atomic layers.Work as J
TpWhen becoming maximum, subcritical swing is minimum generally.The different connected structure of this silicon/germanium/silicon forms quantum well to electric hole.Transistor arrangement shown in Fig. 9 b has three quantum wells.Discontinuous ability rank in this silicon/germanium/silicon quantum well also can influence resonance and wear tunnel.Penetrating coefficient can have a spike in resonance energy E
1, as dual intensity resistance quantum well, or a plurality of spikes are arranged, because a plurality of quantum wells are arranged, its difference depends on the thickness W of this germanium film basically
GeWhen penetrating coefficient had a plurality of spikes in different-energy, subcritical swing can be seriously influenced.Because the conduction band edge of germanium is high than silicon, germanium film 93 and 96 effectively block electrons is worn the tunnel electric current.Shown in Figure 11 c, work as W
GeIncrease the current ratio J in the time of in off position
Tp/ J
TnUsually can increase.
Figure 12 a shows that when conducting state, electricity pierces tunnel electric current J
Tp(V
B=-0.2V) and W
Si, 2Relation, W wherein
Ge=10,14,18 atomic layers.Figure 12 b shows that subcritical swing is (between V
B=0 and-0.2V between) and W
Si, 2Relation, W wherein
Ge=10,14,18 atomic layers.Figure 12 c demonstration, in the time of in off position, current ratio J
Tp/ J
TnWith W
Si, 2Relation, W wherein
Ge=10,14,18 atomic layers.When conducting state, electricity pierces tunnel electric current J
TpAlong with W
Si, 2Reduce and increase.Work as W
GeDuring=14 atomic layers, if W
Si, 2Greater than 14 atomic layers, then subcritical swing becomes minimum.Work as W
Si, 2During less than 7 atomic layers, subcritical swing is along with W
Si, 2Reduce and rapid riseing.When hindering layer thickness W
Si, 2Too hour, this can hinder and almost become transparent to carrier.Accurate bound state can't be restricted within the quantum well.At this moment, the spike of penetrating coefficient when resonance energy thickens unclear, and the on/off current ratio descends, and also variation of subcritical swing.N type SBQWRTT shown in Fig. 6 c also can be observed similar phenomenon.
What Figure 13 a showed electric hole and electronics wears tunnel electric current (J
TpAnd J
Tn) and base voltage V
BRelation, W wherein
Ge=10,14,18 atomic layers.Figure 13 b shows the relation that electricity pierces coefficient and energy, wherein W
Ge=10,14,18 atomic layer and V
B=0V.At Figure 13 a and 13b, W
Si, 2=9 atomic layers.Improve germanium film thickness W
Ge, can suppress the leakage current of electronics effectively.An interesting phenomenon appears in the different connected structure of this silicon/germanium/silicon, works as W
GeDuring=18 atomic layers, the penetrating coefficient curve has another spike at low-yield (about 0.05eV).The different connected structure of this silicon/germanium/silicon forms a quantum well to electric hole.When a plurality of quantum well, a plurality of spikes possibly appear in penetrating coefficient.At this moment, the current ratio J during closed condition
Tp/ J
TnDiminish, and subcritical swing becomes big.
Figure 14 a shows electric hole and electrons tunnel electric current (J
TpAnd J
Tn) and base voltage V
BRelation, W wherein
Si, 2=6,9,12 atomic layers.Figure 14 b shows the relation that electricity pierces coefficient and electric hole energy, wherein W
Si, 2=6,9,12 atomic layers.At Figure 14 a and 14b, W
Ge=14 atomic layers.J
TnAnd J
TpAll along with W
Si, 2Reduce and increase.Almost become transparent when hindering thickness too hour, can hindering to carrier.At this moment, accurate bound state can't be restricted within the quantum well.Electricity pierce coefficient with regard to the tangible spike of neither one at resonance energy.For instance, work as W
Si, 2During=6 atomic layers, the penetrating coefficient curve shown in Figure 14 b is exactly quite mild.At this moment, the electric hole of wide energy range all might penetrate dual intensity resistance quantum well.So work as W
Si, 2Too hour, the resonance tunneling effect dies down, and subcritical swing variation.
Table 1 shows the optimal components structure that is got by simulation calculation.Table 2 shows its component characteristic.To n type SBQWRTT, J
T, onBe when conducting state, (to work as V
B=V
C=0.2V) drive current, J
T, offBe (to work as V in off position the time
B=0V and V
C=0.2V) leakage current, V
T, linBe to work as J
Tn=1 * 10
3A/cm
2And V
CV during=0.01V
B, V
T, satBe to work as J
Tn=1 * 10
3A/cm
2And V
CV during=0.2V
B, the resistance of drain induction energy descends, and (Drain Induced Barrier Lowering DIBL), according to the used definition of MOSFET, is to be (V
T, lin-V
T, sat)/(0.2V-0.01V).Emitter grounding, i.e. V
E=0V.To p type SBQWRTT, the polarity of terminal voltage is opposite.
Table 1
| Structural parameters | N type SBQWRTT | P type SBQWRTT |
| The emitter-base bandgap grading emitter-base bandgap grading can hinder the base stage collection utmost point and can hinder collection extreme direction Schottky and can hinder highly | NiSi 2 Si，W EB＝19ML NiSi 2，W B＝2ML Si，W CB＝19ML NiSi 2 (100) qΦ bn＝0.4eV | CoSi 2 Si/Ge/Si，W Si，1/W Ge/W Si，2＝2/14/9ML CoSi 2，W B＝2ML Si/Ge/Si，W Si，1/W Ge/W Si，2＝2/14/9ML CoSi 2 (100) qΦ bp＝0.38eV |
Table 2
| Component parameter | N type SBQWRTT | P type SBQWRTT |
| J t，on(A/cm 2) J t，off(A/cm 2) J t，on/J t，off Swing(mV/dec) V t，lin(V) V t，sat(V) DIBL(mV/V) V CC(V) | 2.13×10 5 3.95×10 2 539 73.2 0.079V 0.03V 262 0.2 | 1.24×10 5 2.38×10 2 520 73.6 -0.077V -0.044V 177 0.2 |
Figure 15 a shows the electrons tunnel electric current J of n type SBQWRTT
TnAnd the electricity of p type SBQWRTT pierces tunnel electric current J
TpWith V
BRelation, its V
CValue is referring to table one.Work as V
BAt V
CCScope in, wear tunnel electric current J
tWith V
BBe index growth relation.For MOSFET, I
DOnly in subcritical district, be only V
GExponential function.When MOSFET assembly during in complete conducting, I
DNo longer with V
GIncrease and be exponential relationship and continue increase log (I
D)-V
GCurve presents saturated phenomenon.
Figure 15 b shows the J of n and p type SBQWRTT
t-V
CCharacteristic.The drive current of n type SBQWRTT exceeds about 70% than the drive current of p type SBQWRTT.If p type SBQWRTT is greater than n type SBQWRTT, then this p type SBQWRTT can operate with this n type SBQWRTT pairing.Shown in Figure 15 b, the J of this n type SBQWRTT
TnWith V
CIncrease and continue to increase unsaturated phenomenon.But for this p type SBQWRTT, when | V
C| during greater than 0.1V, J
TpAppear and V
CSaturated phenomenon.Because structural difference, p type SBQWRTT has less DIBL than n type SBQWRTT.The emitter-base bandgap grading of this p type SBQWRTT can hinder district 90 and the collection utmost point, and hinder the district 91 be to be made up of silicon/germanium/different joint of silicon, and the emitter-base bandgap grading of this n type SBQWRTT can hinder and distinguishes 32 and collect the utmost point and can hinder that to distinguish 34 be to be made up of silicon fiml.J to n and p type SBQWRTT
t-V
CCurve, along with | V
B| increase and evacuate more because J
TnAnd J
TpBe V
BExponential function.Figure 15 c shows the transmission curve (Transfer Curve) and the circuit diagram of SBQWRTT inverter.This p type SBQWRTT is bigger approximately by 50% than this n type SBQWRTT, to compensate its lower drive current.Though SBQWRTT and MOSFET on component characteristic, modular construction and operating mechanism, have many differences, this SBQWRTT inverter also has the transmission curve of balanced, symmetrical and big output/input gain.
Schottky can hinder the difference on ability rank when highly representing main carrier to pass through metal and interface.(its working function is Φ to Schottky-Mo Te theoretical (Schottky-Mott Theory) prediction metal
M) (its electron affinity is X with semiconductor
S) to hinder height should be Φ for the Schottky at interface
Bn=Φ
M-X
SThis Simple Theory has been ignored the reaction between metal and the semiconductor.Experimental observation polycrystalline Schottky diode finds that its Schottky can hinder the height and the working function of metal, does not exist very strong linear relationship between the two.Previously with this phenomenon owing to highdensity interface state, cause fermi level to be fixed.Fermi level mechanism of ammonium fixation, this theory do not think that the atomic structure of metal and silicon interface can influence Schottky and can hinder height.Yet many researchs recently point out that fermi level is not fixed, and interfacial structure can hinder Schottky significant effects is highly arranged.The example of knowing for the people is at the interface of nickel disilicide and silicon (111), and Schottky can hinder the direction that highly depends on silicide.Nickel disilicide can be according to both direction length on silicon (111): silicide has identical direction with substrate in the A type, and silicide is shared surface normal axis (111) with silicon in Type B, but around the relative silicon turnback of this axis.The Schottky of nickel disilicide and n type silicon (111) can hinder height, and the A type is 0.65eV, and Type B is 0.79eV.The another one example is, it highly is 0.4eV that the Schottky of monocrystalline nickel disilicide and silicon (100) can hinder, differ from usually multi-crystal silicification nickel thing and n type silicon (100) observe and 0.6-0.7eV.
Figure 16 is by a n type SBQWRTT and the inverter that p type SBQWRTT forms, the vertical view of its circuit layout.This n type SBQWRTT is repeatedly on this p type SBQWRTT, to save area.To this n type SBQWRTT, top electrodes district (that is collector region) is defined in n service area 1601, and n base area 1602 defines middle and bottom electrical polar region (that is base region and emitter region).To this p type SBQWRTT, top electrodes district (that is emitter region) is defined in p service area 1611, and p base area 1612 defines middle and bottom electrical polar region (that is base region and collector region).The zone of electric current is defined in this n and p service area 1601 and 1611.This p service area 1611 makes this n and p type assembly that the drive current than balance arranged greater than this n service area 1601.The input 1622 of inverter is connected to the base contact 1632 of this n type SBQWRTT and the base contact 1642 of this p type SBQWRTT.The output 1623 of inverter is connected to the collector dot 1633 of this n type SBQWRTT and the collector dot 1643 of this p type SBQWRTT.The emitter-base bandgap grading contact 1631 of this n type SBQWRTT is connected to ground 1621.The emitter-base bandgap grading contact 1641 of this p type SBQWRTT is connected to V
CC1624.
The processing procedure of SBQWRTT below will be described.Figure 17 a is presented at the layer structure after crystalline substance of heap of stone and the oxidate.Figure 17 b-d is after metal-1 step, the cross-sectional figure that is got along B-B ', C-C ' and the D-D ' transversal of Figure 16.(basic air pressure is less than 4 * 10 at ultra high vacuum
-11Torr) under the environment, carry out surface treatment and crystal growth.Parent material is silicon (a 100) wafer 1701.See through repeated oxidation and erosion, clear up this crystal column surface, then thin the and volatile oxide of tool of long one deck.Then, this wafer gets into the settling chamber.This wafer was heated to 950 degree Celsius 10 minutes in ultra high vacuum, and received silicon bundle bump 10 minutes at 780 degree Celsius approximately, then about 30 seconds of the of short duration annealing of 900 degree Celsius approximately, to remove this volatile oxidn and impurity from substrate surface.Remove after the oxide; At 650 degree Celsius approximately; With the silicon buffer film of the long bed thickness about 100 of molecular beam epitaxy method to
; Then in the of short duration annealing of 900 degree Celsius approximately, to guarantee the cleaning of silicon face.
Calcirm-fluoride (CaF
2) be insulator, its band gap is about 12eV.The calcirm-fluoride crystallization is a cube structure, similar diamond structures.Its lattice constant (Lattice Constant) is almost equal with the lattice constant of silicon, and difference has only 0.6%.But mat molecular beam epitaxy method is at the good calcirm-fluoride film of silicon face growth lattice quality.Wafer temperature is about 400 to 650 degree Celsius; With the ultrapure calcirm-fluoride compound of electron beam evaporation, at the calcirm-fluoride film 1702 of silicon wafer surface crystals growth thick about 200 of heap of stone to
.By evaporation calcirm-fluoride solid source, can keep calcium: the stoichiometric ratio of fluorine=1: 2.Then in 600 to 850 degree Celsius annealing rapidly, to reduce interface charge density.This calcirm-fluoride film 1702 provides the insulation of assembly and its infrabasal plate on it.After the calcirm-fluoride growth; Wafer temperature drops to below the 100, and the thin silicon films of deposition growing one bed thickness about 20 to
.This wafer is heated to 600 degree Celsius, and is of heap of stone brilliant with the solid phase of accomplishing previous deposited silicon film.After solid phase brilliant processing procedure of heap of stone, substrate temperature is controlled at 550 to 750 degree Celsius, mat molecular beam epitaxy method, crystals growth one deck silicon fiml of heap of stone.Silicon fiml 1703 on the calcirm-fluoride, gross thickness are about 100 to
Nickel disilicide and cobalt disilicide have the cube lattice, differ with the lattice constant of silicon and are respectively-0.4% and-1.2%.By molecular beam epitaxy method and atom lamination method, under UHV condition, the monocrystalline silicide film of nickel disilicide and cobalt disilicide can be built crystals growth on silicon substrate, and its lattice structure is flawless, and the interface is clearly demarcated.These silicide films have good electron and mechanical property, for example good layer uniformity, high conductivity and good thermal stability.Also can be by molecular beam epitaxy method and atom lamination method, under UHV condition, crystals growth monocrystalline silicon membrane of heap of stone is on silicide film.Silicon engages with the Schottky of silicide (for example nickel disilicide and cobalt disilicide) can form different connected structure, operates according to quantum-mechanical rule.The MSMSM structure of this SBQWRTT can be made up of silicide/silicon/silicide/silicon/different connected structure of silicide, and utilizes ultra high vacuum crystal technique of heap of stone to make.
Under UHV condition, (Two-step Template Method sees people such as Tung at Appl.Phys.Lett.1983, and pp.888-890), what monocrystalline nickel disilicide and cobalt disilicide can successes is grown on silicon (100) surface to use the two-part template method.First step is to be particularly suitable under the condition of tuberculosis, growth model layer, and second step is under the condition that is fit to the homogeneous epitaxial crystals growth, crystals growth of heap of stone on this model layer.Using such method forms thin epitaxial layer at lower temperature earlier, is used as the model layer, then builds crystals growth in higher temperatures.For example, at room temperature,,, deposit the metal or the disilicide of several atomic layers from the electron beam source of each other metal and silicon in the molecular beam epitaxy chamber.In 400 to the 500 of short duration annealing of degree (1 to 5 minute) Celsius approximately afterwards, this brilliant silicide layer of heap of stone is by the required model layer of growing up as follow-up silicide.Under room temperature or higher temperature, according to stoichiometric ratio, plated metal and silicon reach required thickness on this model layer simultaneously, then in 450 to 800 degree annealing Celsius approximately.
Use the processing procedure of two-part growth, in ultra high vacuum molecular beam epitaxy chamber, growth cobalt disilicide film 1704 is on wafer, and this film is the collection utmost point of p type SBQWRTT.At first; At room temperature; According to stoichiometric ratio, deposit cobalt and silicon simultaneously grow the model layer of thick pact
; And in the vacuum of 400 degree Celsius, annealed 1 minute.Grow up to after the thin cobalt disilicide model layer; The setting substrate temperature is 450 degree Celsius; While deposit cobalt and silicon; Growth one deck thicker cobalt disilicide film makes that the gross thickness of this film is 200 to
Silicon/germanium/silicon composite membrane 1705, it is that the collection utmost point of p type SBQWRTT can hinder layer, crystals growth of heap of stone is on wafer.This composite membrane 1705 is made up of 2 layers of silicon, 14 layers of germanium and 9 layers of silicon, and substrate temperature is set at 200 degree Celsius, with atom lamination method, deposits each layer in regular turn.This composite membrane 1705 was 700 degree annealing Celsius 2 minutes then.
Atom lamination method is a kind of by coating technique according to chemical vapour deposition technique.Main difference is that double base is reflected in the atom lamination method and is broken down into two sections half-reaction, with the thickness of accurate controlling diaphragm.Atom lamination method in substrate, reaches the uniformity and the precise thickness of atomic level with successive reaction lining film.In each step, reactant is saturated activated positions on substrate fully, and atom lamination method is become from limiting journey, innately can reach accurate atomic layer and grow up.In the modular construction of SBQWRTT, different layers has different THICKNESS CONTROL requirements.Atom lamination method and molecular beam epitaxy method, these two kinds of crystal techniques of heap of stone are incorporated in this ultra high vacuum settling chamber, can grow each layer of different-thickness.
With atom lamination method, substrate temperature is set at 200 degree Celsius, and growth thickness is the cobalt disilicide film 1706 of 2 atomic layers, and it is the base stage of p type SBQWRTT, and 400 degree annealing Celsius 1 minute.Under the growth condition identical with silicon/germanium/silicon fiml 1705, on wafer, grow silicon/germanium/silicon composite membrane 1707, it is that the emitter-base bandgap grading of p type SBQWRTT can hinder layer.This silicon/germanium/silicon composite membrane 1707 is made up of 9 atomic layer silicon, 14 atomic layer germanium and 2 atomic layer silicon, deposits each layer in regular turn with atom lamination method.The growth condition identical with cobalt disilicide film 1704 grows cobalt disilicide film 1708 on wafer, it is the emitter-base bandgap grading of p type SBQWRTT.
By silicon model technology, with the molecular beam epitaxy method, grown silicon buffer film 1709 on wafer.At first; At room temperature; Deposition of thick is the thin silicon films of
approximately; Then, the of short duration annealing of 500 degree Celsius approximately 2 minutes.This silicon fiml can be used as model, is used for the thicker silicon fiml of subsequent growth, to guarantee silicon nuclear and tectal brilliant direction of heap of stone.Use the molecular beam epitaxy method, substrate temperature is set at 500 degree Celsius, and the grown silicon cover layer is on silicon model layer.The gross thickness of silicon buffer film 1709 about 100 is to
Use the growth condition identical, build crystals growth calcirm-fluoride film 1710 on wafer with calcirm-fluoride film 1702.Calcirm-fluoride dielectric film 1710 provides n type SBQWRTT and its insulation of p type SBQWRTT down on it.
Use the growth condition identical, build crystals growth silicon buffer film 1711 on wafer with silicon fiml 1703. Silicon buffer film 1703,1709 and 1711 purposes are to improve growth lattice structure and consistency of each epitaxial of heap of stone on it.
Use the processing procedure of two-part growth, in ultra high vacuum molecular beam epitaxy chamber, growth nickel disilicide film 1712 is on wafer, and this film is the emitter-base bandgap grading of n type SBQWRTT.At first; At room temperature; According to stoichiometric ratio, nickel deposited and silicon simultaneously grow the nickel disilicide model layer of thick pact
; Then 500 degree annealing Celsius 2 minutes, to carry out the solid phase building crystal to grow.Then; At room temperature; Simultaneously nickel deposited and silicon is on the model layer, makes that the gross thickness of nickel disilicide film is 200 to
then, at 750 degree Celsius; Carried out high annealing 2 minutes, to improve the crystalline quality of nickel disilicide film.
Use atom lamination method, substrate temperature is set at 200 degree Celsius, and growth thickness is the silicon fiml 1713 of 19 atomic layers on wafer, and this film is that the emitter-base bandgap grading of n type SBQWRTT can hinder layer, and 700 degree annealing Celsius 2 minutes.Use atom lamination method, substrate temperature is set at 200 degree Celsius, and growth thickness is the nickel disilicide film 1714 of 2 atomic layers on wafer, and this film is the base stage of n type SBQWRTT, and 800 degree annealing Celsius 1 minute.Use the condition identical with silicon fiml 1713, growth thickness is the silicon fiml 1715 of 19 atomic layers on wafer, and this film is that the collection utmost point of n type SBQWRTT can hinder layer.Use the condition identical with nickel disilicide film 1712; Growth thickness is 200 to the nickel disilicide film 1716 of
on wafer, and this film is the collection utmost point of n type SBQWRTT.The silicon dioxide film 1717 of about
of deposit thickness is used to protect assembly on wafer.Then, remove this wafer from supervacuum chamber.
In this exemplary layout and processing procedure, this SBQWRTT is the formed vertical stratification of crystals growth of heap of stone.This n type SBQWRTT storehouse is on this p type SBQWRTT, to save area.This n and p type SBQWRTT respectively have three silicon compound electrode layers, as its collection utmost point, base stage and emitter-base bandgap grading.From top to bottom, three electrode layers of this n type SBQWRTT are respectively the collection utmost point, base stage and emitter-base bandgap gradings, three electrode layers of this p type SBQWRTT be respectively emitter-base bandgap grading, base stage, with the collection utmost point.In digital circuit, the emitter-base bandgap grading of n type SBQWRTT is ground connection sometimes, and the emitter-base bandgap grading of p type SBQWRTT is received VCC sometimes.For making the signal between these two kinds of assemblies be coupled as minimum, the top electrodes of the bottom electrode of n type SBQWRTT and p type SBQWRTT is to be emitter-base bandgap grading.Can also between these two emitter layers, add the grounding electrode of brilliant silicide layer of heap of stone, further to reduce the signal coupling.
Shown in Figure 17 c, the formation in tableland provides the insulation between contact landing and the adjacent component.N top electrodes tableland 1721 is defined in this n service area 1601.This n base area 1602 defines n base portion tableland 1722.P top electrodes tableland 1723 is defined in this p service area 1611.This p base area 1612 defines p base portion tableland 1724.The Wet-type etching of micro-photographing process and high selectivity is used to form these tablelands.Base area 1602 and 1612 not only defines the zone of base layer 1706 and 1714, also defines the zone of bottom electrode layer 1704 and 1712 simultaneously.Forming base portion tableland 1722 and at 1724 o'clock, semiconductor energy resistance layer 1707 and 1715 is retained on base layer 1706 and 1714, to protect this base layer.After tableland 1721 to 1724 forms; Mat Low Pressure Chemical Vapor Deposition (LPCVD); The layer border dielectric of deposition of silica (Inter-Level Dielectric, ILD) film 1731 is on wafer, and with chemical mechanical milling method (Chemical Mechanical Polishing; CMP) handle, and reach smooth comprehensively.The final thickness of the layer border dielectric layer 1731 on n top electrodes tableland is about
Contact light shield 1631,1632 and 1633 defines the contact hole (Contact Holes) of emitter-base bandgap grading, base stage and the collection utmost point of n type SBQWRTT respectively.Contact light shield 1641,1642 and 1643 defines the contact hole of emitter-base bandgap grading, base stage and the collection utmost point of p type SBQWRTT respectively.The contact of each electrode layer has its light shield and contact etch.Therefore, 6 electrode layers have 6 contact light shields.Use and fit shape sedimentation (Conformal Deposition, for example Low Pressure Chemical Vapor Deposition and atom lamination method) and non-isotropy etching (Anisotropic Etch), inboard at the contact hole that leads to bottom electrode, form silicon nitride (Si
3N
4) sidewall spacer body (Sidewall Spacers) 1741 and 1742, shown in Figure 17 d and 17b.The insulation that sidewall spacer body (1741 and 1742) provides the oneself to align between haptic element (Contact Plug) and base layer (1706 and 1714).If do not adopt the way of sidewall spacer body (1741 and 1742), then need two light shields in addition, to produce the contact tableland of two bottom electrode layer (1704 and 1712), this can increase transistorized size inevitably.Extremely thin because of base layer (1706 and 1714), the thickness of several atomic layers is only arranged, after opening other emitter-base bandgap grading/collection utmost point contact hole, just open the base stage contact hole, remove to avoid other contact etch and photoresistance, base layer is caused over etching and the infringement of electricity slurry.Semiconductor energy resistance layer (1707 and 1715) can be used as etching stopping layer when the base stage contact etch.Metal (for example tungsten) is deposited and filling contact hole, becomes haptic element 1743.Then, use chemical mechanical milling method, remove unnecessary tungsten from crystal column surface, and reach smooth comprehensively.The material 1751 of deposition one deck low-k.Carry out little shadow and etching then, produce the used groove of metal-1 at this dielectric layer 1751.Metal (for example copper) is deposited and grinds, and forms metal-1 layers 1752, connects mutually for assembly.
The SBQWRTT that this specification discloses differs from aforesaid Prior Art assembly (MBT and RTT) in following several respects at least:
1.MBT (Fig. 1 a) has a Schottky to engage (Fig. 1 b) in the MIMS structure to no Schottky joint, in the SMS structure, has two Schottky to engage (Fig. 1 c) in the MIMIM structure.SBQWRTT has four Schottky to engage (Fig. 3) in the MSMSM structure.
2. (Fig. 1 a) or the MBT of MIMS (Fig. 1 b) structure, it is insulator that emitter-base bandgap grading can hinder for MIMIM.For the MBT of MIMS (Fig. 1 b) or SMS (Fig. 1 c) structure, a semiconductor collector region and a quite well atomic layer in full.Near the contact of the collection utmost point, a large amount of doping should be arranged, form low-resistance nurse contact difficult to understand.SBQWRTT has two semiconductor energy resistance districts, that is emitter-base bandgap grading can hinder district 32 and the collection utmost point can hinder district 34.These two can be hindered the thickness (less than
even less than
) that the district has only several atomic layers; And common non-impurity-doped, to reduce the inequality that impurity collision and doping content distribute.
3. MIMIM is arranged, and (Fig. 1 a) or the MBT of MIMS (Fig. 1 b) structure allows electric current can hinder the district through its insulation, and hot carrier passes through insulating barrier, can cause the problem of reliability.SBQWRTT does not have insulating barrier in its current path, so there is not this problem.
4.MBT operation principles do not rely on resonance to wear tunnel.The common bias voltage of this assembly makes and injects the hot electron in the base stage that its energy is far above the fermi level of base stage.Because discontinuous ability rank are comparatively approaching at the higher-energy place, so the hot electron that injects almost has continuous ability rank in base stage.On the other hand, SBQWRTT is very little because of base width, has only ability rank to exist in the quantum well usually.Because of injecting its energy of electronics near first the discontinuous ability rank in quantum well, produce the resonance tunneling effect, significantly promote its drive current.
Though SBQWRTT and traditional RTT have the structure of dual intensity resistance quantum well,, they have following basic difference on modular construction and operating mechanism:
1.RTT the quantum well zone be semiconductor, and the quantum well zone of SBQWRTT is metal or silicide.
Do not engage 2.RTT there is Schottky, and SBQWRTT has four schottky junctions to be combined in its MSMSM structure.
3.RTT, and be mainly used in the for example circuit application of oscillator because of the characteristic of its negative difference resistance.This assembly is biased between spike and the lowest point usually.To most circuit application, negative difference resistance can cause unwelcome vibration and drive current to descend.SBQWRTT is general purpose transistor, and its bias voltage is usually under the peak head, to avoid unwelcome negative difference resistance.
4.RTT a plurality of abilities rank are arranged usually in quantum well, so I-E characteristic shows a plurality of peak values.SBQWRTT has only discontinuous ability rank usually in quantum well.The I-E characteristic of SBQWRTT, (for example BJT and MOSFET) is similar with conventional transistor, does not have a plurality of peak values.
Though describe the present invention with reference to certain embodiments, this describes only is explanation the present invention, is not considered to limit the present invention.Practise in the people of this skill and possibly derive many modifications and application, do not define marrow of the present invention and scope and do not deviate from appended claim.
Figure 18 representative a kind of variation wherein, wherein base stage 1810 is metal and semi-conductive superlattice structure (Superlattice Structure).According to traditional definition, superlattice are by the semiconductor lamella of less band gap and the semiconductor lamella of big band gap, the periodic structure that interleaving stack forms.Superlattice have definition more widely in the present invention.It can be made up of with semiconductor layer staggered metal (or silicide) layer.In Figure 18, base region 1810 can hinder 1805 of the 1804 and second Metal Substrate polar regions, district by the first Metal Substrate polar region 1803, semiconductor base stage and form.WS is the thickness that the semiconductor base stage can hinder district 1804, and WB is the thickness (supposing that there is identical thickness these two Metal Substrate polar regions) of Metal Substrate polar region 1803 and 1805.Metal Substrate polar region 1803 and 1805 wherein has at least one to be connected to base terminal 37.Except the base region, superlattice also can be used on emitter region and collector region.
Figure 19 a shows the n type SBQWRTT of superlattice base structure, its subcritical swing (V
B0 and 0.2V between) and the electrons tunnel electric current J of conducting state
Tn(at V
B=0.2V) and W
SRelation.Emitter-base bandgap grading can hinder district 1802, semiconductor base stage and can hinder district 1804 and collect the utmost point and can hinder that to distinguish 1806 be to be made up of plain (100) silicon.Emitter region 1801, Metal Substrate polar region 1803 and 1805 and collector region 1807 (100) be to constitute by nickel disilicide.Schottky between (100) nickel disilicide and (100) silicon can hinder height q Φ
BnBe 0.4eV.W
EB=W
CB=19 atomic layers.W
B=2 atomic layers.V
E＝0V。V
C＝0.2V。Work as W
SDuring greater than 10 atomic layers, J
TnAnd subcritical swing almost with W
SIrrelevant.Work as W
SDuring less than 10 atomic layers, along with W
SReduce, subcritical swing is risen rapidly, and J
TnThen descend rapidly.Work as W
SDrop to zero, W
BBecome twice, and E
1Diminish.Because the appearance of negative difference resistance, make J
TnAnd subcritical swing all is affected and variation.
Figure 19 b shows the n type SBQWRTT of superlattice base structure, and its electronics and electricity pierce tunnel electric current J
TnAnd J
TpWith V
BRelation.Work as W
SHour, negative difference resistance occurs in less V
BBefore negative difference resistance takes place, if V
BEnough little, then subcritical swing almost with W
SIrrelevant.At V
BDuring=0V, J
TnCompare J
TpExceed 3 one magnitude.
Although illustrated and described embodiments of the invention; For those of ordinary skill in the art; Be appreciated that under the situation that does not break away from principle of the present invention and spirit and can carry out multiple variation, modification, replacement and modification that scope of the present invention is accompanying claims and be equal to and limit to these embodiment.
Claims (32)
1. semiconductor transistor assembly comprises:
A) one or more conduction base region is connected to the first electronics end;
B) first semiconductor energy resistance district, the conduction base region is somebody's turn to do in contact, and wherein first Schottky can hinder and engage the interface that is formed at this first semiconductor energy resistance district and this conduction base region;
C) second semiconductor energy resistance district, the conduction base region is somebody's turn to do in contact, and wherein second Schottky can hinder and engage the interface that is formed at this second semiconductor energy resistance district and this conduction base region;
D) conduction emitter region contacts this first semiconductor energy resistance district, and wherein the 3rd Schottky can hinder and engage the interface that is formed at this conduction emitter region and this first semiconductor energy resistance district, and wherein this conduction emitter region is connected to the second electronics end; And
E) conduction collector region contacts this second semiconductor energy resistance district, and wherein the 4th Schottky can hinder and engage the interface that is formed at this conduction collector region and this second semiconductor energy resistance district, and wherein this conduction collector region is connected to the 3rd electronics end;
Wherein, At least the size in this first semiconductor energy resistance district or this second semiconductor energy resistance district less than 100
and this conduction base region between this first semiconductor energy resistance district and this second semiconductor energy resistance district, form one or more quantum wells.
2. semiconductor transistor assembly as claimed in claim 1; Wherein this first semiconductor energy resistance district comprises the ground floor between this conduction base region and this conduction emitter region, wherein the thickness of this ground floor less than 100
3. semiconductor transistor assembly as claimed in claim 2, wherein this ground floor comprises silicon, wherein this ground floor is parallel to (100) or (110) crystal face.
4. like the described semiconductor transistor assembly of Shen claim 1; Wherein this second semiconductor energy resistance district comprises the second layer between this conduction base region and this conduction collector region, wherein the thickness of this second layer less than 100
5. semiconductor transistor assembly as claimed in claim 1, wherein a kind of material is arranged is silicon, germanium, carbon or III-V compound semiconductor this first semiconductor energy resistance district or this second semiconductor energy resistance district.
6. semiconductor transistor assembly as claimed in claim 1; Wherein there is layer structure in this first semiconductor energy resistance district or this second semiconductor energy resistance district at least, and its thickness is less than
7. semiconductor transistor assembly as claimed in claim 1 when suitable voltage is added in this conduction base region, can produces and wear the tunnel electric current, through this first semiconductor energy resistance district and this second semiconductor energy resistance district.
8. semiconductor transistor assembly as claimed in claim 7; Working function when this conduction base region; Near the conduction band edge in this first semiconductor energy resistance district or this second semiconductor energy resistance district, and during away from its valence band edge, this main carrier of wearing the tunnel electric current is an electronics.
9. semiconductor transistor assembly as claimed in claim 8, the voltage that wherein imposes on this conduction base region is positive with respect to emitter voltage.
10. semiconductor transistor assembly as claimed in claim 8, wherein this conduction base region comprises the nickel disilicide of a layer thickness less than
.
11. semiconductor transistor assembly as claimed in claim 10, wherein this nickel disilicide layer is parallel to (100) crystal face.
12. semiconductor transistor assembly as claimed in claim 7; Working function when this conduction base region; Near the valence band edge in this first semiconductor energy resistance district or this second semiconductor energy resistance district, and during away from its conduction band edge, this main carrier of wearing the tunnel electric current is electric hole.
13. semiconductor transistor assembly as claimed in claim 12, the voltage that wherein imposes on this conduction base region is born with respect to emitter voltage.
14. semiconductor transistor assembly as claimed in claim 12, wherein this conduction base region comprise a layer thickness less than 20
cobalt disilicide.
15. semiconductor transistor assembly as claimed in claim 14, wherein this cobalt disilicide layer is parallel to (100) crystal face.
16. semiconductor transistor assembly as claimed in claim 1, wherein this first semiconductor energy resistance district or this second semiconductor energy resistance district are not doped at least.
17. semiconductor transistor assembly as claimed in claim 1, wherein this conduction emitter region, conduction base region or conduction collector region comprise one or more metal, silicide, germanide and metallic compound.
18. semiconductor transistor assembly as claimed in claim 1, wherein this first semiconductor energy resistance district or this second semiconductor energy resistance district comprise the different connected structure of silicon/germanium at least.
19. semiconductor transistor assembly as claimed in claim 18, wherein the combination thickness of the different connected structure of this silicon/germanium less than 60
20. semiconductor transistor assembly as claimed in claim 1, wherein this conduction base region comprises:
A) the first conduction base region contacts this first semiconductor energy resistance district;
B) a semiconductor base stage can hinder the district, contacts this first conduction base region; And
C) the second conduction base region contacts this second semiconductor energy resistance district.
21. a semiconductor transistor comprises:
A) one or more conduction base region;
B) first semiconductor energy resistance district, the conduction base region is somebody's turn to do in contact, and wherein first Schottky can hinder and engage the interface that is formed at this first semiconductor energy resistance district and this conduction base region;
C) second semiconductor energy resistance district, the conduction base region is somebody's turn to do in contact, and wherein second Schottky can hinder and engage the interface that is formed at this second semiconductor energy resistance district and this conduction base region;
D) conduction emitter region contacts this first semiconductor energy resistance district, and wherein the 3rd Schottky can hinder and engage the interface that is formed at this conduction emitter region and this first semiconductor energy resistance district; And
E) conduction collector region contacts this second semiconductor energy resistance district, and wherein the 4th Schottky can hinder and engage the interface that is formed at this conduction collector region and this second semiconductor energy resistance district;
When suitable voltage is added in this conduction base region; Can produce and wear the tunnel electric current; Through this first semiconductor energy resistance district and this second semiconductor energy resistance district, and this conduction base region between this first semiconductor energy resistance district and this second semiconductor energy resistance district, one or more quantum wells formed.
22. semiconductor transistor as claimed in claim 21, wherein at least the size in this first semiconductor energy resistance district or this second semiconductor energy resistance district less than 100
23. a semiconductor transistor comprises:
A) one or more conduction base region;
B) first semiconductor energy resistance district, the conduction base region is somebody's turn to do in contact, and wherein first Schottky can hinder and engage the interface that is formed at this first semiconductor energy resistance district and this conduction base region;
C) second semiconductor energy resistance district, the conduction base region is somebody's turn to do in contact, and wherein second Schottky can hinder and engage the interface that is formed at this second semiconductor energy resistance district and this conduction base region;
D) conduction emitter region contacts this first semiconductor energy resistance district, and wherein the 3rd Schottky can hinder and engage the interface that is formed at this conduction emitter region and this first semiconductor energy resistance district; And
E) conduction collector region contacts this second semiconductor energy resistance district, and wherein the 4th Schottky can hinder and engage the interface that is formed at this conduction collector region and this second semiconductor energy resistance district;
Wherein this conduction emitter region, this conduction base region maybe this conduction collector region comprise one or more metal, silicide, germanide and metallic compound;
Wherein this first semiconductor energy resistance district comprises the ground floor between this conduction base region and this conduction emitter region;
Wherein this second semiconductor energy resistance district comprises the second layer between this conduction base region and this conduction collector region;
Wherein the thickness of this ground floor and this second layer less than 50
Wherein this ground floor or the second layer comprise silicon;
Wherein this ground floor is parallel to (100) or (110) crystal face;
Wherein this conduction base region between this first semiconductor energy resistance district and this second semiconductor energy resistance district forms a quantum well;
Wherein when suitable voltage is added in this conduction base region, can produces and wear the tunnel electric current, through this first semiconductor energy resistance district and this second semiconductor energy resistance district.
24. a three dimensional integrated circuits comprises:
A) plate base;
B) the first semiconductor transistor assembly, it comprises:
I) the first conductive bottom electrode layer, it is positioned on this substrate;
Ii) first semiconductor energy resistance layer, it contact this first conductive bottom electrode layer, and wherein first Schottky can hinder joint and is formed at this first semiconductor energy and hinders layer the interface with this first conductive bottom electrode layer;
The iii) first conduction base layer, it contacts this first semiconductor energy resistance layer, and wherein second Schottky can hinder to engage and be formed at the interface that this first conduction base layer and this first semiconductor energy hinder layer;
Iv) second semiconductor energy resistance layer, it contacts this first conduction base layer, wherein the 3rd Schottky can hinder engage be formed at this second semiconductor energy resistance layer with this first conduct electricity base layer the interface; And
The v) first conductive tip electrode layer, it contacts this second semiconductor energy resistance layer, and wherein the 4th Schottky can hinder to engage and be formed at the interface that this first conductive tip electrode layer and this second semiconductor energy hinder layer;
C) first insulating barrier; And
D) the second semiconductor transistor assembly, it comprises:
I) the second conductive bottom electrode layer, it is positioned on this first insulating barrier;
Ii) the 3rd semiconductor energy resistance layer, it contact this second conductive bottom electrode layer, and wherein the 5th Schottky can hinder joint and is formed at the 3rd semiconductor energy and hinders layer the interface with this second conductive bottom electrode layer;
The iii) second conduction base layer, its contact the 3rd semiconductor energy resistance layer, wherein, the 6th Schottky can hinder to engage and be formed at the interface that this second conduction base layer and the 3rd semiconductor energy hinder layer;
Iv) the 4th semiconductor energy resistance layer, it contacts this second conduction base layer, wherein the 7th Schottky can hinder engage be formed at the 4th semiconductor energy resistance layer with this second conduct electricity base layer the interface; And
The v) second conductive tip electrode layer, its contact the 4th semiconductor energy resistance layer, wherein the 8th Schottky can hinder to engage and be formed at the interface that this second conductive tip electrode layer and the 4th semiconductor energy hinder layer;
Wherein this first semiconductor energy resistance layer, this first conduction base layer and this second semiconductor energy resistance layer form first dual intensity resistance quantum well; Wherein the 3rd semiconductor energy resistance layer, the second conduction base layer and the 4th semiconductor energy resistance layer form second dual intensity resistance quantum well; Wherein be added in the voltage of this first conduction base layer, control is worn the tunnel electric current through this first dual intensity resistance quantum well.
25. three dimensional integrated circuits as claimed in claim 24, wherein this first semiconductor transistor is the p type, and this second semiconductor transistor is the n type.
26. three dimensional integrated circuits as claimed in claim 24, wherein this substrate comprises monocrystalline silicon, and its end face is parallel to (100) or (110) crystal face.
27. three dimensional integrated circuits as claimed in claim 26, comprising monocrystalline silicon between this first conductive tip electrode layer of this first insulating barrier and this first semiconductor transistor assembly.
28. three dimensional integrated circuits as claimed in claim 26, comprising monocrystalline silicon between this second conductive bottom electrode layer of this first insulating barrier and this second semiconductor transistor assembly.
29. three dimensional integrated circuits as claimed in claim 24, wherein this first insulating barrier comprises monocrystalline calcirm-fluoride.
30. three dimensional integrated circuits as claimed in claim 24, comprising second insulating barrier between this substrate and this first conductive bottom electrode layer.
31. three dimensional integrated circuits as claimed in claim 24 is comprising at least one at following all layers of a contact hole: this first conductive bottom electrode layer, this first conduction base layer, this first conductive tip electrode layer, this second conductive bottom electrode layer, this second conduction base layer and this second conductive tip electrode layer.
32. three dimensional integrated circuits as claimed in claim 24 is comprising at least one at following all layers of one or more tablelands: this first conductive bottom electrode layer, this first conduction base layer, this first conductive tip electrode layer, this second conductive bottom electrode layer, this second conduction base layer and this second conductive tip electrode layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/258,425 US7936040B2 (en) | 2008-10-26 | 2008-10-26 | Schottky barrier quantum well resonant tunneling transistor |
| US12/258,425 | 2008-10-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101728427A CN101728427A (en) | 2010-06-09 |
| CN101728427B true CN101728427B (en) | 2012-05-23 |
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| CN2009101375704A Expired - Fee Related CN101728427B (en) | 2008-10-26 | 2009-05-14 | Semiconductor transistor |
Country Status (5)
| Country | Link |
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| US (1) | US7936040B2 (en) |
| JP (1) | JP5368252B2 (en) |
| KR (1) | KR101021736B1 (en) |
| CN (1) | CN101728427B (en) |
| TW (1) | TWI452693B (en) |
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| RU2749575C1 (en) * | 2020-09-07 | 2021-06-15 | Федеральное государственное бюджетное учреждение науки Институт радиотехники и электроники им. В.А. Котельникова Российской академии наук | Metal-dielectric-metal-dielectric-metal photodetector |
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| CN101853882B (en) * | 2009-04-01 | 2016-03-23 | 台湾积体电路制造股份有限公司 | There is the high-mobility multiple-gate transistor of the switch current ratio of improvement |
| US8455860B2 (en) * | 2009-04-30 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing source/drain resistance of III-V based transistors |
| US9768305B2 (en) * | 2009-05-29 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gradient ternary or quaternary multiple-gate transistor |
| US8617976B2 (en) | 2009-06-01 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain re-growth for manufacturing III-V based transistors |
| US8124463B2 (en) | 2009-09-21 | 2012-02-28 | International Business Machines Corporation | Local bottom gates for graphene and carbon nanotube devices |
| US8455929B2 (en) | 2010-06-30 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of III-V based devices on semiconductor substrates |
| US8901536B2 (en) * | 2010-09-21 | 2014-12-02 | The United States Of America, As Represented By The Secretary Of The Navy | Transistor having graphene base |
| US8546246B2 (en) | 2011-01-13 | 2013-10-01 | International Business Machines Corporation | Radiation hardened transistors based on graphene and carbon nanotubes |
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| US9059044B2 (en) | 2012-11-15 | 2015-06-16 | International Business Machines Corporation | On-chip diode with fully depleted semiconductor devices |
| US9059265B2 (en) * | 2012-12-18 | 2015-06-16 | The United States Of America, As Represented By The Secretary Of The Navy | Graphene resonant tunneling transistor |
| CN104051528B (en) * | 2013-03-13 | 2017-04-12 | 台湾积体电路制造股份有限公司 | Intra-band tunnel FET |
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2008
- 2008-10-26 US US12/258,425 patent/US7936040B2/en not_active Expired - Fee Related
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2009
- 2009-02-24 TW TW098105853A patent/TWI452693B/en not_active IP Right Cessation
- 2009-05-14 CN CN2009101375704A patent/CN101728427B/en not_active Expired - Fee Related
- 2009-09-29 KR KR1020090092424A patent/KR101021736B1/en not_active IP Right Cessation
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| RU2749575C1 (en) * | 2020-09-07 | 2021-06-15 | Федеральное государственное бюджетное учреждение науки Институт радиотехники и электроники им. В.А. Котельникова Российской академии наук | Metal-dielectric-metal-dielectric-metal photodetector |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101021736B1 (en) | 2011-03-15 |
| US7936040B2 (en) | 2011-05-03 |
| CN101728427A (en) | 2010-06-09 |
| JP2010135761A (en) | 2010-06-17 |
| US20100102298A1 (en) | 2010-04-29 |
| TW201017879A (en) | 2010-05-01 |
| JP5368252B2 (en) | 2013-12-18 |
| KR20100046103A (en) | 2010-05-06 |
| TWI452693B (en) | 2014-09-11 |
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