CN101699625A - High trigger current SCR and ESD protective device - Google Patents
High trigger current SCR and ESD protective device Download PDFInfo
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- CN101699625A CN101699625A CN 200910233694 CN200910233694A CN101699625A CN 101699625 A CN101699625 A CN 101699625A CN 200910233694 CN200910233694 CN 200910233694 CN 200910233694 A CN200910233694 A CN 200910233694A CN 101699625 A CN101699625 A CN 101699625A
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- 230000001681 protective effect Effects 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 119
- 239000002184 metal Substances 0.000 claims abstract description 106
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000002019 doping agent Substances 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- -1 boron ion Chemical class 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
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- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a high trigger current SCR and ESD protective device, comprising a P-type doped semiconductor substrate, an N-type doped well and a P-type doped well are respectively arranged on the P-type doped semiconductor substrate, an N-type doped semiconductor area and a P-type doped semiconductor area are arranged in the N-type doped well, the N-type doped semiconductor area and the P-type doped semiconductor area are arranged in the P-type doped well, an anode metal layer and a metal layer are respectively connected above the N-type doped semiconductor area and the P-type doped semiconductor area on the surface of the N-type doped well, a metal layer and a cathode metal layer are respectively connected above the N-type doped semiconductor area and the P-type doped semiconductor area on the surface of the P-type doped well, and the anode metal layer and the metal layer are connected by a diode which is formed by the P-type doped semiconductor area and the N-type doped semiconductor area, and the metal layer and the cathode metal layer are directly connected by metal. The protective device can effectively improve the trigger current and is suitable for ESD protection in a high-voltage integrated circuit.
Description
Technical field
The invention belongs to the high voltage integrated circuit technical field, relate to a kind of electrostatic discharge protection component, in particular, be static discharge (Electro-Static Discharge, ESD) the transverse semiconductor silicon controlled rectifier controller in the protection circuit that is applicable under the hyperbaric environment about a kind of.
Background technology
Along with multimedia application role in everyone daily life is growing, the relation between computer and the consumer electronics is also close day by day, the growth of portable and functional aspect is had the demand of continuation.This just requires element that higher integrated level is arranged---and total trend but is to cause sensitivity and expensive chip, and the risk of being damaged owing to the ESD surge that has external interface is also increasing.When mobile phone, digital camera, when products such as MP3 player and PDA provided more function, their I/O port also increased thereupon, caused Electrostatic Discharge to enter system and interference or damage integrated circuit (IC).In addition, because the increase of characteristic and multi-functional integrated, the IC design is responsive more to ESD, and the designer must tackle this challenge, makes IC that the most effective esd protection is provided as far as possible, also will reduce to account for board space and cost for extra protection component simultaneously.
When with traditional semiconductor controllable silicon (Semiconductor controlled rectifier, in the time of SCR) as esd protection, the V of generation
EsdVery low, equal its V
HoldSo can predict, traditional SCR can a large amount of electric current of conducting, makes that unnecessary electric charge is released fast, prevents that protected device from being burnt out, so be suitable as very much the esd protection device.
But in the high voltage integrated circuit application, current density is big, and the heating of the PN junction of device is very serious, make high voltage integrated circuit esd protection very difficulty do.And exist problems such as inhomogeneous triggering and trigger current be lower as the esd protection device in the high voltage integrated circuit with SCR.Especially trigger current is low; make the false triggering under the effect of extraneous noise jamming of SCR device easily; breech lock (latch-up) phenomenon takes place; press welding block is clamped at a lower voltage; disturbed normal signal transmission; this just makes that esd protection has lost meaning, so we must take measures to improve the trigger current of SCR device.
Abroad the someone proposes to utilize a SCR and NMOS to constitute the trigger current that an esd protection device can improve SCR greatly together; but owing to introduced a NMOS pipe; obviously can increase the complexity of technology, increase area of chip, be unfavorable for that chip is integrated.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, provide a kind of under the prerequisite that does not increase technology difficulty and cost, can obtain the SCR device of higher relatively trigger current, this device has been avoided the false triggering phenomenon under noise jamming effectively.
The present invention adopts following technical scheme:
A kind of SCR ESD protective device of high trigger current, comprise: P type dope semiconductor substrates, on P type dope semiconductor substrates, be respectively arranged with adjacent N type dopant well and P type dopant well, in N type dopant well, be provided with N type doped semiconductor area and P type doped semiconductor area, in P type dopant well, be provided with N type doped semiconductor area and P type doped semiconductor area, be provided with field oxide in the N type doped semiconductor area on the surface of the N type doped semiconductor area on the surface of N type dopant well and zone beyond the P type doped semiconductor area and P type dopant well and the zone beyond the P type doped semiconductor area, at field oxide, the N type doped semiconductor area on the surface of N type dopant well and P type doped semiconductor area, the surface of the N type doped semiconductor area on the surface of P type dopant well and P type doped semiconductor area is provided with oxide layer, in the N type doped semiconductor area on the surface of N type dopant well be connected with anode metal layer and metal level respectively above the P type doped semiconductor area, and in the N type doped semiconductor area on the surface of P type dopant well be connected with metal level and cathodic metal layer above the P type doped semiconductor area respectively, it is characterized in that between described anode metal layer and metal level and described metal level and cathodic metal layer between in connect one of at least by diode.
Compared with prior art, the present invention has following advantage:
(1) the transverse semiconductor silicon controlled rectifier controller of the body silicon among the present invention, between anode metal layer and metal level, be connected by constituting diode with N type doped semiconductor area by P type doped semiconductor area, because the existence of the diode of this connection, make the voltage of the N type dopant well under the P type doped semiconductor area just can impel the diode current flow of P type doped semiconductor area and N type dopant well formation than the low 1.4V of high potential (as long as traditional structure is low 0.7V) that anode metal layer connect, thereby the injection in hole takes place, and then trigger SCR.Because the doping content of N type dopant well is constant, so its resistance is constant, the raising of potential difference (1.4V) can only be satisfied by the raising that requires trigger current.So the present invention significantly improves the trigger current of SCR, can effectively prevent the device false triggering that the outside noise signal causes.
(2) the transverse semiconductor silicon controlled rectifier controller of the body silicon among the present invention, all can being connected in series between anode metal layer and the metal level and between metal level and the cathodic metal layer by a plurality of diodes, further improve potential difference, thereby further improve the trigger current of SCR device.
(3) the transverse semiconductor silicon controlled rectifier controller of the body silicon among the present invention does not change the voltage of keeping of SCR device, i.e. V
HoldKeep consistent with traditional SCR.
(4) making of the transverse semiconductor silicon controlled rectifier controller of the body silicon among the present invention can with the process compatible of traditional SCR element manufacturing, between anode metal layer and the metal level and the diode of introducing between metal level and the cathodic metal layer can realize that and doping process can utilize the technology of making nsd or psd to realize by polysilicon doping.
Description of drawings
Fig. 1 is traditional transverse semiconductor silicon controlled rectifier controller (SCR device) structural representation.
Fig. 2 is transverse semiconductor silicon controlled rectifier controller (SCR device) structural representation of the body silicon that adds that between anode metal layer and metal level the diode that is made of P type doped semiconductor area and N type doped semiconductor area is connected.
Fig. 3 is transverse semiconductor silicon controlled rectifier controller (SCR device) structural representation of the body silicon that adds that between metal level and cathodic metal layer the diode that is made of P type doped semiconductor area and N type doped semiconductor area is connected.
Fig. 4 adds by P type doped semiconductor area to be connected with the diode that N type doped semiconductor area constitutes between anode metal layer and metal level, and adds transverse semiconductor silicon controlled rectifier controller (SCR device) structural representation of the body silicon that the diode that is made of P type doped semiconductor area and N type doped semiconductor area is connected between metal level and cathodic metal layer.
Fig. 5 is transverse semiconductor silicon controlled rectifier controller (SCR device) structural representation that adds the body silicon that is connected by P type doped semiconductor area and N type doped semiconductor area and the series diode that is made of P type doped semiconductor area and N type doped semiconductor area between anode metal layer and metal level.
Embodiment
With reference to Fig. 2, a kind of SCR ESD protective device of high trigger current, comprise: P type dope semiconductor substrates 1, on P type dope semiconductor substrates 1, be respectively arranged with adjacent N type dopant well 2 and P type dopant well 3, in N type dopant well 2, be provided with N type doped semiconductor area 4 and P type doped semiconductor area 5, in P type dopant well 3, be provided with N type doped semiconductor area 6 and P type doped semiconductor area 7, be provided with field oxide 8 in the N type doped semiconductor area 6 on the surface of the N type doped semiconductor area 4 on the surface of N type dopant well 2 and zone beyond the P type doped semiconductor area 5 and P type dopant well 3 and the zone beyond the P type doped semiconductor area 7, at field oxide 8, N type doped semiconductor area 4, P type doped semiconductor area 5, the surface of N type doped semiconductor area 6 and P type doped semiconductor area 7 is provided with oxide layer 9, be connected with anode metal layer 10 and metal level 11 respectively in N type doped semiconductor area 4 with above the P type doped semiconductor area 5, and be connected with metal level 12 and cathodic metal layer 13 respectively in N type doped semiconductor area 6 with above the P type doped semiconductor area 7, one of at least connect by diode between anode metal layer 10 and the metal level 11 and between described metal level 12 and the cathodic metal layer 13, in the present embodiment
(1) between anode metal layer 10 and the metal level 11 by being connected with the diode that N type doped semiconductor area 15 constitutes by P type doped semiconductor area 14, and directly connect between described metal level 12 and the cathodic metal layer 13 with metal
(2) also can be connected with the diode that N type doped semiconductor area 17 constitutes between metal level 12 and the cathodic metal layer 13, and directly connect between anode metal layer 10 and the metal level 11 with metal by P type doped semiconductor area 16.
(3) between anode metal layer 10 and metal level 11 by being connected with the diode that N type doped semiconductor area 15 constitutes by P type doped semiconductor area 14, and also can be connected between metal level 12 and the cathodic metal layer 13 by the diode that P type doped semiconductor area 16 and N type doped semiconductor area 17 constitute.
(4) between anode metal layer 10 and the metal level 11 and the diode between metal level 12 and the cathodic metal layer 13 connect and all can connect by two or more diodes.
(5) described P type doped semiconductor area 14 and 16 and N type doped semiconductor area 15 and 17 all on polysilicon, carry out ion implantation doping and constitute.
The present invention adopts following method to prepare:
1, the making of Chang Gui SCR device, comprise the injection of P type doped well region and N type doped well region, the P type doped semiconductor area on P type doped well region and N type doped well region surface and the formation of N type doped semiconductor area, the growth of field oxygen and passive oxidation layer, deposit of metal or the like forms conventional scr structure shown in Figure 1 at last.
2, deposit photoresist, the metal between etching anode metal layer 10 and the metal level 11, the deposit polysilicon is removed photoresist then.
3, deposit photoresist injects the boron ion, forms P type semiconductor doped region 14, removes photoresist.
4, deposit photoresist injects phosphonium ion, forms N type semiconductor doped region 15, removes photoresist.
If 5 introduce a plurality of diodes, manufacture method is the same, just will note the position of photoresist deposit.
Claims (9)
1. the SCR ESD protective device of a high trigger current, comprise: P type dope semiconductor substrates (1), on described P type dope semiconductor substrates (1), be respectively arranged with adjacent N type dopant well (2) and P type dopant well (3), in described N type dopant well (2), be provided with N type doped semiconductor area (4) and P type doped semiconductor area (5), in described P type dopant well (3), be provided with N type doped semiconductor area (6) and P type doped semiconductor area (7), the described N type doped semiconductor area (4) on the surface of described N type dopant well (2) and P type doped semiconductor area (5) in addition the zone and the N type doped semiconductor area (6) and P type doped semiconductor area (7) zone in addition on the surface of P type dopant well (3) be provided with field oxide (8), in described field oxide (8), N type doped semiconductor area (4), P type doped semiconductor area (5), the surface of N type doped semiconductor area (6) and P type doped semiconductor area (7) is provided with oxide layer (9), be connected with anode metal layer (10) and metal level (11) respectively in described N type doped semiconductor area (4) with above the P type doped semiconductor area (5), and be connected with metal level (12) and cathodic metal layer (13) respectively in described N type doped semiconductor area (6) with above the P type doped semiconductor area (7), it is characterized in that, connect one of at least between described anode metal layer (10) and metal level (11) and between described metal level (12) and the cathodic metal layer (13) by diode.
2. the SCR ESD protective device of high trigger current according to claim 1, it is characterized in that, between described anode metal layer (10) and metal level (11), pass through to be connected with the diode that N type doped semiconductor area (15) constitutes, and directly connect between described metal level (12) and the cathodic metal layer (13) with metal by P type doped semiconductor area (14).
3. the SCR ESD protective device of high trigger current according to claim 1, it is characterized in that, be connected with the diode that N type doped semiconductor area (17) constitutes by P type doped semiconductor area (16) between described metal level (12) and the cathodic metal layer (13), and directly connect between described anode metal layer (10) and the metal level (11) with metal.
4. the SCR ESD protective device of high trigger current according to claim 1, it is characterized in that being connected with the diode that N type doped semiconductor area (15) constitutes by P type doped semiconductor area (14) between described anode metal layer (10) and the metal level (11), and be connected with the diode that N type doped semiconductor area (17) constitutes by P type doped semiconductor area (16) between described metal level (12) and the cathodic metal layer (13).
5. according to the SCR ESD protective device of claim 2,3,4 described high trigger currents, it is characterized in that described P type doped semiconductor area (14) and (16) and N type doped semiconductor area (15) and (17) are all carried out ion implantation doping and constituted on polysilicon.
6. the SCR ESD protective device of high trigger current according to claim 1, it is characterized in that, connect by two series diodes between described anode metal layer (10) and the metal level (11), and directly connect between metal level (12) and the cathodic metal layer (13) with metal.
7. the SCR ESD protective device of high trigger current according to claim 1 is characterized in that, the diode in series number also can be greater than two between described anode metal layer (10) and metal level (11).
8. the SCR ESD protective device of high trigger current according to claim 2, it is characterized in that, two or more diodes that pass through between metal level (12) and the cathodic metal layer (13) connect, and directly connect with metal between anode metal layer (10) and the metal level (11).
9. the transverse semiconductor silicon controlled rectifier controller of body silicon according to claim 3, it is characterized in that, between described anode metal layer (10) and the metal level (11) and the diode between described metal level (12) and the cathodic metal layer (13) connect and all can connect by two or more diodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910233694 CN101699625A (en) | 2009-10-28 | 2009-10-28 | High trigger current SCR and ESD protective device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910233694 CN101699625A (en) | 2009-10-28 | 2009-10-28 | High trigger current SCR and ESD protective device |
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| CN101699625A true CN101699625A (en) | 2010-04-28 |
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| CN 200910233694 Pending CN101699625A (en) | 2009-10-28 | 2009-10-28 | High trigger current SCR and ESD protective device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201404A (en) * | 2011-05-16 | 2011-09-28 | 中国科学院上海微系统与信息技术研究所 | SOI (silicon on insulator)-based ESD (electro-static discharge) protection device and production method thereof |
| CN108206432A (en) * | 2016-12-20 | 2018-06-26 | 北京小米移动软件有限公司 | Data-interface with ESD structures |
| CN108321154A (en) * | 2017-12-15 | 2018-07-24 | 西安科技大学 | TSV pinboards and preparation method thereof based on SCR pipes |
| CN109698194A (en) * | 2018-12-28 | 2019-04-30 | 电子科技大学 | A kind of Schottky clamper SCR device for ESD protection |
-
2009
- 2009-10-28 CN CN 200910233694 patent/CN101699625A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201404A (en) * | 2011-05-16 | 2011-09-28 | 中国科学院上海微系统与信息技术研究所 | SOI (silicon on insulator)-based ESD (electro-static discharge) protection device and production method thereof |
| CN108206432A (en) * | 2016-12-20 | 2018-06-26 | 北京小米移动软件有限公司 | Data-interface with ESD structures |
| CN108321154A (en) * | 2017-12-15 | 2018-07-24 | 西安科技大学 | TSV pinboards and preparation method thereof based on SCR pipes |
| CN109698194A (en) * | 2018-12-28 | 2019-04-30 | 电子科技大学 | A kind of Schottky clamper SCR device for ESD protection |
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Open date: 20100428 |