CN101689513B - 多功能芯片贴膜以及使用此贴膜的半导体封装方法 - Google Patents

多功能芯片贴膜以及使用此贴膜的半导体封装方法 Download PDF

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Publication number
CN101689513B
CN101689513B CN200780052483.8A CN200780052483A CN101689513B CN 101689513 B CN101689513 B CN 101689513B CN 200780052483 A CN200780052483 A CN 200780052483A CN 101689513 B CN101689513 B CN 101689513B
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Prior art keywords
die bonding
bonding film
chip
wafer
pad pasting
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Expired - Fee Related
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CN200780052483.8A
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CN101689513A (zh
Inventor
姜炳彦
徐凖模
成忠铉
金载勋
玄淳莹
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Hi Tech Corp
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LG Innotek Co Ltd
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Priority claimed from KR1020070013935A external-priority patent/KR20080074602A/ko
Priority claimed from KR1020070013933A external-priority patent/KR20080074601A/ko
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Publication of CN101689513A publication Critical patent/CN101689513A/zh
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Abstract

用于半导体封装过程的多功能芯片贴膜，包括：第一芯片贴膜，其贴合到具有精细电路图案和焊接凸点图案的晶圆的表面，并具有第一粘接强度；第二芯片贴膜，其贴合在第一层芯片贴膜上，并相对于晶圆、芯片、PCB和挠性板具有第二粘接强度；该多功能芯片贴膜在晶背研磨过程中用作晶背研磨胶带，并且在晶背研磨过程结束后并不被移除，而是被用来将芯片贴合到连接构件；并且，本发明在晶背研磨过程中将芯片贴膜用作晶背研磨胶带，同时在晶圆切割过程中将芯片贴膜用作晶圆保护手段，从而防止了锯切毛刺、划痕或裂纹。

Description

多功能芯片贴膜以及使用此贴膜的半导体封装方法
技术领域
本发明涉及多功能芯片贴膜(die attachment film)，具体涉及用于半导体封装过程的多功能芯片贴膜，其在晶背研磨过程中作为晶背研磨胶带，并且在晶背研磨过程后并不被移除，而是被用来将芯片贴合到连接构件；本发明还涉及使用此贴膜的半导体封装方法。
背景技术
通常，用于制造半导体芯片的过程包括：在具有预定厚度的半导体晶圆中形成精细电路图案；对晶圆的背表面进行晶背研磨；以及将晶圆切割成符合预定器件标准的单独芯片，并将这些单独芯片封装成半导体器件。
在半导体芯片制造过程的晶背研磨过程中，晶背研磨胶带被贴合到具有精细电路图案的晶圆的前表面，该贴有晶背研磨胶带的表面被研磨卡盘(grind chuck)吸住，晶圆的背表面被紧密放置于切割模具上，当研磨剂被喷射时，晶圆被进行晶背研磨，以使晶圆厚度为150至200μm。在晶背研磨过程中，巨大的压力或机械振动被施加到晶圆，晶背研磨胶带防止了在此过程中可能出现的晶圆损坏。
然而，常规上，在晶背研磨结束后需要将晶背研磨胶带从晶圆前表面移除。并且，在晶背研磨过程后，将切割膜贴合到晶圆的背表面，使用切割膜将晶圆置于切割模具上，然后移除晶背研磨胶带，此时，如果贴在与贴有晶背研磨胶带的晶圆表面相反的表面上的切割膜的粘接强度弱于晶背研磨胶带的粘接强度，晶圆就可能翘起。
与此同时，在切割过程中，具有精细电路图案的晶圆的表面可能会出现诸如锯切毛刺、划痕、裂纹等缺陷，然而在现有技术中，切割过程是在没有任何保护装置的情况下执行的。并且，在切割过程后，由于每个芯片都被拾取针拾起，并被安置在物件上供封装(例如引线框)上，薄芯片在拾取方向上可能会发生翘曲，并且如果过度翘曲，芯片就会产生意料之外的故障，从而降低所得半导体装置的可靠性。
发明内容
本发明被设计以解决现有技术的问题，因此本发明的一个目的是提供用于半导体封装过程的多功能芯片贴膜，其用作将芯片粘合到连接构件的芯片贴膜，同时也在芯片粘合过程之前的晶背研磨过程中用作晶背研磨胶带；本发明的另一个目的是提供使用该贴膜的半导体器件封装方法。
为了达到上述目的，用于半导体封装过程的多功能芯片贴膜包括：第一芯片贴膜，其贴合在具有精细电路图案和焊接凸点图案的晶圆的表面，并具有第一粘接强度；以及第二芯片贴膜，其贴合在第一芯片贴膜上，并具有第二粘接强度；该多功能芯片贴膜在半导体封装过程的晶背研磨过程中用作晶背研磨胶带，并且在晶背研磨过程结束后并不被移除，而是被用来将芯片贴合到连接构件。
优选地，第一芯片贴膜和第二芯片贴膜均由透明或半透明材料制成。
在本发明中，此多功能芯片贴膜具有第一芯片贴膜和第二芯片贴膜的层叠结构，并且第一芯片贴膜和第二芯片贴膜均由从以下组中任选的一种树脂材料制成：环氧基树脂、丙烯酸基树脂(acryl-based resin)、硅基树脂、橡胶基树脂、聚氨酯基树脂和弹性体基树脂。
优选地，基于硅晶圆表面贴合，第一粘接强度于25℃时为10至2000gf/cm；基于AUS308表面贴合，第二粘接强度于25℃时为10至2000gf/cm。
优选地，基于7天85℃/60％湿度的抗湿性测试(JL2)，第一芯片贴膜和第二芯片贴膜均具有0至2％wt的吸湿率。
优选地，第一芯片贴膜和第二芯片贴膜于50℃时均具有104至1010Pa的储能模量，更加优选地，第二芯片贴膜于50℃时具有106至109Pa的储能模量。
优选地，第一芯片贴膜和第二芯片贴膜至少之一含有导电填充物，并且该导电填充物的体积占树脂材料的体积的0.5％至70％。
此外，优选地，具有导电填充物的贴膜的厚度与没有导电填充物的贴膜的厚度比为10∶1至0.1∶1，更加优选地是4∶1至0.5∶1。
在本发明中，导电填充物由从以下组中任选的一种导电金属制成：金、银、铜和镍，或由涂覆有导电金属的核-壳结构的有机材料制成。
在本发明中，导电填充物的颗粒直径为0.05至50μm。
优选地，在第一芯片贴膜与第二芯片贴膜之间插入中间层，以形成多层结构，此中间层由从以下组中任选的一种或至少两种制成：聚酯、聚乙烯、聚乙烯对苯二酸盐、乙烯基树脂(vinyl)、聚丙烯、聚苯乙烯、聚碳酸酯、聚氯乙烯、聚甲基丙烯酸甲酯、聚缩醛、聚甲醛、聚丁烯对苯二甲酸酯(polybutyleneterephthalate)、丙烯腈-丁二烯-苯乙烯、和乙烯-乙烯醇共聚物。
为了达到上述目的，根据本发明一个方面的使用多功能芯片贴膜的半导体封装方法包括：(a)将芯片贴膜贴合到具有精细电路图案和焊接凸点图案的晶圆的表面，使该芯片贴膜的第一芯片贴膜表面面向该晶圆；(b)对该晶圆背表面进行晶背研磨，然后将切割膜贴合到其上；(c)将该具有芯片贴膜的晶圆锯切成至少一个芯片；以及(d)将该切割膜从该芯片移除，然后使用焊接凸点通过倒装互连(flip chip bonding)将该芯片电学连接到连接构件，使该芯片贴膜的第二芯片贴膜表面面向该连接构件。
为了达到上述目的，根据本发明另一个方面的使用多功能芯片贴膜的半导体封装方法包括：(a)将芯片贴膜贴合到具有精细电路图案和焊接凸点图案的晶圆的表面，使该芯片贴膜的第一芯片贴膜表面面向该晶圆；(b)对该晶圆背表面进行晶背研磨，然后将切割芯片贴膜贴合到其上；(c)将该具有芯片贴膜的晶圆锯切成至少一个芯片；以及(d)将该切割芯片贴膜的一个切割膜层从该芯片移除，将该芯片贴合到该连接构件，然后使用焊接凸点通过芯片倒装互连将另一个芯片电学连接到该芯片，使另一个芯片面向芯片贴膜表面。
在本发明中，连接构件是从以下组中任选的一种：PCB(印制电路板)、引线框和芯片。
附图说明
图1是图示了根据本发明的一个优选实施方案的芯片贴膜的横截面视图。
图2是图示了根据本发明的一个优选实施方案的半导体封装方法的流程图。
图3至6是图示了根据本发明的一个优选实施方案的半导体封装过程的横截面视图。
具体实施方式
此后，将参照附图对本发明的优选实施方案进行详细描述。
图1是图示了根据本发明的一个优选实施方案的芯片贴膜的横截面视图。
参照图1，芯片贴膜100包括：第一芯片贴膜10，其贴合到具有精细电路图案和焊接凸点图案50的晶圆的表面；第二芯片贴膜20，其贴合到第一芯片贴膜10；以及保护膜11，其贴合到芯片贴膜100的两个表面，以保护芯片贴膜100。
如图1所示，保护膜11保护芯片贴膜100的粘性表面免受杂质污染，并且可以由聚乙烯或聚对苯二甲酸乙二酯(Polyethyleneterephthalate)(PET)制成。然而，本发明并不局限于此。
芯片贴膜100具有第一芯片贴膜10和第二芯片贴膜20的层叠结构。
在此，第一芯片贴膜10以第一粘接强度贴合到具有精细电路图案和焊接凸点图案50的晶圆的表面，同时是需要高粘接强度的材料层，以使芯片从晶圆分离。第二芯片贴膜20以第二粘接强度贴合在第一芯片贴膜10上，同时是被研磨卡盘吸住的材料层，以在晶背研磨过程中固定晶圆。考虑到这点，基于硅晶圆表面贴合，第一粘接强度于25℃时为10至2000gf/cm；基于AUS308表面贴合，第二粘接强度于25℃时为10至2000gf/cm。
并且，在半导体封装过程的晶圆切割过程中，从晶圆30产生高热，并使用冷却液来冷却晶圆30。因此，芯片贴膜100应该具有抗湿性，因此需要较低的吸湿率。考虑到这点，基于7天85℃/60％湿度的抗湿性测试(JL2)，芯片贴膜100具有0至2％wt的吸湿率。
与此同时，在半导体封装的拾取过程中，当芯片被拾取针拾起时，薄芯片在拾取方向可能发生翘曲，此外，当芯片被贴合到引线框时，芯片可能会由于芯片安装头的抽吸工具而发生翘曲。为了防止这些问题，芯片贴膜100于50℃时具有104至1010Pa的储能模量，更加优选地，第二芯片贴膜100于50℃时具有106至109Pa的储能模量。
并且，芯片贴膜100在晶背研磨过程中能够用作晶背研磨胶带，并且在晶背研磨过程结束后并不被移除，而是在接下来的晶圆切割过程中保持原样。因此，芯片贴膜100由透明或半透明材料制成，以在晶圆切割过程中显示具有精细电路图案的晶圆的表面。
第一芯片贴膜10和第三芯片贴膜20均可以由环氧基树脂、丙烯酸基树脂、硅基树脂、橡胶基树脂、聚氨酯基树脂和弹性体基树脂制成。然而，本发明并不局限于此。
并且，在第一芯片贴膜10和第二芯片贴膜20之间可以插入中间层，以形成具有多层结构的芯片贴膜100，并且该中间层由聚酯、聚乙烯、聚乙烯对苯二酸盐、乙烯基树脂、聚丙烯、聚苯乙烯、聚碳酸酯、聚氯乙烯、聚甲基丙烯酸甲酯、聚缩醛、聚甲醛、聚丁烯对苯二甲酸酯、丙烯腈-丁二烯-苯乙烯、或乙烯-乙烯醇共聚物制成。然而，本发明并不局限于此。
并且，芯片贴膜100的第一芯片贴膜10和第二芯片贴膜20至少之一含有导电填充物21，以使当芯片被倒装互连到连接构件时，芯片和连接构件之间具有良好的电学结合性。例如，导电填充物21由任一选自金、银、铜或镍等导电金属的材料制成，或由涂覆有导电金属的核-壳结构的有机材料制成。然而，本发明并不局限于此。并且，导电填充物21的体积占第二层贴膜20的树脂材料的体积的0.5％至70％，同时导电填充物21的颗粒直径为0.05至50μm。
图2是图示了根据本发明的一个优选实施方案的半导体封装方法的流程图，图3至6是图示了根据本发明的一个优选实施方案的半导体封装过程的横截面视图。
参照图2至6，在根据本发明的一个优选实施方案的半导体封装方法中，如图3所示，保护膜11被从芯片贴膜100移除，然后芯片贴膜100被贴合到具有精细电路图案和焊接凸点图案50的晶圆30的表面，使芯片贴膜100的第一芯片贴膜10的表面面向晶圆30(S100)。
接下来，晶圆30被固定，使形成于被贴合到晶圆30的第一芯片贴膜10上的第二芯片贴膜20的表面被研磨卡盘吸住，然后执行晶背研磨(S200)。
然后，如图4所示，将切割膜40贴合到贴有芯片贴膜100的晶圆30的已研磨的背表面(S300)。
然后，如图5所示，固定晶圆30，使贴到晶圆30的背表面的切割膜40被贴合到切割台，晶圆30被切割锯70锯切成独立芯片110(S400)。
然后，芯片110被拾起，切割膜40被从芯片110移除。并且，如图6所示，芯片110被翻转，以使含有导电填充物21的第二层贴膜20面向连接构件60，然后执行倒装互连(flip chip bonding)，以使用焊接凸点50在芯片110和连接构件60之间建立电学连接(S 500)。此时，导电填充物21使芯片110和连接构件60之间的电学连接更紧密。
这里，连接构件60是从以下组中任选的一种：PCB(印制电路板)、引线框和芯片，并且连接构件可电学连接到芯片110。然而，本发明不局限于特定类型的连接构件60。
如上所述，根据本发明的芯片贴膜100执行将芯片110贴合到连接构件60的基本功能，同时在晶背研磨过程中用作晶背研磨胶带，并在倒装互连过程中用作芯片110和链接构件60之间的底部填充物。
与此同时，替代性地，在步骤S300中可以用切割芯片贴膜(未示出)来代替贴到晶圆30的背表面的切割膜40，在这种情况下，芯片110的切割芯片贴膜(未示出)的表面可以被贴合到连接构件60，并且另一个芯片(未示出)可以被贴合到芯片110的芯片贴膜100的表面，从而两个不同芯片可以彼此电学连接。
如此，应理解，详细描述和具体实例虽然指示了本发明的优选实施方案，但只是举例而已，因为基于此详细描述，本发明的精神和范围内的很多改变和修改对本领域技术人员都是显而易见的。
工业适用性
根据本发明的半导体封装方法可以利用芯片贴膜来将芯片贴合到连接构件，该芯片贴膜在晶背研磨过程中用作晶背研磨胶带，同时在晶圆切割过程中用作晶圆保护装置，从而防止了可能出现在晶圆表面的锯切毛刺、划痕、裂纹。并且，本发明可以免除晶背研磨过程后移除晶背研磨胶带的需要。此外，本发明可以由晶背研磨胶带材料和底部填充材料形成芯片贴膜，从而降低半导体封装成本。

Claims (15)

1.用于半导体封装过程的多功能芯片贴膜，包括：
第一芯片贴膜，其贴合到具有精细电路图案和焊接凸点图案的晶圆的表面，并具有第一粘接强度；以及
第二芯片贴膜，其贴合在第一芯片贴膜上，并具有第二粘接强度；
其中第一芯片贴膜和第二芯片贴膜至少之一含有导电填充物；并且
其中该多功能芯片贴膜在半导体封装过程的晶背研磨过程中用作晶背研磨胶带，并且该多功能芯片贴膜在晶背研磨过程结束后并不被移除，而是被用来将芯片贴合到连接构件。
2.权利要求1所述的多功能芯片贴膜，其中第一芯片贴膜和第二芯片贴膜均由透明或半透明材料制成。
3.权利要求2所述的多功能芯片贴膜，其中基于硅芯片表面贴合，第一粘接强度于25℃时为10至2000gf/cm；基于AUS308表面贴合，第二粘接强度于25℃时为10至2000gf/cm。
4.权利要求2或3所述的多功能芯片贴膜，其中第一芯片贴膜和第二芯片贴膜均具有0至2％wt的吸湿率。
5.权利要求4所述的多功能芯片贴膜，其中第一芯片贴膜和第二芯片贴膜于50℃时均具有104至1010Pa的储能模量。
6.权利要求5所述的多功能芯片贴膜，其中第二芯片贴膜于50℃时具有106至109Pa的储能模量。
7.权利要求6所述的多功能芯片贴膜，其中第一芯片贴膜和第二芯片贴膜均由从以下组中任选的一种树脂材料制成：环氧基树脂、丙烯酸基树脂、硅基树脂、橡胶基树脂、聚氨酯基树脂和弹性体基树脂。
8.权利要求7所述的多功能芯片贴膜，其中芯片贴膜含有的导电填充物的体积占树脂材料的体积的0.5％至70％。
9.权利要求8所述的多功能芯片贴膜，其中导电填充物仅包含在第二芯片贴膜中，该第二芯片贴膜与第一芯片贴膜的厚度比为10∶1至0.1∶1。
10.权利要求9所述的多功能芯片贴膜，其中导电填充物的颗粒直径为0.05至50μm。
11.权利要求10所述的多功能芯片贴膜，其中导电填充物由从以下组中任选的一种导电金属制成：金、银、铜和镍，或由涂覆有导电金属的核-壳结构的有机材料制成。
12.使用权利要求1至11之任一所述的多功能芯片贴膜的半导体封装方法，包括：
(a)将芯片贴膜贴合到具有精细电路图案和焊接凸点图案的晶圆的表面，使该芯片贴膜的第一芯片贴膜表面面向该晶圆；
(b)对该晶圆背表面进行晶背研磨，然后将切割膜贴合到其上；
(c)将该具有芯片贴膜的晶圆锯切成至少一个芯片；
(d)将该切割膜从该芯片移除，然后使用焊接凸点通过倒装互连将该芯片电学连接到连接构件，使该芯片贴膜的第二芯片贴膜表面面向该连接构件。
13.权利要求12所述的半导体封装方法，其中连接构件是从以下组中任选的一种：印刷电路板、引线框和芯片。
14.使用权利要求1至11之任一所述的多功能芯片贴膜的半导体封装方法，包括：
(a)将芯片贴膜贴合到具有精细电路图案和焊接凸点图案的晶圆的表面，以使该芯片贴膜的第一芯片贴膜表面面向该晶圆；
(b)对该晶圆背表面进行晶背研磨，然后将切割芯片贴膜贴合到其上；
(c)将该具有芯片贴膜的晶圆锯切成至少一个芯片；
(d)将该切割芯片贴膜的一个切割膜层从该芯片移除，将该芯片贴合到连接构件，然后使用焊接凸点通过倒装互连将该芯片电学连接到另一芯片，使该另一个芯片面向该芯片的第二芯片贴膜表面。
15.权利要求14所述的半导体封装方法，其中连接构件是从以下组中任选的一种：印制电路板、引线框和芯片。
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