CN101667563A - 半导体器件及其制造方法以及半导体密封用树脂 - Google Patents

半导体器件及其制造方法以及半导体密封用树脂 Download PDF

Info

Publication number
CN101667563A
CN101667563A CN200910166793A CN200910166793A CN101667563A CN 101667563 A CN101667563 A CN 101667563A CN 200910166793 A CN200910166793 A CN 200910166793A CN 200910166793 A CN200910166793 A CN 200910166793A CN 101667563 A CN101667563 A CN 101667563A
Authority
CN
China
Prior art keywords
resin
semiconductor device
semiconductor chip
lead portion
phenyl ring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200910166793A
Other languages
English (en)
Other versions
CN101667563B (zh
Inventor
岩崎富生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of CN101667563A publication Critical patent/CN101667563A/zh
Application granted granted Critical
Publication of CN101667563B publication Critical patent/CN101667563B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48639Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48663Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48664Palladium (Pd) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464Palladium (Pd) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明的目的在于提供一种提高引线和密封体树脂(模树脂)的粘合性、不引起剥离、可靠性高的半导体器件。所述半导体器件具有半导体芯片和与所述半导体芯片电连接的以金属作为主构成材料的多根引线、以及密封所述半导体芯片的树脂,其特征在于,所述多根引线具有从所述树脂中露出的外引线部分和埋入所述树脂中的内引线部分;所述树脂含有具有苯环的芳香族化合物和/或具有环己烷环的化合物;在所述内引线部分的表面材料与所述树脂接触的界面上的所述树脂中含有的苯环和/或环己烷环、和作为所述内引线部分的表面材料的主构成材料的金属原子重叠排列。

Description

半导体器件及其制造方法以及半导体密封用树脂
技术领域
本发明涉及一种半导体器件及该半导体器件的制造方法以及半导体密封用树脂。
背景技术
专利文献1中公开了一种密封半导体芯片的方法,在由Cu合金形成的引线基质上作为基底镀覆进行Cu触击电镀,之后部分镀覆用于引线接合或管芯焊接的银、金、钯等,用树脂等密封连接有引线的半导体芯片。
非专利文献1为涉及固体物理学的古典文献,其中登载了晶格常数(最邻近原子间距离等)。
非专利文献2中,关于在高分子材料的浸湿性、摩擦·磨蚀特性、粘接性、生物适应性等方面高分子固体表面的构造和物性的控制,记载了通过使用放射光的表面X射线衍射、扫描力显微镜的分析技术。
【专利文献1】特开平9-195068号公报
【非专利文献1】第5版Kittel固体物理学入门(上):p.28、丸善株式会社(1978年)。
【非专利文献2】Denso Technical Review:vol.12、No.2、pp.3~12(2007年)
发明内容
即使如专利文献1中所记载,实施在引线基质上镀覆铜、银、金、钯等后用树脂等密封半导体芯片的方法,由上述镀覆表面和树脂等形成的密封体的粘合性也不充分,有时引起剥离。由于使用需要比现有温度更高的回流焊温度(Reflow temperature)的无铅软焊条,所以上述剥离的问题变得更加严重。
本发明的目的在于提供一种提高引线和密封体树脂(模树脂(Mold Resin))的粘合性、不引起剥离的半导体器件。而且,本发明的目的在于提供一种可靠性高的半导体器件。
进而,本发明的目的在于提供一种成品率高的半导体制造方法。
另外,本发明的目的在于提供一种不引起剥离的半导体密封用树脂。
由本说明书的描述和附图可知本发明的上述和其他目的以及新特征。
本发明的半导体器件具有半导体芯片和与所述半导体芯片电接的以金属作为主构成材料的多根引线、以及密封所述半导体芯片的树脂,其特征在于,所述多根引线具有从所述树脂中露出的外引线部分和埋入所述树脂中的内引线部分,所述树脂含有具有苯环的芳香族化合物和/或具有环己烷环的化合物,在所述内引线部分的表面材料和所述树脂接触的界面上的所述树脂中含有的苯环和/或环己烷环、和作为所述内引线部分的表面材料的主构成材料的金属原子重叠排列。
根据本发明,可以提供一种提高引线和密封体树脂(模树脂)的粘合性、不引起剥离的半导体器件。另外,根据本发明,可以提供一种高可靠性的半导体器件。进而,根据本发明,可以提供一种成品率高的半导体制造方法。
附图说明
【图1】为表示本发明的实施例的半导体器件的外观斜视图。
【图2】为图1的A-B剖面图。
【图3】为表示形成于图2的半导体器件上的引线的一部分的放大剖面图。
【图4】为表示(111)取向的铜中含有的添加元素对剥离强度产生的影响的图。
【图5】为表示(111)取向的镍中含有的添加元素对剥离强度产生的影响的图。
【图6】为表示(111)取向的铂中含有的添加元素对剥离强度产生的影响的图。
【图7】为表示(111)取向的钯中含有的添加元素对剥离强度产生的影响的图。
【图8】为表示(001)取向的钌中含有的添加元素对剥离强度产生的影响的图。
【图9】为表示(111)取向的金中含有的添加元素对剥离强度产生的影响的图。
【图10】为表示(111)取向的银中含有的添加元素对剥离强度产生的影响的图。
【图11】为表示添加到树脂中的环己烷分子对树脂和金或银的剥离强度产生的影响的图。
【图12】为表示添加到树脂中的环己烷分子对树脂和铂、钯或钌的剥离强度产生的影响的图。
【图13】为表示添加到树脂中的环己烷分子对树脂和被氧化的铜或被氧化的镍的剥离强度产生的影响的图。
【图14】为表示铜的(111)取向率对剥离强度产生的影响的图。
【图15】为表示镍的(111)取向率对剥离强度产生的影响的图。
【图16】为表示金的(111)取向率对剥离强度产生的影响的图。
【图17】为表示银的(111)取向率对剥离强度产生的影响的图。
【图18】为表示被氧化的铜、被氧化的镍的(111)取向率对剥离强度产生的影响的图。
【图19】为表示利用广角X射线衍射测定铜的例子的图。
【图20】为表示含有80at%苯环的全芳香族液晶聚酯(例如,住友化学制的SUMIKASUPER)的分子结构的图。
【图21】为表示铜的(111)面的晶体结构的图。
【图22】为在铜的(111)面上,重叠全芳香族液晶聚酯的分子构造,从上方看到的图。
【图23】为表示银的(111)面的晶体结构的图。
【图24】在银的(111)面上重叠全芳香族液晶聚酯的分子结构,从上方观看而得到的图。
【图25】为表示本发明的实施例中的半导体器件的制造工序的图,为说明切割的斜视图。
【图26】为表示接着图25的半导体器件的制造工序的图,表示在引线框上搭载半导体芯片的工序的斜视图。
【图27】为表示接着图26的半导体器件的制造工序的图,表示用金属线将半导体芯片和引线电连接的工序的斜视图。
【图28】为表示接着图27的半导体器件的制造工序的图,表示用树脂密封半导体芯片的工序的斜视图。。
【图29】为表示本发明的实施例的半导体器件的外观斜视图。
符号说明
1:半导体器件,2:树脂,3:引线,3a:外引线,3b:内引线,4:引板,5:半导体芯片,5a:焊盘,6:金属线,10:表层,20:半导体晶片,20a:半导体芯片,21:刀片,22:引线框、23:金属线,24:树脂,25:半导体器件,26:引线
具体实施方式
本发明涉及一种半导体器件及其制造技术,特别涉及一种具有使用芳香族化合物树脂作为密封半导体芯片的密封体、从密封体中露出一部分引线的结构的半导体器件及适用于其制造的有效的技术。而且,本发明涉及一种用作密封体的树脂。
在具有半导体芯片和与所述半导体芯片电连接的以金属作为主构成材料的多根引线、以及密封所述半导体芯片的树脂的半导体器件中,发明人等为了获得提高引线和密封树脂(模树脂)的粘合性的方法,进行了深入研究,结果发现作为引线的表面材料和密封树脂的组合,使用高晶格整合性材料的组合是有效的。
具体而言,在具有半导体芯片和与所述半导体芯片电连接的由金属构成的多根引线、以及密封上述半导体芯片的树脂的半导体器件中,使用铜(Cu)或镍(Ni)的(111)取向膜作为上述内引线部分的表面材料,使所述表面材料中含有选自硼(B)0.5~12at%、锰(Mn)0.2~13at%、硅(Si)0.2~13at%的一种元素作为添加元素,使用具有苯环的芳香族化合物作为上述树脂是有效的。
在具有半导体芯片和与上述半导体芯片电连接的由金属构成的多根引线、以及密封上述半导体芯片的树脂的半导体器件中,使用铜或镍的(111)取向膜作为上述内引线部分的表面材料,使该表面材料中含有氧,使用具有苯环的芳香族化合物作为上述树脂,使该树脂中含有环己烷分子(也称作环己烷环)是有效的。
在具有半导体芯片和与上述半导体芯片电连接的由金属构成的多根引线、以及密封上述半导体芯片的树脂的半导体器件中,使用铂(Pt)或钯(Pd)的(111)取向膜或钌(Ru)的(001)取向膜作为上述内引线部分的表面材料,使所述表面材料中含有选自硼0.1~12at%、锰0.2~13at%、硅0.4~13at%的一种元素作为添加元素,使用具有苯环的芳香族化合物作为上述树脂是有效的。
在具有半导体芯片和与上述半导体芯片电连接的由金属构成的多根引线、以及密封所述半导体芯片的树脂的半导体器件中,使用铂或钯的(111)取向膜或钌的(001)取向膜作为上述内引线部分的表面材料,使用具有苯环的芳香族化合物作为上述树脂,使该树脂中含有环己烷分子是有效的。
在具有半导体芯片和与上述半导体芯片电连接的由金属构成的多根引线、以及密封上述半导体芯片的树脂的半导体器件中,使用金(Au)或银(Ag)的(111)取向膜作为上述内引线部分的表面材料,使用具有苯环的芳香族化合物作为上述树脂,使该树脂中含有环己烷分子是有效的。在这种情况下,优选使金或银中含有选自硼0.2~13at%、锰0.4~13at%、硅0.1~12at%中的一种元素作为添加元素更为有效。
以下实施方式中,为了方便起见,必要时分成多个部分或实施方式进行说明,但除特别注明的情况之外,各部分相互之间并不是没有关系,存在一方是另一方的一部分或全部的变形例、具体化或是补充说明等关系。
而且,以下实施方式中,在提及要素的数等(包括个数、数值、量、范围等)的情况下,除特别注明的情况和原理上显然限定为特定数的情况等之外,不限于该特定的数,可以在特定的数以上或以下。
进而,以下的实施方式中,其构成要素(也包括要素步骤等),除特别注明的情况和原理上显然为必须的情况等之外,当然未必是必须的。
同样地,以下的实施方式中,提及构成要素等的形状、位置关系等时,除特别注明的情况和原理上显然并非如此的情况等之外,包含实质上与其形状等近似或类似的要素等。对于所述数值和范围该情况同样适用。
另外,在用于说明实施方式的全部图中,原则上同一构件标记为同一符号,省略重复说明。
实施例
以下,根据图示的实施例详细说明本发明的实施方式。
首先,图1是表示作为本发明实施例的半导体器件的斜视图。另外,图2是图1的A-B剖面图。本实施例中的半导体器件的封装形态是QFP(Quad Flat Package)。
如图1所示,本实施例中的半导体器件1被长方体形状的树脂(密封体)2覆盖,从该树脂2的四个侧面引出引线3。引线3具有弯曲成L字型的结构。
另外,如图2所示,引线3是由从树脂2的侧面引出的外引线3a和形成在树脂2的内部的内引线3b构成的。在被左右的内引线3b夹持(被多根内引线3b包围)的中央部,形成引板4。在该引板4上配置有半导体芯片5。在半导体芯片5上,形成MISFET(Metal InsulatorSemiconductor Field Effect Transistor)等电路元件和布线,最上层形成焊盘5a。焊盘5a与金属线6连接,该金属线6连接在内引线3b上。
图3是图2中区域C的放大图。即,图3是将埋入树脂2中的内引线3b放大的剖面图。
如图3所示,在内引线3b的表面(也包括内表面),形成表层10。引线3以铜、铜合金、镍合金、铁合金作为主材料构成。表层10以铜、镍、铂、钌、钯、金、银等作为主材料,但本发明中,如下所述,为了提高与树脂2的粘合性,有时含有硼、锰、硅等作为添加元素。另外,为了提高粘合性,使树脂2中含有苯环或环己烷分子。表层10由例如镀覆或化学气相沉积法、喷溅法等形成,但为了加快制造速度或降低成本,优选镀覆法。另外,为了形成如下所述的晶体取向性高的表层,优选在温度条件为35℃以上的高温下进行镀覆。这是由于在35℃以上的高温下,原子容易活跃地移动,恢复更稳定配置的倾向提高。但是,温度过高时,会导致在湿法镀覆中产生腐蚀,所以期望在70℃以下的温度下进行镀覆。
以下说明选定表层10的材料和树脂2的优选组合及由其得到的提高粘合性的效果。
首先,在使用含有80at%苯环的全芳香族液晶聚酯(例如,住友化学制SUMIKASUPER)作为树脂2,使用铜、镍、铂、钯、银和金的各自的(111)取向晶体以及钌的(001)取向晶体作为表层10的情况下,通过实验评价树脂2和表层10的粘合性,结果示于图4~图10。图4、图5、图6、图7、图8、图9、图10分别是使用铜、镍、铂、钯、钌、金、银作为表层10时的结果。
上述图中,纵轴的剥离强度F/F0是用剥离能F除以横轴为零时的剥离能F0进行无量纲化加以表示。F0的值对应于铜、镍、铂、钯、钌、金、银分别为0.226、0.258、0.153、0.156、0.158、0.095、0.094。需要说明的是,上述数值的单位是焦耳每平方米。
此处,铂、钯、钌的F0的值小于铜、镍,进而银、金的F0的值小于上述元素的F0的值。发明人发现,与构成树脂2的苯环的晶格失配作为决定上述大小关系的支配因素是重要的。即,发现表层10的最邻近原子间距离越接近苯环的第二邻近碳原子间的距离0.243纳米,剥离能F0越大。此处,以纳米为单位,铜、镍、铂、钯、钌、金、银的最邻近原子间距离分别是0.256、0.249、0.277、0.275、0.265、0.288、0.289,例如,可以由非专利文献1的28页中记载的晶格常数(最邻近原子间距离等)容易地得到。发明人发现,上述数值与苯环的第二邻近碳原子间距离0.243纳米之差越小,F0越大。
因此,对于图4~图10所示含有添加元素时的F/F0的结果,也同样发现由于通过加入添加元素可以得到使表层10的最邻近原子间距离接近0.243纳米的作用,所以可以增大F/F0。但是,如果以过高的浓度加入添加元素,则由于表层10的晶体结构变得不稳定,反而会导致F/F0变小。因此,发现如图4~图10所示,添加元素的浓度在增大F/F0方面存在适当的浓度范围。有效果的浓度范围如下所述。
根据图4、图5,在使用铜或镍的(111)取向膜作为内引线部分的表面材料的情况下,使该表面材料中含有选自硼0.5~12at%、锰0.2~13at%、硅0.2~13at%中的一种元素作为添加元素是有效的。
根据图6、图7、图8,使用铂或钯的(111)取向膜或钌的(001)取向膜作为内引线部分的表面材料,使该表面材料中含有选自硼0.1~12at%、锰0.2~13at%、硅0.4~13at%中的一种元素作为添加元素是有效的。
根据图9、图10,使用金或银的(111)取向膜作为内引线部分的表面材料时,使该表面材料中含有选自硼0.2~13at%、锰0.4~13at%、硅0.1~12at%中的一种元素作为添加元素是有效的。
关于金和银,不含有添加元素时的剥离能F0小,原有的粘合性弱,而且如图9、图10所示,即使含有添加元素,由于剥离强度最多只能增大2倍左右,所以较优选在树脂2中加入环己烷分子。其理由如下所述,环己烷分子的第二邻近碳原子间距离约为0.27纳米,大于苯环的第二邻近碳原子间距离,与金、银的最邻近原子间距离0.288、0.289纳米的失配小。关于铂、钯、钌,最邻近原子间距离分别是0.277、0.275、0.271纳米,所以更优选加入第二邻近碳原子间距离约为0.27纳米的环己烷分子。铜、镍的情况如下,由于最邻近原子间距离为0.255、0.249纳米,所以不必加入环己烷分子。
但是,对于使表面轻微氧化至流过电流的程度的铜、镍的情况,由于掺入氧使得最邻近原子间距离接近约0.3纳米,所以与金或银的情况相同,更优选在树脂2中加入环己烷分子。
显示上述效果的图为图11~图13。在上述图中也同样,纵轴的剥离强度F/F0通过用剥离能F除以横轴为零时的剥离能F0进行无量纲化加以表示。
图11为表示使用金或银的(111)取向膜作为内引线部分的表面材料,使用含有80at%苯环的全芳香族液晶聚酯(例如住友化学制SUMIKASUPER)作为树脂2时,树脂2中含有环己烷的效果的图。
图12为表示使用铂或钯的(111)取向膜或钌的(001)取向膜作为内引线部分的表面材料,使用含有80at%苯环的全芳香族液晶聚酯(例如,住友化学制SUMIKASUPER)作为树脂2时,树脂2中含有环己烷的效果的图。
图13为表示使用铜或镍的(111)取向膜被氧化的材料作为内引线部分的表面材料,使用含有80at%苯环的全芳香族液晶聚酯(例如,住友化学制的SUMIKASUPER)作为树脂2时,树脂2中含有环己烷的效果的图。
在上述图中,加入环己烷分子可以通过加入例如东丽·道康宁株式会社制的称为2-(3,4环氧基环己基)乙基三甲氧基硅烷的偶联剂来实施。另外,也可以使用β-(3,4-环氧环己基)乙基三乙氧基硅烷等。
如图11~图13所示,环己烷分子的添加浓度在得到效果方面存在适当的浓度,即浓度过高也不好。这是由于浓度过高时,树脂2中存在的苯环的连接变得不稳定,反而导致剥离强度降低。根据图11~图13,合适的环己烷分子的添加浓度如下所述,内引线的表面为具有(111)取向的金、银时,添加浓度为2~40at%;内引线的表面为具有(111)取向的铂、钯、具有(001)取向的钌时,添加浓度为1~20at%;内引线的表面为具有(111)取向的铜、镍被氧化的材料时,添加浓度为1~20at%。
图11中仅表示一部分的例子,但加入环己烷分子时,也较优选使金、银中含有选自硼0.2~13at%、锰0.4~13at%、硅0.1~12at%中的一种元素作为添加元素。另外,图12中也仅表示一部分的例子,但加入环己烷分子时,也较优选使铂、钯、钌中含有选自硼0.1~12at%、锰0.2~13at%、硅0.4~13at%中的一种元素作为添加元素。进而,图13中也仅表示一部分的例子,但加入环己烷分子时,也较优选使被氧化的铜、被氧化的镍中含有选自硼0.5~12at%,锰0.2~13at%、硅0.2~13at%中的一种元素作为添加元素。
以上的说明中,给出了加入环己烷分子(环己烷环)的情况,但本发明的特征在于,环己烷环的第二邻近碳原子间距离与构成和树脂接触的内引线部分的表面材料的金属的最邻近原子间距离相近。因此,只要为具有环己烷环的化合物即可以适用。
以上的例子是铜、镍、铂、钯、金、银、被氧化的铜、被氧化的镍的(111)取向率为100%的例子,对于钌来说是(001)取向率为100%的例子。
但是,如图14~18所示,可知在取向率不是100%、而是51%以上的情况下,也可以得到与取向率为100%的情况基本相同的提高剥离强度的效果。此处,铜、镍、铂、钯、金、银、被氧化的铜、被氧化的镍的(111)取向率定义为在图19所示的广角X射线衍射光谱中,将(111)的峰强度除以(111)、(200)、(220)、(311)的峰强度的总合,将得到的商乘以100所得的值。单位是%。另外,钌的(001)取向率定义为将(002)的峰强度除以(100)、(002)、(101)的峰强度的总合,将得到的商乘以100所得的值。单位也是%。
如图14~18所示,所述取向率较优选为51%以上。另外,在图14~18中仅给出了一部分的例子,但取向率不是100%时,也较优选使铜、镍中含有选自硼0.5~12at%、锰0.2~13at%、硅0.2~13at%中的一种元素作为添加元素。另外,在图14~图18中没有示出,但取向率不是100%时,也较优选使铂、钯、钌中含有选自硼0.1~12at%、锰0.2~13at%、硅0.4~13at%中的一种元素作为添加元素,较优选在树脂2中以1~20at%的浓度加入环己烷分子。另外,在图14~图18中没有示出,但取向率不是100%时,也较优选使金、银中含有选自硼0.2~13at%、锰0.4~13at%、硅0.1~12at%中的一种元素作为添加元素,较优选在树脂2中以2~40at%的浓度加入环己烷分子。另外,在图14~图18中没有示出,但取向率不是100%时,也较优选使被氧化的铜、被氧化的镍中含有选自硼0.5~12at%、锰0.2~13at%、硅0.2~13at%中的一种元素作为添加元素,较优选在树脂2中以1~20at%的浓度加入环己烷分子。
至此,说明了使用含有80at%苯环的全芳香族液晶聚酯(例如,住友化学制SUMIKASUPER)作为树脂2的例子,和向其中加入环己烷分子的例子,但使用含有40at%以上苯环的树脂作为树脂2时也能得到相同的效果。苯环的浓度小于40at%时,由于以苯环的第二邻近碳原子间距离为特征的晶格匹配的影响减弱,所以本实施例中所示的效果减小。
然后,详细说明晶格失配的影响。图20为含有80at%苯环的全芳香族液晶聚酯(例如,住友化学制SUMIKASUPER)的分子结构,表示苯环的第二邻近碳原子间距离0.243纳米与作为其根号3倍(31/2倍、约1.73倍)的0.421纳米。图21中示出铜的(111)面,表示其最邻近铜原子间距离0.255纳米及作为其根号3倍的0.442纳米。最邻近铜原子间距离0.255纳米是与苯环的第二邻近碳原子间距离0.243纳米接近的值,晶格失配小。在图21中铜的(111)面上重叠图20的全芳香族液晶聚酯的分子结构,从上方看到的图是图22。图22中示出在苯环中心的正下方排列有铜原子,显示晶格匹配良好。即,在本实施例的树脂与铜原子接触的界面上,使树脂中含有的苯环与铜原子重叠地进行排列。因此,可以提高树脂与铜原子的粘合性。
另一方面,图23中示出了银的(111)面,示出其最邻近铜原子间距离0.289纳米与作为其根号3倍的0.501纳米。最邻近银原子间距离0.289纳米是与苯环的第二邻近碳原子间距离0.243纳米存在显著差异的值,晶格失配大。在图23的银的(111)面上重叠图20的全芳香族液晶聚酯的分子结构,从上方观看得到的图是图24。图24中示出在苯环中心的正下方没有排列银原子,表示晶格匹配不好。
另一方面,环己烷分子(环己烷环)的第二邻近碳原子间距离约为0.27纳米,大于苯环的该距离,与银的最邻近原子间距离0.289纳米的失配减小。发明人发现失配越小剥离强度越大,还发现添加元素或添加分子(环己烷分子)的效果也基于上述原理。即,在本实施例的树脂与银原子接触的界面上,使树脂中含有的环己烷环和银原子重叠地进行排列,由此可以提高树脂与银原子的粘合性。
通常,在树脂与金属原子接触的界面上,使树脂中含有的苯环和/或环己烷环与金属原子重叠地进行排列,由此可以提高树脂与金属原子的粘合性。
作为树脂2中的固化剂,没有特别限定,可以使用通常作为环氧树脂的固化剂使用的胺类化合物、酸酐类化合物、酰胺类化合物、酚类化合物等。具体而言,可以举出二氨基二苯基甲烷、二亚乙基三胺、三亚乙基四胺、二氨基二苯砜、异佛尔酮二胺、苄基二甲胺等叔胺、双氰胺、四亚乙基五胺、苄基二甲胺、酮亚胺化合物、由亚麻酸的二聚物与乙二胺合成得到的聚酰胺树脂、苯二甲酸酐、偏苯三酸酐、1,2,4,5-苯四酸酐、马来酸酐、四氢化苯二甲酸酐、甲基四氢化苯二甲酸酐、甲基降冰片烯二酸酐、六氢化苯二甲酸酐、甲基六氢化苯二甲酸酐、双酚类、酚类(苯酚、烷基取代苯酚、萘酚、烷基取代萘酚、二羟基苯、二羟基萘等)与各种醛的缩聚物、酚类与各种二烯化合物的聚合物、酚类与芳香族二羟甲基的缩聚物、或二甲氧基甲基联苯与萘酚类或酚类的缩合物等、联苯酚类及其改性体、咪唑、三氟化硼-胺配位化合物、胍衍生物等。固化剂的使用量相对于组合物中的1当量环氧基,优选为0.2~1.5当量,特别优选为0.3~1.2当量。另外,使用叔胺作为固化剂时,其使用量相对于组合物中的含有环氧基的化合物(本发明的环氧化合物与根据需要使用的其他环氧树脂),优选为0.3~20重量%,特别优选为0.5~10重量%。
本实施例的树脂2中可以根据需要含有固化促进剂。作为固化促进剂,例如可以举出2-甲基咪唑、2-乙基咪唑、2-乙基-4-甲基咪唑等咪唑类、2-(二甲基氨基甲基)苯酚、1,8-二氮杂-双环(5,4,0)十一碳烯-7等叔胺类、三苯膦等膦类、辛酸锡等金属化合物、季鏻盐等。相对于组合物中的含有环氧基化合物100重量份,根据需要可以使用0.01~15重量份的固化促进剂。
在外引线3a中形成以锡(锡、Sn)作为主构成材料的镀覆膜的情况一直就有,其原因如下所述,在本实施例中也优选存在镀覆膜。
图1所示的半导体器件1安装在安装基板上,此时形成于安装基板上的端子和形成于半导体器件1上的引线3进行电连接。在该端子和引线3的电连接中使用焊锡。因此,也可通过焊锡使以铜作为主构成材料的引线3直接与端子连接,但为了提高引线3对焊锡的浸湿性,在引线3的表面上形成表层10(镀覆膜)。
如上所述,通过在引线3的表面形成表层10,可以提高引线3和焊锡间的浸湿性,提高经焊锡的引线3和安装基板上的端子的连接可靠性。表层10中使用以与焊锡的浸湿性良好的锡作为主材料的膜。进而,通过在引线3的表面上形成表层10,可以防止引线3的腐蚀及氧化。
然后,说明本实施例中的半导体器件的制造方法。作为本实施例的封装形态,对QFP进行了说明,但在如下所示的制造方法中,对与QFP相同的表面安装型封装形态SOP(Small Outline Package)进行说明。无论封装形态为QFP或SOP,基本的制造工序都相同。
首先,在图25中准备半导体晶片20。将半导体晶片20划分为多个芯片区域,在多个芯片区域上分别形成LSI(Large Scale IntegrationCircuit)。LSI在所谓的晶片工序(前工序)中形成。
接下来,利用刀片21切断半导体晶体20。即,通过将半导体晶片20按芯片区域单位切断,得到半导体芯片。另一方面,准备用于搭载半导体芯片的引线框。该引线框22例如以铜作为主材料。
接下来,在形成于引线框上的引线的表面形成镀覆膜。在该镀覆工序中,将本实施例中的技术思想具体现实化。例如,如上所述,在引线的表面上首先通过电场镀覆法形成金膜。之后,在金膜上通过电解镀覆法形成以锡为主材料的镀覆膜。
然后,如图26所示,在镀覆处理后的形成引线图案的引线框22的引板上,搭载半导体芯片20a。将半导体芯片20a搭载在通过芯片焊接形成于引线框22上的引板上。
接下来,如图27所示,将形成于搭载在引板上的半导体芯片20a上的焊盘(未图示)、和形成于引线框22上的多根引线(内引线),通过金属线23连接。金属线23通过使用毛细管将焊盘和引线连接。
之后,如图28所示,利用树脂24密封包括在引线框22上搭载的半导体芯片20a和内引线的区域。利用树脂24进行密封是为了保护半导体芯片20a不受外力引起的冲击和水分的浸入。期望树脂本身由环氧树脂、聚酰亚胺树脂、酚醛树脂、不饱和聚酯树脂、有机硅树脂等热固性树脂、或液晶聚合物、聚苯醚、聚苯硫(PPS)树脂、聚砜、聚酰胺·酰亚胺·聚芳基砜树脂等热塑性树脂成型。
然后,由引线框22中将用树脂24密封的密封体进行单片化。由此,可以得到图29所示的半导体器件25。半导体器件25由利用树脂24形成的密封体和由该密封体引出的引线(外引线)26构成。在从密封体引出的引线26的表面上形成镀覆膜(未图示)。该图中引线26以间距p等间隔地排列。
以上,基于实施方式具体说明了本发明人的发明,但本发明不限定于上述实施方式,当然可以在不脱离其主旨的范围内进行各种改变。
产业上的可利用性
本发明可以广泛应用于制造半导体器件的制造业。

Claims (17)

1、一种半导体器件,具有半导体芯片和与所述半导体芯片电连接的以金属作为主构成材料的多根引线、以及密封所述半导体芯片的树脂,其特征在于,所述多根引线具有从所述树脂中露出的外引线部分和埋入所述树脂中的内引线部分,所述树脂含有具有苯环的芳香族化合物和/或具有环己烷环的化合物,所述内引线部分的表面材料与所述树脂接触的界面上的所述树脂中含有的苯环和/或环己烷环、和作为所述内引线部分的表面材料的主构成材料的金属原子重叠排列。
2、如权利要求1所述的半导体器件,其特征在于,所述内引线部分的表面材料含有选自硼、锰和硅中的一种元素作为添加元素。
3、如权利要求2所述的半导体器材,其特征在于,作为所述内引线部分的表面材料的主构成材料的金属是铜或镍。
4、如权利要求2所述的半导体器件,其特征在于,作为所述内引线部分的表面材料的主构成材料的金属是铂、钯或钌。
5、如权利要求2所述的半导体器件,其特征在于,作为所述内引线部分的表面材料的主构成材料的金属是金或银。
6、如权利要求3所述的半导体器件,其特征在于,所述添加元素的含有率在所述添加元素为硼时为0.5~12at%,所述添加元素为锰时为0.2~13at%,所述添加元素为硅时为0.2~13at%,所述树脂是含有苯环的芳香族化合物。
7、如权利要求6所述的半导体器件,其特征在于,所述内引线部分的表面晶体组织具有铜或镍的(111)晶体取向。
8、如权利要求7所述的半导体器件,其特征在于,所述内引线部分的表面材料含有氧,所述树脂是在含有40at%以上苯环的芳香族化合物中仅添加1~20at%的环己烷分子的树脂。
9、如权利要求4所述的半导体器件,其特征在于,所述添加元素的含有率在所述添加元素为硼时为0.1~12at%,所述添加元素为锰时为0.2~13at%、所述添加元素为硅时为0.4~13at%,所述树脂是含有苯环的芳香族化合物。
10、如权利要求9所述的半导体器件,其特征在于,所述内引线部分的表面晶体组织具有铂或钯的(111)晶体取向或钌的(001)晶体取向。
11、如权利要求10所述的半导体器件,其特征在于,所述树脂是在含有40at%以上苯环的芳香族化合物中仅添加1~20at%的环己烷分子的树脂。
12、如权利要求5所述的半导体器件,其特征在于,添加元素的含有率在所述添加元素为硼时为0.2~13at%,所述添加元素为锰时为0.4~13at%,所述添加元素为硅时为0.1~12at%。
13、如权利要求12所述的半导体器件,其特征在于,所述内引线部分的表面晶体组织具有金或银的(111)晶体取向。
14、如权利要求13所述的半导体器件,其特征在于,所述树脂是在含有40at%以上苯环的芳香族化合物中仅添加2~40at%的环己烷分子的树脂。
15、一种树脂,含有用于提高与界面上的金属原子的晶格整合性的苯环和环己烷环,其特征在于,在含有40at%以上所述苯环的芳香族化合物中加入1~40at%所述环己烷环。
16、一种半导体器件的制造方法,所述半导体器件具有半导体芯片和与所述半导体芯片电连接的以金属作为主构成材料的多根引线、以及密封所述半导体芯片的树脂,其特征在于,包括在所述多根引线的表面,在35℃以上的温度条件下,形成具有高晶体取向性的表层的镀覆膜的工序。
17、一种半导体器件的制造方法,所述半导体器件具有半导体芯片和与所述半导体芯片电连接的以金属作为主构成材料的多根引线、以及密封所述半导体芯片的树脂,其特征在于,包括下述工序:
准备以金属作为主构成材料的引线框的工序;
在形成于所述引线框上的多根引线的表面上,在35℃以上的温度条件下,形成具有高晶体取向性的表层的镀覆膜的工序;
在上述引线框的引板上设置所述半导体芯片的工序;
将所述半导体芯片和形成于所述引线框上的所述多根引线通过金属线连接的工序;
使用用于密封所述半导体芯片的树脂形成密封体的工序;
切断所述引线框,将所述密封体进行单片化的工序。
CN2009101667933A 2008-09-01 2009-08-20 半导体器件及其制造方法以及半导体密封用树脂 Expired - Fee Related CN101667563B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008222979A JP4585022B2 (ja) 2008-09-01 2008-09-01 半導体装置
JP2008-222979 2008-09-01
JP2008222979 2008-09-01

Publications (2)

Publication Number Publication Date
CN101667563A true CN101667563A (zh) 2010-03-10
CN101667563B CN101667563B (zh) 2012-05-16

Family

ID=41724081

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009101667933A Expired - Fee Related CN101667563B (zh) 2008-09-01 2009-08-20 半导体器件及其制造方法以及半导体密封用树脂

Country Status (4)

Country Link
US (1) US8203221B2 (zh)
JP (1) JP4585022B2 (zh)
KR (1) KR101585250B1 (zh)
CN (1) CN101667563B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10147697B1 (en) * 2017-12-15 2018-12-04 Nxp Usa, Inc. Bond pad structure for semiconductor device packaging

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4610932A (en) * 1984-12-06 1986-09-09 At&T Technologies, Inc. Electrical contacts
US5246511A (en) * 1990-05-14 1993-09-21 Hitachi Metals, Ltd. High-strength lead frame material and method of producing same
JP3701373B2 (ja) 1995-11-17 2005-09-28 大日本印刷株式会社 リードフレームとリードフレームの部分貴金属めっき方法、及び該リードフレームを用いた半導体装置
KR100231838B1 (ko) * 1997-05-20 1999-12-01 유무성 집적회로용 리드프레임 및 그 제조방법
JP4086949B2 (ja) * 1998-02-10 2008-05-14 古河電気工業株式会社 金属被覆部材
JP2001335708A (ja) * 2000-05-26 2001-12-04 Matsushita Electric Works Ltd 熱可塑性樹脂組成物、その製造方法、並びに半導体素子収納用パッケージ
JP2003068965A (ja) * 2001-08-30 2003-03-07 Hitachi Ltd 半導体装置
JP4976718B2 (ja) * 2005-03-25 2012-07-18 住友化学株式会社 固体撮像装置及びその製造方法
KR100997606B1 (ko) * 2005-07-29 2010-11-30 스미토모 베이클라이트 가부시키가이샤 에폭시 수지 조성물 및 반도체장치

Also Published As

Publication number Publication date
US20100052139A1 (en) 2010-03-04
JP4585022B2 (ja) 2010-11-24
JP2010062169A (ja) 2010-03-18
US8203221B2 (en) 2012-06-19
KR20100026994A (ko) 2010-03-10
CN101667563B (zh) 2012-05-16
KR101585250B1 (ko) 2016-01-13

Similar Documents

Publication Publication Date Title
US10978418B2 (en) Method of forming an electrical contact and method of forming a chip package with a metal contact structure and protective layer
JP4421972B2 (ja) 半導体装置の製法
CN104485321B (zh) 半导体管芯封装件及其制造方法
CN1261009C (zh) 半导体管芯的对称封装
US8304872B2 (en) Lead frame, method for manufacturing the same and semiconductor device
US10312212B2 (en) Self-adhesive die
DE102014100196B4 (de) Verfahren zum elektrophoretischen Abscheiden (EPD) eines Films auf einer exponierten leitfähigen Oberfläche und ein elektrisches Bauteil daraus
US9368435B2 (en) Electronic component
CN106067511A (zh) 带树脂引线框、半导体装置及其制造方法
CN102386106A (zh) 部分图案化的引线框以及在半导体封装中制造和使用其的方法
TWI375998B (en) Adhesive sheet for producing a semiconductor device
CN106328604A (zh) 芯片封装
CN101133491A (zh) 不含铅且多层被预镀敷的引线框
KR20120118485A (ko) 반도체 장치
CN1630070A (zh) 半导体装置制造用粘结膜
CN104205314B (zh) 半导体装置及其制造方法
CN103377951A (zh) 半导体器件的制造方法和半导体器件
CN107851693A (zh) 氮化物半导体发光元件用的基台及其制造方法
CN112117251A (zh) 芯片封装结构及其制作方法
CN104205315B (zh) 半导体装置
CN101667563B (zh) 半导体器件及其制造方法以及半导体密封用树脂
JP2013209450A (ja) 半導体封止用エポキシ樹脂組成物
US10049966B2 (en) Semiconductor device and corresponding method
CN211879377U (zh) 器件
CN102005418A (zh) 半导体装置及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120516

Termination date: 20180820