CN101657891A - 凸面管芯连接方法 - Google Patents
凸面管芯连接方法 Download PDFInfo
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- CN101657891A CN101657891A CN200880011809A CN200880011809A CN101657891A CN 101657891 A CN101657891 A CN 101657891A CN 200880011809 A CN200880011809 A CN 200880011809A CN 200880011809 A CN200880011809 A CN 200880011809A CN 101657891 A CN101657891 A CN 101657891A
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- Die Bonding (AREA)
Abstract
提供了一种组装一种微电子装置的方法,该方法包含使用凸面管芯连接工艺将管芯粘着到基片的步骤。该凸面管芯连接工序基本上包括a)提供其上具有底部填充材料的管芯,b)捡起该管芯并将该管芯翻转,c)加热该底部填充材料的管芯直到它至少轻微地液化并形成凸出表面,以及d)将管芯放置在基片上。
Description
相关申请的交叉引用
本申请依据35U.S.C§119(e)要求享有于2007年3月13日提交的标题为“凸面管芯连接方法”(Convex Die Attachment Method)的美国临时专利申请第No.60/894,574号的优先权,其公开内容通过引用被并入本文。
发明领域
本发明涉及电子封装。更具体地,本发明涉及用于组装电子封装件的一种方法,该方法采用在将管芯放置在基片上之前,将无流式底部填充材料(no-flow underfill)施加到管芯。
发明背景
在传统的制造工序中,在一般以硅为半导体材料的单个大“晶片”上大量地构成包含电气元件的个别管芯。个别管芯有作为电气连接的小金属焊盘。该等个别管芯随后从晶片中被切出来,并使用从焊盘导出的小导线连接到外壳。这些导线连接到在外壳的外侧上的引脚,而引脚随后被连接到基片,比如印刷电路板(PCB)。
一种叫做“倒晶封装芯片”(flip-chip)、用于芯片制造的较新工序是有优势的,因为它不需要任何引线键合,并且经常被用于半导体装置,比如IC芯片。倒晶封装芯片是简单地被翻转(flipped over)的管芯,以使该管芯包含电路的一面最接近装配基片。在处理晶片的最后步骤中,焊料球或“凸块”被置入在管芯焊盘上,该焊料球或“凸块”被用于直接地连接到对应的、在基片上的接合连接器的电路。
倒装芯片的处理和常规IC制造类似,但有一些轻微的修改。在晶片被制造后,一小焊料点马上被置入在每个焊盘上。个别的管芯随后从晶片中被切出来(被切片)。通过将芯片翻转以使焊料球被向下放置到下面的电子设备或电路板上的连接器,该倒装芯片被连接到基片。焊料随后被重新融化(回流),以在管芯上的电路和基片之间产生电连接。
回流的焊料凸块在管芯的接触区域和基片的接触区域之间产生机械的和电气的连接。然而,由于焊料的性质,该机械连接是相对弱的,并且易于在管芯的自然热循环过程中变形或裂开。另外,管芯表面的底面保持外露、通过回流的焊料凸块在安装基片的表面离开地被悬挂。一种通常被称为底部填充材料(underfill)的电气绝缘的粘合剂,一般通过注射施加入此空间,并被固化,以提供更强的机械连接、提供热桥,以及确保焊料接合点不会由于管芯和基片之间的热膨胀系数的差异而受压。
底部填充材料经管芯和基片之间的毛细作用而流动,并因此需要可观的时间以及需要从多个点施加,以确保在管芯和基片之间没有未被填充的空隙。底部填充材料一般是基于环氧树脂的,并且具有合适的粘性以恰当地流动且在固结/固化之后机械地强固。在施加注射后,底部填充材料就被加热,以驱逐出任何溶剂,并/或使底部填充复合材料固化。这可以在焊料回流过程之前,或者作为焊料回流过程的一个部分被完成。
底部填充材料常常不完全地填充元件之间的空间,以至在管芯下留有空气。在来自回流炉的热量引起残存空气膨胀并胀破底部填充材料或管芯时,可能引起该部分的灾难性的故障。
在和其它的自动工序中相比,用注射器手动地施加底部填充材料是花费时间且劳动密集性的步骤。消除此步骤的一个尝试涉及到,在基片上放置管芯之前,用底部填充材料在合适的位置涂覆基片。这通常被称为无流式底胶充填,并图1A-1C中显示。晶片被制作完成后,一小焊料点就被置入在每个焊盘上。个别管芯随后从晶片中被切出来(被切片)。包含焊料凸块20的管芯10随后被倒转到准备对齐并放置在基片上的位置,如图1A所示。图1B示出了处于倒转位置的管芯10,准备对齐并放置在基片40上,其中该基片40已经被涂有底部填充复合材料30。管芯10被对齐以使焊料凸块30与基片40上的连接器50对齐。在图1C中,倒装芯片10被放置并连接到基片40,以使焊料球20被向下放置到在下面的电子设备或者电路板60的连接器50上,且焊料被回流。虽然此工序使底部填充材料的施加自动化,但是仍然存在的问题是,底部填充材料在基片上的润湿不均匀,以及焊料凸块妨碍了空气从元件之间脱逸,以至在管芯和基片之间存在残存空气60。
发明概述
在本发明的第一方面,提供了用于组装微电子装置的一种方法,该方法包含使用凸面管芯连接工艺将管芯粘着到基片的步骤。
在本发明的第二方面,提供了一种用于形成电子组件的方法,该方法包括:
a)提供在其上有底部填充材料的管芯;
b)捡起并翻转管芯;
c)加热底部填充材料直到它至少轻微地液化并形成一凸面,以及
d)将管芯放置在基片上。
在本发明的一个实施方式中,该管芯包括微电子元件。在本发明的另一个实施方式中,该管芯包括外部电连接。在本发明的又一个实施方式中,该管芯包括焊料凸块,以及在本发明的另一个实施方式中,底部填充材料大致上围绕焊料凸块。在本发明的一个另外的实施方式中,该基片包括用于与焊料凸块连接的焊盘。
在本发明的另一个实施方式中,方法的步骤a)包括:
a1)提供晶片;
a2)在所述晶片上形成焊料凸块;
a3)使用包含环氧树脂和溶剂的底部填充材料涂覆所述具有凸块的晶片;
a4)干燥所述底部填充材料以大致上移除全部的溶剂;
a5)将晶片切成个别的管芯。
在本发明的另外的实施方式中,干燥底部填充材料以大致上移除上全部的溶剂的步骤是在真空下进行的和/或底部填充材料被加热以干燥底部填充材料。
在本发明的一个实施方式中,捡起管芯并将管芯翻转的步骤包括:使用加热的管芯接合器捡起管芯,该加热的管芯接合器通过所述管芯的主体提供加热步骤的热量。在本发明的一个变化的实施方式中,底部填充材料经由导向该管芯的热空气流被加热。
在本发明的另一个实施方式中,将涂覆后的管芯定位和放置在基片上的步骤包括:
d1)将管芯上的焊料凸块与基片上对应的焊盘对准;
d2)将管芯放置在基片上;
d3)允许底部填充材料润湿基片并实质上填充管芯和基片之间的空间;
d4)加热组件以凝固底部填充材料。
在本发明的一个实施方式中,底部填充材料是通过加热组件来固化的。在本发明的另一个实施方式中,加热组件以固化底部填充材料的步骤包括:将基片加热到足以使焊料回流的温度。
在本发明的另一个实施方式中,底部填充复合材料包含环氧树脂、溶剂、固化剂,并可选择地包括焊剂(flux)。在本发明的又一个实施方式中,固化剂包含热潜伏固化剂。在本发明的另一个实施方式中,环氧树脂包含固态双酚A或双酚F环氧树脂。在本发明的又一个实施方式中,环氧树脂的熔点低于大约100℃。在本发明的另外的实施方式中,溶剂包含二氯甲烷。
在本发明的另一个实施方式中,基片包含另一个管芯以形成堆叠的芯片组件。在本发明的另外的实施方式中,堆叠的芯片组件包含多个管芯。在本发明的另一个实施方式中,在放置涂有底部填充材料的管芯之前,基片被涂有底部填充组合物。
附图简述
图1示出了现有技术的微电子组件。
图2示出了在本发明的一个实施方式中的凸面管芯连接工艺,该实施方式包括(a)涂覆后的翻转的管芯,(b)在其上形成有凸面的加热的管芯,以及(c)将管芯放置在基片上。
图3示出了依据本发明的一个实施方式的完整的制造和焊接工艺,该实施方式包含(a)带有焊料凸块的晶片,(b)施加有底部填充材料的晶片,(c)带有被干燥的底部填充材料的晶片,(d)被切片的晶片,(e)被捡起并翻转的管芯,(f)放置在基片上的管芯,以及(g)管芯粘着到焊料已回流和底部填充材料已固化的基片。
发明详细详述
在微电子元件的制造中有多种方法用于生产硅晶片、粘着焊料凸块以及将晶片切成个别的管芯。本发明的各种实施方式的方法可以容易地被整合进本领域技术人员能认识的现存工艺中。
在本发明的第一方面,管芯被涂有底部填充材料。底部填充材料优选地包含环氧树脂。该底部填充材料可以选择地包含一种或多种固化剂、溶剂、焊剂溶液以及填料。在本发明的一个实施方式中,包含多个管芯的晶片被涂覆,然后被切成个别的已涂覆管芯。在本发明的另一个实施方式中,管芯在从晶片切出后个别地被涂覆。
在本发明的另一个实施方式中,底部填充复合材料的一个重要特性是它的液化温度。该液化温度为固态的底部填充材料液化并开始流动的温度,从而在管芯被翻转时,由于重力在其上形成凸面。在本发明的一个实施方式中,此温度将落在用于倒装芯片应用的通用的工作和处理范围内,并且可以从大约20℃变化到大约270℃。在本发明的一个优选的实施方式中,该液化温度将在从大约40℃到大约150℃的范围内,并且最优选地为从大约80℃到大约120℃。
本发明的方法采用的底部填充复合材料可以包括适合于如本文描述的加热/液化步骤的任何底部填充复合材料。底部填充复合材料被调节为具有合适的粘性、液化温度以及可以对于特定的用途所需要的任何其它性质。在本发明的一个优选实施方式中,底部填充复合材料包括基于环氧树脂的底部填充材料,其包括热潜伏固化剂。该热潜伏固化剂允许底部填充材料在管芯上被加热而不引起固化,以允许底部填充材料在捡起/加热/放置各步骤的整个过程中保持非固化。在管芯被放置在基片上后,底部填充材料就接着被加热到固化剂的初始温度以上,以使环氧树脂开始固化。在环氧树脂聚合或交联到使得粘性相当地增加的程度时,固化开始。
在本发明的最优选的实施方式中,底部填充复合材料包含熔点温度低于大约100℃的双酚A或双酚F固态环氧树脂,以及热潜伏固化剂,比如Stapleton的美国专利申请公开号2008/0012124号中描述的固化剂,该固化剂具有在大约150℃以上的固化初始温度。
在大多数倒装芯片装置中,焊料球的大小范围为从25μm到500μm。根据用途,底部填充材料可以完全地覆盖焊料球或者仅仅覆盖其一部分。因此,在本发明的一个实施方式中,底部填充材料的厚度可以从0.1μm变化到10mm,优选地在25μm到1mm之间,并且理想地在100μm到400μm之间。然而,应认识到,微电子元件组件的几何形状和底部填充材料的性质将规定施加的最终厚度。
在本发明的、底部填充材料包含溶剂的实施方式中,在放置步骤之前,需要干燥步骤以从底部填充材料移除溶剂。该干燥步骤包括,例如加热底部填充材料以使溶剂蒸发,或将底部填充材料放置于真空下,以使溶剂从底部填充材料移除。
当管芯被涂覆了底部填充材料并且移除了任何溶剂,那么涂覆后的管芯可以选择地被储存一段时间,直到微电子元件组件要被构造为止。
在本发明的进一步的实施方式中,如图2A-2C中所示,涂有底部填充材料30的管芯10被捡起并翻转,以便焊料球20和底部填充复合组合物30向下。涂有底部填充材料20的管芯10随后被加热。在加热到足够的温度后,即在或接近底部填充材料的液化温度时,重力和表面张力将使底部填充材料形成一凸面,如图2B中所示。在本发明的实施方式中,凸面的形状可以使用温度、涂层厚度、粘性以及底部填充材料的表面能来调节。包括具有一凸面的底部填充复合材料30的被加热的管芯10随后被定位并放置在基片40上。底部填充材料30的凸形允许空气60脱逸,以防止在管芯10和基片40之间残留有空气。
在本发明的一个实施方式中,通过用加热的管芯接合器来使管芯便于被捡起、加热以及放置。管芯接合器一般地使用放置头,该放置头经由抽吸捡起管芯、将板和管芯放置对准,然后将管芯放置在板上并停止抽吸以释放管芯。加热的管芯接合器,比如由Datacon(Datacon North America,Trevose,PA 19053)出售的那些管芯接合器,在管芯被放置时,允许管芯和/或基片同时加热。用于加热管芯的方式包括,通过加热放置头以传导加热管芯、经由从管芯接合器传导的热量加热基片,或者经由热空气流对板和/或基片进行对流加热。
管芯被放置成使得焊料球接触在基片上对应的连接器焊盘,以允许管芯和基片(优选地为印刷电路板)之间的电气互连。在底部填充材料润湿基片时,底部填充材料的凸形保留使空气脱逸的空间。这防止了在本文论述的不希望有的空气的残存。底部填充材料可润湿基片的表面,并大致上填充管芯和基片之间的区域,和围绕焊料球。在本发明的一个优选的实施方式中,基片完全地围绕焊料球,在底部填充材料中不留任何空隙。
在本发明的一个替代的实施方式中,捡起并放置的步骤是使用倾斜的或不均匀的捡起及放置头(pick and place head)实现的。这将允许将管芯放置时,凸出涂层的顶点相对于管芯偏离中心。类似地,在某些情形中,保持基片处于相对于管芯呈一角度,以提供相同的偏中心对准,可以是有利的。
在本发明的另一个实施方式中,管芯和基片二者在放置步骤的过程中均被加热。加热管芯和板确保底部填充材料保持为液体,直到它有机会充分地润湿基片的表面。通常,温度将在正常的操作温度范围大约20℃到大约270℃内。在本发明的一个优选的实施方式中,该温度在大约40℃和大约150℃之间,并且理想地在大约80℃和大约120℃之间。
在管芯被放置在基片上后,微电子组件被加热以使焊料回流并固化底部填充复合材料。在本发明的一个替代的实施方式中,底部填充材料在放置之后但在使焊料回流之前被冷却。这允许底部填充复合材料重新固化并将组件保持在一起。这在放置和回流之间有时间延迟时,或者在组件在这些步骤之间必须被移动或储存时可以是有优势的。在本发明的一个另外的实施方式中,组件被置于后烘烤工序,以使底部填充材料在低于焊料回流温度的温度下固化。
在本发明的另一个实施方式中,基片和管芯都被涂有底部填充材料。在基片上的底部填充材料涂层通过覆盖基片的任何表面特征物比如焊料掩模或突出的电气互连点,来提供均匀的接触表面。应用在基片上的底部填充材料的成分可以与涂覆管芯的不同。然而,在本发明的优选的实施方式中,基片上的底部填充复合材料与在管芯上的底部填充复合材料大致上相同。另外,涂覆基片这一做法,在管芯被放置时提供底部填充材料对底部填充材料的接触,这会改进润湿,并进一步减少在放置过程中残留空气的可能性。
在本发明的另一个实施方式中,该基片包含另一个管芯。在此实施方式中,微电子组件由将管芯一个堆叠在另一个上并同时互相带有电气互连而构成。其在本发明此实施方式的范围内,以在依据本文的不同实施方式的方法制备的组件中提供多个堆叠的管芯。
例子
在本发明的第一示范性的实施方式中,如图3A-3G所示,本发明的实施方式的方法被并入微电子元件生产工序。在图3A中,该工序从在其上形成有多个焊料凸块120的晶片100开始。在图3B中晶片100被涂有底部填充材料130,该底部填充材料130完全覆盖焊料凸块120。底部填充材料130依据表1包括固态的环氧树脂、热潜伏固化剂、溶剂以及焊剂溶液。
表1——底部填充复合材料
*LORD Curative包含在Stapleton的美国专利申请第2008/0012124号中描述的固化剂。
如图3C所示,底部填充组合物130随后通过使用热量和微真空移除涂层溶剂而硬化,以在管芯100上产生非粘性的干燥涂层,该非粘性的干燥涂层完全地覆盖焊料凸块120。随后晶片100被切割成个别的管芯110,如图3D所示。
如图3E所示,个别的管芯110随后被加热的管芯接合器170捡起,在此时,固态的未固化树脂130液化以产生凸面。在图3F中,带有低粘度的凸出表面的管芯110随后被对准并放置到被加热的板140上,允许树脂130在连接工序的过程中润湿板140的表面。板140在放置的过程中同时被加热到一温度,该温度低于可能会使板140损坏或者使树脂开始固化的温度。
然后管芯110和板140通过回流炉,以形成120和板140上的电气元件150之间的物理连接。然后组件在180-200℃被后烘烤1小时,以确保底部填充复合材料完全固化。
虽然本发明已经参考特定的实施方式进行了描述,但应认识到这些实施方式仅为对本发明的原理的说明。本领域技术人员应知晓本发明的装置和方法可以以其它的形式和实施方式构造和实施。因此,本文的描述不应被理解为限制本发明,因为其它实施方式也属于本发明的范围。
虽然本发明已经参考特定的实施方式进行了描述,但应认识到这些实施方式仅为对本发明的原理的说明。本领域技术人员应知晓本发明的复合材料、装置和方法可以以其它的形式和实施方式构造和实施。因此,本文的描述不应被理解为限制本发明,因为其它实施方式也属于本发明由附加的权利要求界定的范围。
Claims (22)
1.一种用于形成电子组件的方法,其包括:
a)提供在其上具有底部填充材料的管芯;
b)捡起并翻转所述管芯;
c)加热所述底部填充材料直到所述底部填充材料至少轻微地液化并形成一凸面,以及
d)将所述管芯放置在基片上。
2.如权利要求1所述的方法,其中所述管芯包括微电子元件。
3.如权利要求1所述的方法,其中所述管芯包括外部的电连接。
4.如权利要求1所述的方法,其中所述管芯包括焊料凸块。
5.如权利要求4所述的方法,其中在步骤a)中,所述底部填充材料大致上围绕所述焊料凸块。
6.如权利要求4所述的方法,其中所述基片包括用于与所述焊料凸块连接的焊盘。
7.如权利要求1所述的方法,其中步骤a)包括:
a1)提供晶片;
a2)在所述晶片上形成焊料凸块;
a3)使用包含树脂和溶剂的底部填充材料涂覆所述具有凸块的晶片;
a4)干燥所述底部填充材料以大致上移除全部的溶剂;
a5)将所述晶片切成个别的管芯。
8.如权利要求7所述的方法,其中步骤a4)是在真空下进行的。
9.如权利要求7所述的方法,其中在步骤a4)中,所述底部填充材料被加热以干燥所述底部填充材料。
10.如权利要求1所述的方法,其中步骤b)包括:使用加热的管芯接合器捡起所述管芯,所述接合器通过所述管芯的主体为步骤c)提供热量。
11.如权利要求1所述的方法,其中在步骤c)中,所述底部填充材料经由导向所述管芯的热空气流被加热。
12.如权利要求1所述的方法,其中步骤d)包括:
d1)将所述管芯上的所述焊料凸块与所述基片上对应的焊盘对准;
d2)将所述管芯放置在所述基片上;
d3)允许所述底部填充材料润湿所述基片并大致上填充所述管芯和所述基片之间的空间;
d4)加热所述组件,以固结所述底部填充材料。
13.如权利要求12所述的工艺,其中在步骤d4)中,所述底部填充材料被固化。
14.如权利要求12所述的工艺,其中步骤d4)包括:将所述基片加热到足以使所述焊料回流的温度。
15.如权利要求1所述的工艺,其中所述底部填充复合材料包含环氧树脂、溶剂、固化剂,并可选择地包括焊剂。
16.如权利要求15所述的工艺,其中所述固化剂包含热潜伏固化剂。
17.如权利要求16所述的工艺,其中所述环氧树脂包含固态的双酚A或双酚F环氧树脂。
18.如权利要求16所述的工艺,其中所述环氧树脂的熔点小于大约100℃。
19.如权利要求15所述的工艺,其中所述溶剂包含二氯甲烷。
20.如权利要求1所述的工艺,其中所述基片包含另一个管芯以形成堆叠的芯片组件。
21.如权利要求20所述的工艺,其中所述堆叠的芯片组件包含多个管芯。
22.如权利要求1所述的工艺,其中,在放置涂有底部填充材料的管芯之前,所述基片被涂有底部填充组合物。
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WO2010061552A1 (ja) * | 2008-11-25 | 2010-06-03 | 住友ベークライト株式会社 | 電子部品パッケージおよび電子部品パッケージの製造方法 |
US20120178219A1 (en) * | 2011-01-11 | 2012-07-12 | Nordson Corporation | Methods for vacuum assisted underfilling |
US8796075B2 (en) | 2011-01-11 | 2014-08-05 | Nordson Corporation | Methods for vacuum assisted underfilling |
KR20140007429A (ko) * | 2011-03-31 | 2014-01-17 | 미쓰비시 가가꾸 가부시키가이샤 | 삼차원 집적 회로 적층체, 및 삼차원 집적 회로 적층체용 층간 충전재 |
KR20140058557A (ko) | 2011-07-15 | 2014-05-14 | 쓰리엠 이노베이티브 프로퍼티즈 컴파니 | 반도체 패키지 수지 조성물 및 그의 사용 방법 |
US8865487B2 (en) * | 2011-09-20 | 2014-10-21 | General Electric Company | Large area hermetic encapsulation of an optoelectronic device using vacuum lamination |
US9461008B2 (en) * | 2012-08-16 | 2016-10-04 | Qualcomm Incorporated | Solder on trace technology for interconnect attachment |
JP2014091744A (ja) | 2012-10-31 | 2014-05-19 | 3M Innovative Properties Co | アンダーフィル組成物、半導体装置およびその製造方法 |
DE102013102542A1 (de) * | 2013-03-13 | 2014-09-18 | Schweizer Electronic Ag | Elektronisches Bauteil und Verfahren zum Herstellen eines elektronischen Bauteils |
US9972590B2 (en) * | 2016-07-05 | 2018-05-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Semiconductor package having a solder-on-pad structure |
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WO1999004430A1 (en) * | 1997-07-21 | 1999-01-28 | Aguila Technologies, Inc. | Semiconductor flip-chip package and method for the fabrication thereof |
SG88747A1 (en) * | 1999-03-01 | 2002-05-21 | Motorola Inc | A method and machine for underfilling an assembly to form a semiconductor package |
JP2000339648A (ja) * | 1999-05-24 | 2000-12-08 | Tdk Corp | 磁気ヘッド装置の製造方法 |
US6796481B2 (en) * | 2000-01-14 | 2004-09-28 | Toray Engineering Co., Ltd. | Chip mounting method |
TW574739B (en) * | 2001-02-14 | 2004-02-01 | Nitto Denko Corp | Thermosetting resin composition and semiconductor device using the same |
US7323360B2 (en) * | 2001-10-26 | 2008-01-29 | Intel Corporation | Electronic assemblies with filled no-flow underfill |
US7180640B2 (en) * | 2002-09-20 | 2007-02-20 | Maltseff Paul A | Monolithic micro scanning device |
WO2004034433A2 (en) * | 2002-10-08 | 2004-04-22 | Chippac, Inc. | Semiconductor stacked multi-package module having inverted second package |
US6919420B2 (en) * | 2002-12-05 | 2005-07-19 | International Business Machines Corporation | Acid-cleavable acetal and ketal based epoxy oligomers |
US7301222B1 (en) * | 2003-02-12 | 2007-11-27 | National Semiconductor Corporation | Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages |
US20050028361A1 (en) * | 2003-08-07 | 2005-02-10 | Indium Corporation Of America | Integrated underfill process for bumped chip assembly |
US7229933B2 (en) * | 2004-03-31 | 2007-06-12 | Intel Corporation | Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor |
US7485502B2 (en) * | 2006-01-31 | 2009-02-03 | Stats Chippac Ltd. | Integrated circuit underfill package system |
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US20080280392A1 (en) | 2008-11-13 |
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