CN101656236A - Submount and method for manufacturing same - Google Patents

Submount and method for manufacturing same Download PDF

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Publication number
CN101656236A
CN101656236A CN 200910168047 CN200910168047A CN101656236A CN 101656236 A CN101656236 A CN 101656236A CN 200910168047 CN200910168047 CN 200910168047 CN 200910168047 A CN200910168047 A CN 200910168047A CN 101656236 A CN101656236 A CN 101656236A
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submount
layer
brazing layer
brazing
substrate
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CN 200910168047
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CN101656236B (en
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大鹿嘉和
中野雅之
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Dowa Electronics Materials Co Ltd
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Dowa Electronics Materials Co Ltd
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Priority claimed from JP2005091941A external-priority patent/JP2006278463A/en
Priority claimed from JP2005105045A external-priority patent/JP2006286944A/en
Priority claimed from JP2005105046A external-priority patent/JP5062545B2/en
Priority claimed from JP2005105044A external-priority patent/JP2006286943A/en
Application filed by Dowa Electronics Materials Co Ltd filed Critical Dowa Electronics Materials Co Ltd
Publication of CN101656236A publication Critical patent/CN101656236A/en
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Publication of CN101656236B publication Critical patent/CN101656236B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor

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Abstract

A submount with an electrode layer having excellent wettability in soldering and method of manufacturing the same are disclosed. A submount (1) for having a semiconductor device mounted thereon comprises a submount substrate (2), a substrate protective layer (3) formed on a surface of the submount substrate (2), an electrode layer (4) formed on the substrate protective layer (3) and a solder layer(5) formed on the electrode layer (3) wherein the electrode layer (4) is made having an average surface roughness of less than 1 [mu]m. The reduced average surface roughness of the electrode layer (4) improves wettability of the solder layer (5), allowing the solder layer (5) and a semiconductor device to be firmly bonded together without any flux therebetween. A submount (1) is thus obtained which with the semiconductor device mounted thereon is reduced in heat resistance, reducing its temperature rise and improving its performance and service life.

Description

Submount and manufacture method thereof
The application be the applying date be on March 17th, 2006, Chinese patent application number be 200680012991.9, denomination of invention divides an application for " Submount and manufacture method thereof ".
Technical field
Submount that the present invention relates in semiconductor device, use and manufacture method thereof.
Background technology
Usually, with semiconductor device packages the time, carry on heating panel or the radiator, carry out from the heat radiation of the heat of semiconductor device generation.Have in order to improve heat dissipation characteristics between semiconductor device and heating panel, clamp the higher substrate of pyroconductivity, be the situation of Submount (Submount) parts.As the higher substrate of this pyroconductivity, known have an aluminium nitride (AlN) etc.
With under Submount and the situation that semiconductor device engages, its bond strength is arranged as a requirement.In the prior art, the noble metal by costliness is provided with adhesion layer or in order to improve the surface roughness that electrode layer on the bottom surface that is configured in brazing layer and the bond strength between the substrate are regulated substrate itself.
In patent documentation 1, disclose in the Submount that covers by metal level according to the sequential cascade of Ti, Pt, Au, on Au, also carried the Submount structure of semiconductor light-emitting elements across the soldering adhesion layer that constitutes by Ti and Pt and brazing layer.In the document, record following content: when being bonded on semiconductor light-emitting elements on the brazing layer, with the bond strength of semiconductor light-emitting elements be more than the 40MPa, and the surface roughness of the substrate that uses in Submount (Ra) is preferably below the 1 μ m, more preferably below the 0.1 μ m.If surface roughness surpasses 1 μ m, then when the joint of semiconductor light-emitting elements easily and Submount between produce the gap, so the cooling effect of semiconductor light-emitting elements reduces.
In patent documentation 2, disclosing the metal level of using on the substrate that is made of AlN according to the sequential cascade of Ti, Pt, Au covers in the Submount that obtains, surface roughness (Ra) by making substrate is 0.1 to 0.5 μ m, can provide anchor effect because of above-mentioned film forming metal can tolerate thermal cycle, have the Submount of higher bond strength for the AlN substrate.The comparative example that can not obtain enough bond strengths under the too small situation of the surface roughness that makes the AlN substrate is also disclosed.As the higher substrate of pyroconductivity, can enumerate (for example with reference to patent documentations 3) such as aluminium nitride.
In patent documentation 3,4,5, disclose at the 1st of installation semiconductor laser (LD) chip of Submount and bonded to the alloy-layer that is formed with barrier layer, Au and Sn on the 2nd the two sides of heat transmission metal derby or the semiconductor element Submount of the alloy-layer of Sn and Pb.In the document, alloy-layer forms by evaporation, and its alloy composition is adjusted to for example Au: Sn=70: the so-called eutectic composition of 30 (element ratios).By the alloy-layer fusion is joined to LD chip and heat transmission metal derby on the Submount.
In patent documentation 3 and 5, the action layer that discloses the semiconductor laser diode that will produce heat is bonded on the Submount technology that heat dissipation characteristics is improved.In the case, be that the what is called of downside meets down (junction-down) and is bonded on the substrate by the surface that makes the extremely thin action layer that forms by epitaxial growth.Thereby, when engaging, be difficult for taking place because of the poor short circuit of bringing of adhering to of brazing layer to the pn joint.
Like this, Submount is the distortion of the effect of the brazing material when having chip join and the optical semiconductor that brings for the thermal expansion that relaxes the heat transmission metal derby in the chip join and unusual important components.In above-mentioned Submount, with carry the semiconductor element chip on the Submount substrate engage and the Submount substrate is to be undertaken by single face and/or the brazing layer on the two sides that is formed on Submount to the joint of heating panel.
In order to reduce carrying capacity of environment, do not use Pb as the use of the soldering of grafting material, promptly do not have a constantly development of Pbization, the material soldering that proposed Au-Sn, Ag-Sn, In-Sn, Zn-Sn etc. is formed as an alternative.But, under the situation of no Pb soldering, because fusing point becomes than Pb soldering (fusing point of PbSn is 183 ℃) height, thus when semiconductor element is engaged, diminish with the difference of the heat resisting temperature of semiconductor element, so problem such as generating device deterioration sometimes.In addition, there is use amount increase to make surface oxidation easily, also bring the situation of influence for the wettability of soldering self because of Sn and In.
Here, as with one of semiconductor element most important characteristic when brazing layer is bonded on the Submount, brazing layer when soldered joint is arranged and the wettability between the electrode layer.The wettability of normally used no Pb soldering is relatively poor, generally uses the solder flux of rosin based etc.On the other hand, as paste soldering or spherical cored solder wire reticulated printing etc., used under the situation of soldered joint of solder flux, owing to make surface wettability, so infiltrating influence does not almost have by solder flux.But, under the situation that engages the very little semiconductor element of same thickness and volume in the very little soldering of thickness as Submount and volume, owing to can not ignore the influence of solder flux, so situation about engaging without solder flux is arranged to the output reliability of the semiconductor element of joint.Therefore, the wettability of the soldering of Submount is very poor.
In such brazing layer, special in the brazing layer that constitutes by the low melting point brazing material that contains Sn or In as composition, be exposed to the easy oxidation of lip-deep Sn or In, form oxide-film in its surface, so the situation that is difficult for joint when engaging because of the influence soldering of oxide-film is arranged.As the method that is used for improving this situation, in non-patent literature 1, reported that the brazing layer that will contain Sn or In as composition places vacuum atmosphere or reducing atmosphere, the technology that engages after oxide-film is removed.
In non-patent literature 2, reported in the brazing layer of Au-Sn class, Sn layer and Au are folded formation layer by layer and the Au layer is set so that Sn does not expose brazing layer in its surface on the most surperficial.In non-patent literature 3, reported the soldering of when joining to the Si semiconductor element on the Si substrate, using as also, make the technology that makes Sn not be exposed to lip-deep lit-par-lit structure.The brazing layer self of having reported Submount in non-patent literature 4 is formed by alloy, and forms the Au layer on the brazing layer surface, to realize anti-oxidation method.
Under the situation of using no Pb soldering, brazing layer is made lit-par-lit structure so that the metal of easy oxidation such as Sn is not exposed on the surface, thereby engage as eutectic composition.Reported in the case,, also can develop, so also diffusion (with reference to non-patent literature 5 and 6) easily of metallic atom to poised state even at room temperature place because brazing layer self is a nonequilibrium condition.
Like this, in the prior art, as the form of the brazing layer before the fusion, the brazing layer (suitably being called the alloy brazed layer later on) after always using eutectic composition that the formation element of brazing layer formed by alloying.That is, in the operation that the brazing layer before the fusion is formed on the Submount substrate, the general constituent ratio of regulating the metallic element that forms brazing layer that adopts is so that it becomes the method for the eutectic composition of hope.If by the soldering that constitutes of any or they of metallic elements such as Sn element and Au, Ag, Pb, for example be Au-Sn alloy brazed layer, then regulate so that Au: Sn=70: 30 (elements than).
And then a requirement when Submount is engaged with semiconductor light-emitting elements has the uneven reduction of its junction temperature.When Submount is engaged with semiconductor light-emitting elements, by the brazing layer heating and melting that will on Submount, form up to becoming liquid phase fully, it is contacted with the electrode that is formed on semiconductor element side, cooling curing then, thus across the brazing layer of fusion Submount is engaged with semiconductor light-emitting elements.As the heating means of brazing layer, the large-scale heating means of using resistance-heated furnace or hot platform etc. or the local anxious heating means of heating of local lamp or hot gas heating etc. etc. are arranged, wait according to the form of encapsulation and operation and select heating means.But, under the situation of using local anxious heating means to heat, because of the heating-up temperature deviation often takes place for the difference of the material of Submount and semiconductor element or the performance of heater etc.And, under the temperature of heater likened to the low situation of the junction temperature of target, degradation undesirable condition under the wettability of fusion joint not or soldering took place easily.Otherwise, under the temperature of heater likens to the high situation of the junction temperature of target, the undesirable condition that destruction that semiconductor element chip takes place sometimes etc. is brought.
In addition, the poor short circuit that the brazing layer in order to prevent to engage has brought to having climbed of semiconductor element in patent documentation 3, forms brazing layer by evaporation, and its thickness is thinned to approximately (0.5 μ m).In patent documentation 5, in order to prevent flowing of brazing layer, on the Submount substrate, be provided with and prevent that soldering from flowing and use groove, soldering is flow in the groove.
In addition, the situation that forms circuit pattern and carry semiconductor device on Submount is arranged.In order to form the such fine pattern of electrode layer, if use the photoetching rule to form with comparalive ease.As photolithographic developer solution, generally use the such alkaline-based developer of tetramethyl amine.According to this mode, can carry out the Butut under the 1 μ m unit.
As using photolithographic concrete electrode formation method, lifting from (lift off) mode is main flow.Lifting in mode, in advance by rotary coating device etc. behind painting erosion resistant agent on the one side, implement Butut by photoetching process earlier.Then,,, by with the resist dissolving and the part of film forming on the upper surface of resist removed and form the electrode of regulation the electrode film forming by vapour deposition method or sputtering method.But, in the development behind photolithographic cloth exposure map, owing to directly contact with developer solution as the Submount substrate surface of electrode evaporation, so the situation of substrate surface because of roughening such as corrosion arranged according to the base material material.
Patent documentation 1: the spy opens the 2002-368020 communique
Patent documentation 2: the spy opens the 2001-308438 communique
Patent documentation 3: the spy opens flat 1-138777 communique
Patent documentation 4: special fair 6-3815 communique
Patent documentation 5: special fair 8-31654 communique
Non-patent literature 1:J.F.Kuhmann and other 8 people, " Oxidation and ReductionKinetics of Eutectic SnPb; InSn and AuSn:A Knowledge Base for FluxlessSolder Bonding Applications ", IEEE Electronic Components andTechnology Conference, pp.120-126,1997
Non-patent literature 2:C.R.Dohle and other 3 people, " Low Temperature Bonding ofEpitaxial Lift Off Devices with AuSn ", IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part B, Vol.19, No.3, pp.575-580,1996
Non-patent literature 3:C.C.Lee and other 1 people, " Fluxless Non-Eutectic JointsFabricated Using Gold-Tin Multilayer Composite ", IEEE Transactions onComponents, Packaging, and Manufacturing Technologies, Vol.26, No.2, pp.416-426,2003
Non-patent literature 4:H.L.Chang and other 11 people, " Effect of Joint Strength ofPbSn and AuSn Solders on Temperature Cycling Tests in Laser Packages ", IEEE Conference Proceedings, LEOS Annual Meeting, IEEE Lasers AndElectro-Optics Society, pp.800-801,1999
Non-patent literature 5:S.Nakahara and other 3 people, " ROOM TEMPERATUREINTERDIFFUSION STUDIES OF Au/Sn THIN FILM COUPLES ", ThinSolod Films, Vol.84, pp.185-196,1981
Non-patent literature 6:M.Hutter and other 6 people, " Calculation of Shape andExperimental Creation of AuSn Solder Bumps for Flip Chip Applications ", IEEE Proceedings Electronic Components ﹠amp; Technology Conference, pp.282-288,2002
As mentioned above, in the Submount of conventional art, can cause the reduction of bond strength because of the deterioration that autgmentability is soaked in soldering or exceedingly rise for joint need make the soldering melting temperature.As a result, the deterioration of the semiconductor element that causes soldered joint or the problem of destruction are arranged.As the energy efficiency in the soldered joint process also is the situation of variation.Under the situation of the adhesion layer that has used noble metal, the bigger problem that also has cost to rise.
Forming on the Submount under the situation of electrode by lift-off method, it is big that the roughness of substrate surface becomes easily, the effect that the bond strength raising of the electrode layer self that makes film forming on substrate surface is arranged, but the electrode layer that film forming on the substrate surface of the thicker state of surface roughness also arranged simultaneously, is the problem of surface roughness chap also.
Summary of the invention
So the 1st purpose of the present invention is in view of the above problems, the Submount and the manufacture method thereof of the good electrode layer of a kind of wettability when having soldered joint is provided.
When the such use of conventional art does not have the Pb soldering semiconductor element is engaged, by
(1) make the soldering fusion with low temperature as far as possible,
(2) fusion of soldering is improved,
Promptly engage at low temperatures as far as possible, promptly add heat with having relatively high expectations that semiconductor element engages with minimum.This low temperatureization also is that productivity that the shortening for the engaging process time brings improves and the problem that requires.
The fusing point of soldering self is by the decision formed of the material that uses, but the histological structure and the surface state of the brazing layer of the fusion of soldering before being fused are arranged.Particularly, use as the installation of semiconductor chip in the state of oxidation on surface under the situation of soldering of small quantity, bring bigger influence, can not carry out firm joint to engagement characteristics.
In no Pb soldering, though making lit-par-lit structure so that above-mentioned Sn etc. easily the metal of oxidation be not exposed under the lip-deep situation because also diffusion easily of metallic atom at room temperature, infringement engages the reliability of self so can produce space etc.Make in the method for soldering moment fusion, the so-called flash of light heating bonding method at light sources such as using Halogen lamp LED, the lip-deep Au that must will be located at brazing layer for anti-oxidation heats fully and makes its fusion and absorb in the brazing layer, and the bad problems such as load increase to semiconductor element own and that bring for the unnecessary heating more than the fusing point and the prolongation of heating time that engage are arranged.In the prior art,, the technology of installing after the oxide-film reduction removed is arranged in vacuum reduction atmosphere in order to improve this soldering fusion property, but because device becomes large-scale, so manufacturing cost uprises.
As mentioned above, for the desired soldering fusion of no Pb soldering property, the problem of oxidation technology self obstruction as the soldering fusion property raising of original purpose that prevent for the braze surface that improves fusion property arranged.
The 2nd purpose of the present invention is in view of the above problems, a kind of Submount of soldering protective layer that possesses the different a plurality of brazing layers of fusing point and prevent the oxidation of brazing layer is provided.
And then, as the soldering of Au-Sn eutectic, using under the situation of lead-free more dystectic soldering, in order to prevent the destruction of the semiconductor element chip that heat is brought, under the low heating-up temperature of trying one's best, semiconductor element chip is engaged mostly.Therefore, the undesirable condition that the destruction of above-mentioned semiconductor element chip is brought takes place easily, its improvement becomes problem.Bad as the joint that the fluctuation to above-mentioned heating-up temperature brings, promptly engage one of reason that deviation exerts an influence, be the melting temperature scope of brazing layer.
In view of the above problems, the 3rd purpose of the present invention is Submount and the manufacture method thereof that the brazing layer that possesses melting temperature wider range is provided for the joint deviation of eliminating Submount.
In the Submount of conventional art, since between Submount substrate and the brazing layer and the bond strength between electrode layer and the brazing layer reduce, if, then need unnecessary operations such as the formation of adhesion layer and Butut thereof between them so deal with by adhesion layer is set.Therefore, can besides spend manufacturing cost.In addition, owing in adhesion layer, use noble metals more, so the problem of the other places cost material cost of having a surplus.In the operation that the pattern of electrode layer forms, because the Submount substrate surface directly contacts with developer solution, if so also the difference substrate surface of with good grounds substrate material forms the dysgenic problem of bringing then can for brazing layer afterwards because of roughening such as corrosion.
The present invention in view of the above problems, the 4th purpose provides a kind of good Submount and manufacture method thereof of respectively connecting airtight property that constitutes each layer of Submount, particularly Submount substrate and electrode layer, electrode layer and brazing layer.
And then, in order to prevent the poor short circuit of the semiconductor element that having climbed of brazing layer brought, need carry out the groove processing of Submount substrate etc., so the problem that has process number to increase.
In view of this problem, the 5th purpose of the present invention provides a kind of when possessing the element that carries at the subtend Submount and carrying out soldered joint, melting temperature wider range and can reduce Submount and the manufacture method thereof of brazing layer to the brazing layer of having climbed of element.
In order to reach above-mentioned the 1st purpose of the present invention, present inventors study repeatedly with keen determination, the result, obtained in Submount, with semiconductor device and Submount when not using the soldered joint of solder flux, the surface roughness of electrode layer brings the understanding of influence can for the wettability of soldering, thereby has finished the present invention.
The Submount that is used for reaching the 1st invention of above-mentioned the 1st purpose comprises the lip-deep substrate protective layer that is formed on the Submount substrate, be formed on the electrode layer on the substrate protective layer and be formed on brazing layer on the electrode layer; the mean roughness of electrode layer surface is lower than 0.1 μ m, preferably is lower than 0.05 μ m.
The surface average roughness of Submount substrate and the mean roughness of electrode layer surface are similarly and are lower than 0.1 μ m, preferably are lower than 0.05 μ m.Do not have the surface average roughness of the Submount substrate of configured electrodes layer to be similarly and be lower than 0.1 μ m, preferably be lower than 0.05 μ m.
There is not the absolute value of difference of the surface average roughness of the Submount substrate surface of configured electrodes layer and electrode layer surface to be preferably below the 0.02 μ m.The Submount substrate is made of nitride-based pottery, especially preferably is made of aluminium nitride.Substrate protective layer or electrode layer preferably contain any metallic element in two or more at least gold, platinum, silver, copper, iron, aluminium, titanium, tungsten, nickel and the molybdenum.
According to said structure, the surface roughness of the electrode layer by making Submount is for being lower than 0.1 μ m, and the wettability of brazing layer improves, and fluxless ground between brazing layer and the semiconductor device can be engaged securely.That is, the brazing layer of the bottom of semiconductor device can be made uniform layer very close to each other, and can make its thickness is that minimal brazing layer engages.Thus, can access the less Submount of thermal resistance when having carried semiconductor device, diminish, can improve the performance and the life-span of semiconductor device so used the temperature of the semiconductor device of Submount of the present invention to rise.
And then, the method of the present invention that is used for reaching above-mentioned the 1st purpose is to comprise the lip-deep substrate protective layer that is formed on the Submount substrate, be formed on the electrode layer on the substrate protective layer and be formed on the manufacture method of the Submount of the brazing layer on the electrode layer, it is characterized in that, comprise: will be different with the metallic element that uses in electrode layer or brazing layer a kind or multiple metal cover on the whole surface of Submount substrate the operation as the substrate protective layer; With behind the electrode layer and brazing layer that form predetermined pattern on the substrate protective layer, the operation that will not have the substrate protective layer of the part of configured electrodes layer and brazing layer to remove.
The whole lip-deep metal that covers the Submount substrate as the substrate protective layer is different with the metal of above-mentioned electrode layer, and also can or multiplely constitute by a kind in titanium, platinum, nickel, tungsten and the molybdenum.
According to above-mentioned manufacture method, can make to high finished product rate the good Submount of wettability of brazing layer.
Then, present inventors are in order to reach above-mentioned the 2nd purpose, for the fusion of above-mentioned brazing layer, are conceived to the fusing point of brazing layer and anti-surface oxidation and have carried out research with keen determination.The result has obtained following understanding: by made fusion more than the soldering in two stages before rising to the temperature of joint; can realize improving the fusion of brazing layer itself simultaneously and the soldering protective layer that is provided with for the most surperficial oxidation that prevents brazing layer is fused easily, thereby expect the present invention.
The Submount that is used for reaching the 2nd invention of above-mentioned the 2nd purpose is characterised in that, comprises: the Submount substrate that is used for semiconductor element mounted thereon; Brazing layer is provided on the surface of Submount substrate; The soldering protective layer is provided on brazing layer the most surperficial; Making brazing layer is the different two or more at least layer of fusing point.
Brazing layer comprises the two or more element among Ag, Au, Cu, Zn, Ni, In, Ga, Bi, Al and the Sn, preferably comprises any or Ag, Au and Sn among Au and Sn, Ag and the Sn.
According to said structure, the fusion multistage ground of Submount of the present invention soldering when the heating fusion carries out, and can relax the variation of melting point that fusion is residual and the composition variation brings of soldering protective layer etc., so can improve the fusion of soldering.
In said structure, preferably, brazing layer is made of two-layer, and the one deck in two-layer is made of the brazing layer that the element set of Au becomes more than 50%, and another layer is made up of the element of Au and is lower than 50% brazing layer and constitutes simultaneously.Perhaps, the one deck in two-layer is made of the brazing layer that the element set of Au and Ag becomes more than 50%, and another layer is made up of the element of Au and Ag and is lower than 50% brazing layer and constitutes simultaneously.Less and make fusing point lower by the Au amount that makes the one deck in the brazing layer that in Submount, uses, can realize cost degradation.
The soldering protective layer also can be by noble metal, particularly be made of Au.Thus, the fusion multistage ground of the soldering that is formed on the Submount is carried out, and the noble metal of the superiors that can be by being formed at brazing layer suppresses the oxidation on brazing layer surface lower, can access good soldering fusion property.
In order to reach above-mentioned the 3rd purpose, present inventors are conceived to the melt temperature scope of brazing layer and have carried out research with keen determination.In the past, conduct solid existence completely under the temperature below the so-called eutectic point of the alloy brazed layer of eutectic composition in the poised state phasor, by it is warmed up to eutectic temperature, brazing layer just begins to become liquid phase state, and generation can engage with the counterdiffusion mutually of the electrode of semiconductor element.That is, the temperature that begins to fuse from brazing layer to the scope of the temperature that becomes liquid phase fully, be that the melting temperature scope is 0 ℃.Therefore, obtained following understanding: in the melting temperature of brazing layer, be to add under the situation that heat engages with minimal more than the fusing point, if than melt temperature even reduce a bit, brazing layer also can be solid phase, can not engage with semiconductor element chip fully, thereby expect the present invention.
The Submount that is used for reaching the 3rd invention of above-mentioned the 3rd purpose is characterised in that, comprises on the surface that is formed on the Submount substrate and is used for the brazing layer of bond semiconductor element; This brazing layer is arranged to not be that it constitutes the composition of the eutectic composition of element, is eutectic composition composition in addition.
Fusion at above-mentioned brazing layer begins temperature and also can have temperature difference between the melting temperature fully.Preferably, this temperature difference is more than 10 ℃.In the differential thermal behavior with this brazing layer heating the time, show that at first the temperature of differential heat fluctuation is bigger than 10 ℃ with the difference of the temperature of the differential heat fluctuation end of representing fusion fully.In addition, preferably, between the temperature that the initial differential heat fluctuation that shows the temperature of differential heat fluctuation and represent to fuse fully finishes, has the differential thermal peak point more than 2.The material that constitutes brazing layer also can be to comprise at least a above metal material among Au, Ag, Cu, Zn, In, Bi, Fe, Pb, Ti, Al, Sb and the Ni and the alloy of Sn.Preferably, the material of formation Submount substrate is any in aluminium nitride, carborundum and the silicon.
Depart from the composition of eutectic composition by making consisting of of brazing layer, thereby owing to be not eutectic composition, so the melt temperature expanded range that can make soldering is for to begin temperature to the fusion end temp of being represented by liquidus temperature from the fusion of being represented by solidus temperature.At this moment,, just become the state that in brazing layer, contains liquid phase,, can form the joint of the function that is enough to bring into play Submount so when semiconductor device is engaged, the counterdiffusion mutually with the electrode of semiconductor element takes place so long as fusion begins more than the temperature.
The manufacture method that is used for reaching the Submount of above-mentioned the 3rd purpose of the present invention is characterised in that, having by constituting element decision is not that the brazing layer of forming of eutectic composition covers under the situation on single face or the two sides, and every kind of evaporation that constitutes element by brazing layer comes the film forming brazing layer.
Has the Submount of forming uniform brazing layer by having the brazing layer film forming of the composition that is not eutectic composition with for example 2 yuan of while evaporations, and can making accurately.
In order to reach above-mentioned the 4th purpose, present inventors have obtained following understanding: in Submount, particularly the Submount substrate brings influence can for the adhesion strength of Submount substrate and electrode with the existence of the carbon compound on the surface of the adhesion strength that forms each layer thereon, for example Submount substrate, thereby has finished the present invention.
The Submount that is used for reaching the 4th invention of above-mentioned the 4th purpose is characterised in that, comprises: the Submount substrate; Electrode layer is formed on the surface of Submount substrate; Brazing layer is formed on the electrode layer; Be formed between Submount substrate and the electrode layer near interface with and/or the concentration of carbon that is formed at the near interface between electrode layer and the brazing layer be 1 * 10 20Atoms/cm 3Below.
The Submount of another structure of the present invention is characterised in that, comprises: the Submount substrate; The substrate protective layer is formed on the Submount substrate; Electrode layer is formed on the substrate protective layer; Brazing layer is formed on the electrode layer; At least more than one the concentration of carbon of near interface that is formed among the near interface that contacts with each other of Submount substrate, substrate protective layer, electrode layer and brazing layer is 1 * 10 20Atoms/cm 3Below.
The Submount of another structure more of the present invention is characterised in that, comprises: the Submount substrate; The substrate protective layer is formed on the Submount substrate; Electrode layer is formed on the substrate protective layer; Adhesion layer is formed on the electrode layer; Brazing layer is formed on the adhesion layer; At least more than one the concentration of carbon of near interface that is formed among the near interface of near interface, adhesion layer and brazing layer of near interface, electrode layer and adhesion layer of near interface, substrate protective layer and electrode layer of Submount substrate and substrate protective layer is 1 * 10 20Atoms/cm 3Below.
Preferably, also be formed with the soldering protective layer on brazing layer, making the concentration of carbon that is formed at the near interface between brazing layer and the soldering protective layer is 1 * 10 20Atoms/cm 3Below.The Submount substrate preferably is made of nitride-based pottery.Nitride-based pottery preferably is made of aluminium nitride.
By making the concentration of carbon that is present in Submount substrate that constitutes Submount and the near interface that forms each layer thereon is 1 * 10 20Atoms/cm 3Below, can improve on the Submount substrate and the adhesion strength of electrode layer or other each layers between adhesion strength, Submount can be engaged securely with semiconductor device.Therefore, use the temperature rising of the semiconductor device of Submount of the present invention to diminish, can improve the performance and the life-span of semiconductor device.
The method that is used for reaching the manufacturing Submount of above-mentioned the 4th purpose is characterised in that, to the region surface of the formation electrode layer of Submount substrate with and/or the region surface of the formation brazing layer of above-mentioned electrode layer implement to reduce the surface clean operation of concentration of carbon.
Preferably, also be included in the operation that forms the substrate protective layer between Submount substrate and the electrode layer, before the formation of substrate protective layer and/or electrode layer, the surface clean operation that enforcement reduces the concentration of carbon of the region surface that forms it.Preferably, also be included in the operation that forms adhesion layer between electrode layer and the brazing layer, before the formation of electrode layer and/or brazing layer, the surface clean operation that enforcement reduces the concentration of carbon of the region surface that forms it.Preferably, also be included in the operation that forms the soldering protective layer on the brazing layer, before the formation of soldering protective layer, implement the surface clean operation of the concentration of carbon on minimizing brazing layer surface.Above-mentioned each surface clean is undertaken by ultraviolet and ozone facture or plasma incineration.
According to above-mentioned manufacture method, can make the adhesion of Submount substrate and electrode layer well or be formed at the Submount of the good adhesion between each layer on the Submount substrate with low-cost and rate of finished products.
The Submount that is used for reaching the 5th invention of above-mentioned the 5th purpose is characterised in that, the ratio of components of element that constitutes the brazing layer of bond semiconductor element changes on the depth direction of brazing layer.Change on depth direction by the ratio of components that makes brazing layer, the melting temperature expanded range that can make soldering to from the melting temperature that obtains by forming of brazing layer surface to the melting temperature that obtains by forming of the brazing layer back side.So long as more than the melting temperature on brazing layer surface, just become the state that in brazing layer, contains liquid phase,, can form the joint of the function that is enough to play Submount so when the bond semiconductor element, the counterdiffusion mutually with the electrode of semiconductor element takes place.And then, can reduce the height of having climbed of the brazing layer that when the bond semiconductor element, produces.
Preferably, the ratio of components of brazing layer changes on the depth direction of brazing layer, so that the fusing point of the face side of bond semiconductor element is lower than the fusing point of its rear side.Preferably, the fusing point of the face side of brazing layer is bigger than 10 ℃ with the difference of the fusing point of rear side.The material that constitutes brazing layer is to comprise at least a above metal material among Au, Ag, Cu, Zn, In, Bi, Fe, Pb, Ti, Al, Sb and the Ni and the alloy of Sn.The material that constitutes the Submount substrate is any in aluminium nitride, carborundum and the silicon preferably.
According to said structure, can reduce the height of having climbed of the brazing layer that when the bond semiconductor element, produces.
And then, the manufacture method that is used for reaching the Submount of the present invention of above-mentioned the 5th purpose is characterised in that, to constitute brazing layer that element constitutes and cover on the Submount substrate and when being bonded on semiconductor element on the brazing layer by multiple, form brazing layer in the following manner: every kind by the evaporation brazing layer constitutes element, so that ratio of components changes on the depth direction of brazing layer.
By for example being formed on the brazing layer that ratio of components changes on the depth direction, can make Submount accurately with brazing layer that ratio of components changes on depth direction with 2 yuan of while evaporations.
According to the 1st invention, the wettability of brazing layer improves, and can fluxless ground engages securely between brazing layer and the semiconductor device.Thereby, can access the less Submount of thermal resistance when having carried semiconductor device.Therefore, use the temperature rising of the semiconductor device of Submount of the present invention to diminish, can improve the performance and the life-span of semiconductor device.In addition, owing to can make Submount,, can make at low cost so production is higher by lift-off method.
According to the 2nd invention,,, can reduce junction temperature so the fusion of fusion beginning temperature, soldering protective layer begins temperature, the equal step-down of melting temperature fully because brazing layer is made of the different a plurality of brazing layers of fusing point and its soldering protective layer.That is, by before rising to junction temperature, make soldering be divided into two stages with on fuse, can provide and can realize improving the fusion of brazing layer itself simultaneously and make for the oxidation that prevents the surface antioxidation coating that the forms Submount of fusion easily.
According to the 3rd invention, by making the consisting of of brazing layer by forming beyond the eutectic composition that constitutes element decision of brazing layer, and the fusion that has brazing layer begins the poor of temperature and complete melting temperature, can enlarge with the semiconductor element that engages by brazing layer between the junction temperature scope.Thereby, can access and when having carried semiconductor element, engage the less Submount of deviation.
According to the 4th invention, the Submount that the adhesion of Submount substrate and electrode layer can be provided and be formed at the good adhesion between each layer on the Submount substrate.In addition, even particularly seldom also can improve adhesiveness, so can realize the shortening of manufacturing process and the reduction of manufacturing cost with noble metal.Thereby, can make Submount well, at low cost by production.
According to the 5th invention, by ratio of components is changed on the depth direction of brazing layer, it is poor to be provided with between the melting temperature at the melting temperature on brazing layer surface and the brazing layer back side, can enlarge with the semiconductor element that engages by brazing layer between the junction temperature scope.Thereby, it is less to engage deviation when having carried semiconductor element, and by in the melting temperature scope, at random setting the heating-up temperature of brazing layer, have the fusion part that at random to regulate brazing layer, be the effect of amount of liquid phase, climbed highly less Submount so can access to the soldering of the semiconductor element that engages.Like this, can prevent from effectively to have climbed incidental poor short circuit when highly becoming big in soldering.
Description of drawings
Fig. 1 is the cutaway view of structure of schematically representing the Submount of the 1st execution mode of the present invention.
Fig. 2 is a cutaway view of schematically representing semiconductor device is carried the structure on the Submount of Fig. 1.
Fig. 3 is the figure that the band of expression embodiment 1,2 and comparative example 1,2 is peeled off rate.
Fig. 4 is (A) optical microscope image of observing from above of the Submount after the band disbonded test of embodiment 1,2 and (B) its key diagram.
Fig. 5 is (A) optical microscope image of observing from above of the Submount after lift-off led in the band disbonded test of comparative example 1,2 and (B) its key diagram.
Fig. 6 is the cutaway view of structure of schematically representing the Submount of the 2nd execution mode of the present invention.
Fig. 7 is the cutaway view of schematically representing the structure of mounting semiconductor element on the Submount of Fig. 6.
Fig. 8 is the cutaway view of structure of schematically representing the Submount of the 3rd execution mode of the present invention.
Fig. 9 is the phantom of the slicing process in the manufacture method of the schematically Submount of presentation graphs 8.
Figure 10 is the phantom of the slicing process (dicing step) before cutting apart in the manufacture method of the schematically Submount of presentation graphs 8.
Figure 11 is result's the figure of the dsc measurement of expression embodiment 5.
Figure 12 is result's the figure of the dsc measurement of expression comparative example 5.
Figure 13 be in embodiment 5, (A) optical microscope image of observing of the Submount of band after the disbonded test and (B) its key diagram from above.
Figure 14 is (A) optical microscope image of observing from above of the Submount in comparative example 5, after band is lift-off led in the disbonded test and (B) its key diagram.
Figure 15 is the cutaway view of structure of schematically representing the Submount of the 4th execution mode of the present invention.
Figure 16 is the cutaway view of structure of Submount of schematically representing the variation of the 4th execution mode.
Figure 17 is the cutaway view of structure of Submount of schematically representing another variation of the 4th execution mode.
Figure 18 is the cutaway view of structure of Submount of schematically representing another variation again of the 4th execution mode.
Figure 19 is a cutaway view of schematically representing semiconductor device is carried the structure on the Submount of Figure 16.
Figure 20 represents the result with the concentration of carbon ratio of the electrode layer surface before the formation brazing layer of ESCA measurement embodiment 6,7 and comparative example 6.
To be expression measure the result's that the concentration of carbon with respect to the depth direction of brazing layer distributes figure for the sample of embodiment 6 to Figure 21 with SIMS.
To be expression measure result's the figure of concentration of carbon of the near interface of the electrode layer of embodiment 6～8 and comparative example 6 and brazing layer with SIMS to Figure 22.
Figure 23 is the figure that the band of expression embodiment 6～8 and comparative example 6 is peeled off rate.
Figure 24 (A), Figure 24 (B) are respectively the optical microscope image of observing from above and its key diagrams that the Submount of making has been carried out the Submount after the band disbonded test in embodiment 6.
Figure 25 (A), Figure 25 (B) are respectively the optical microscope image of observing from above and its key diagrams of the result that the Submount of making has carried out the band disbonded test promptly being peeled off the Submount behind the brazing layer a in comparative example 6.
Figure 26 is the cutaway view of structure of schematically representing the Submount of the 5th execution mode of the present invention.
Figure 27 is the figure that represents that schematically the fusing point of the brazing layer of Figure 26 distributes.
Figure 28 is the figure that represents that schematically the composition of the brazing layer of Figure 26 distributes.
Figure 29 is the figure of a part that schematically represents the equilibrium state diagram of brazing layer.
Figure 30 is the cutaway view of schematically representing the structure of mounting semiconductor element on the Submount of Figure 26.
Figure 31 is a partial sectional view of schematically representing the slicing process in the manufacture method of Submount of Figure 26.
Figure 32 is the cutaway view of having climbed height h of schematically representing brazing layer.
Label declaration
1,10,20,30,40,42,44,50: Submount
2,12,22,32,52: the Submount substrate
3 (3a, 3b), 35 (35a, 35b): substrate protective layer
4 (4a, 4b), 15,33 (33a, 33b): electrode layer
5 (5a, 5b), 13,34 (34a, 34b): brazing layer
5c, 24a, 34c: the zone of having peeled off brazing layer
5d, 24b: the brazing layer of peeling off
7: semiconductor device (light-emitting diode)
14,38: the soldering protective layer
23,53: the electrode layer of element mounting side
24,54: the brazing layer of element mounting side
25,55: the electrode layer on heat dissipation metal side
26,56: the brazing layer on heat dissipation metal side
31,51: the Submount substrate before cutting apart
36 (36a, 36b): adhesion layer
37,57: slice
Embodiment
Below, describe with reference to the structure of accompanying drawing the Submount of embodiments of the present invention.
Fig. 1 is a cutaway view of schematically representing the structure of Submount of the present invention.As shown in Figure 1; in Submount 1 of the present invention; on the single face and/or two sides of Submount substrate 2; be formed with electrode layer 4 across the substrate protective layer 3 that is formed on the substrate surface in part or all the mode that covers Submount substrate 2, on these electrode layer 4 surfaces, be formed with brazing layer 5.The position of the formation brazing layer 5 of electrode layer 4 both can be whole under the situation of light-emitting diode etc., also can be electrode pattern.In addition, also can on the part of electrode layer 4, connect gold thread and form circuit.
As Submount substrate 2, can use the higher aluminium nitride of pyroconductivity (AlN), carborundum (SiC), diamond IIa etc.In addition, on the side of Submount substrate 2, also can form with above-mentioned same electrode layer and the upper surface of Submount substrate 2 is electrically connected with lower surface.
Substrate protective layer 3 is when making Submount 1 of the present invention; covering the whole lip-deep layer of Submount substrate 2 at first, is to be provided with greatly because of etching etc. becomes the surface roughness of Submount substrate 2 in order to prevent in the operation when forming the pattern of electrode layer 4 and brazing layer 5.This substrate protective layer 3 be preferably with the good adhesion of Submount substrate 2, with electrode layer described later 4 different metal, can use among titanium (Ti), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), silver (Ag), copper (Cu), iron (Fe), aluminium (Al) and golden (Au) any.In addition, also can contain these two or more metals.For example, can Ti and Pt is stacked and be formed on the Submount substrate 2.
As electrode layer 4, be preferably metal, can use in gold, platinum, silver, copper, iron, aluminium, titanium, the tungsten any especially.In addition, also can contain these two or more metals.For example, can Ag and Au is stacked and be formed on the substrate protective layer 3.
For brazing layer 5, be preferably do not use lead (Pb), promptly do not have a Pb soldering.And then, can preferably use the soldering that contains the two or more element in silver, gold, copper, zinc (Zn), nickel (Ni), indium (In), gallium (Ga), bismuth (Bi), aluminium, the tin (Sn).
Between electrode layer 4 and brazing layer 5, also can dispose adhesion layer (diagram is omitted) in order to improve the adhesiveness when forming.As adhesion layer, titanium preferably.
In order to improve the wettability of brazing layer 5a, the surface roughness of electrode layer 4 (Ra) is preferably and is lower than 0.1 μ m, is preferably especially to be lower than 0.05 μ m.If making the surface roughness of electrode layer 4 is more than the 0.1 μ m, the wettability variation of brazing layer 5a then, can engage bad, so not preferred.
The surface roughness of Submount substrate 2 (Ra) is also same with the surface roughness of electrode layer 4, is preferably to be lower than 0.1 μ m, is preferably especially to be lower than 0.05 μ m.This is because if Submount substrate 2 is also equal with the surface roughness of electrode layer 4, then can improve the wettability on the surface of electrode layer 4.
In addition, on Submount substrate 2, form the pattern of the metal level of substrate protective layer 3 sometimes by etching by photoetching process.If the surface roughness of Submount substrate 2 becomes big when this etching, the surface roughness that then is formed on the electrode layer 4 on the substrate protective layer 3 thus also becomes greatly, so not preferred.Thereby, for the surface roughness that makes electrode layer 4 is lower than 0.1 μ m, do not have the Submount substrate 2 of configured electrodes layer 4 surface roughness (Ra), be that mean roughness (Ra) that Submount substrate 2 is exposed to lip-deep part is preferably equally and is lower than 0.1 μ m, more preferably be lower than 0.05 μ m.If making the surface roughness of Submount substrate 2 is more than the 0.1 μ m, then the surface roughness of electrode layer 4 becomes more than the 0.1 μ m easily, is not preferred.
And then, there is not the absolute value of difference of surface average roughness (Ra) on the surface of the surface of Submount substrate 2 configured electrodes layer 4, that promptly expose and electrode layer 4 to be preferably below the 0.02 μ m.Under the absolute value of the difference of surface average roughness (Ra) was situation more than 0.02, electrode layer 4 reduced with the adhesiveness of Submount substrate 2, so be not preferred.
Then, the installation to the semiconductor device that carries out with Submount of the present invention describes.Fig. 2 is a cutaway view of schematically representing semiconductor device is carried the structure on Submount of the present invention.As shown in Figure 2, on Submount 1 of the present invention, semiconductor device 7 can carry out soldered joint by brazing layer 5a fluxless ground.Here, semiconductor element comprise the such light-emitting component of laser diode or light-emitting diode, diode, high frequency amplify and switch in the such active element of the transistor that uses or thyristor, integrated circuit etc.
The feature of Submount 1 of the present invention is, the mean roughness that makes Submount substrate 2 surfaces is for being lower than 0.1 μ m, being preferably and being lower than 0.05 μ m, and the surface roughness that makes the electrode layer 4 that forms in the above is for being lower than 0.1 μ m.Therefore, the wettability of brazing layer 5a improves, with the zygosity raising of semiconductor device 7.That is, can make the brazing layer 5a of the bottom of semiconductor device 7 become uniform layer very close to each other.And can make its thickness is that minimal brazing layer engages.According to the Submount 1 of this structure, can form the less joint of thermal resistance.Therefore, use the thermal resistance of the semiconductor device of Submount 1 of the present invention to diminish, the performance of semiconductor device and life-span improve.
Below the manufacture method of Submount of the present invention is described.
Prepare Submount substrate 2, grinding is carried out by grinding (lapping) device in its two sides.Re-use polishing (polishing) device and wait and implement fine finishining and grind, the mean roughness (Ra) that makes the surface of Submount substrate 2 is for being lower than 0.1 μ m, more preferably being lower than 0.05 μ m.
Then, the Submount substrate after grinding 2 is cleaned and carry out cleaning surfacesization, form substrate protective layer 3a on the whole on the surface of Submount substrate 2.This substrate protective layer 3a can form by the vapour deposition method that has used vacuum deposition apparatus or sputtering unit.
Then, carry out Butut by photoetching process.Particularly, use surface that spin coater is coated on Submount substrate 2 equably with resist on the whole, the baking of stipulating by oven then utilizes the mask alignment device to carry out the contact exposure of gamma line.After exposure, the developer solution by the tetramethyl amine will become the resist dissolving of the part of electrode layer 4a, and substrate protective layer 3a is exposed.
Then,, utilize acetone that resist is all dissolved, by lifting, form the electrode layer 4a of regulation thus from the metal beyond the electrode layer 4a is removed by the metal of evaporations such as vacuum deposition apparatus as electrode layer 4a.Then, same with above-mentioned electrode layer 4a, utilize photoetching process and vacuum deposition apparatus lift from, on the part of the lip-deep electrode layer 4a that is formed at Submount substrate 2, form brazing layer 5a.
Then, the lip-deep substrate protective layer 3a that is exposed to Submount substrate 2 is removed by etching, the surface of Submount substrate 2 is exposed.At last, the Submount substrate 2 that obtains is utilized slicing device etc. be divided into the size of the Submount 1 of regulation.
The feature of the manufacture method of Submount 1 of the present invention is, whole of Submount substrate 2 covered with substrate protective layer 3, prevented the surperficial roughening of the Submount substrate 2 when carrying out the Butut of electrode layer 4 and brazing layer 5 by lift-off method effectively.Therefore, the mean roughness on the surface by making Submount substrate 2 is for being lower than 0.1 μ m, being preferably and being lower than 0.05 μ m especially, the surface roughness that can make formation electrode layer 4 in the above can improve the wettability of brazing layer 5 for being lower than 0.1 μ m, being in particular and being lower than 0.05 μ m.According to the manufacture method of Submount 1 of the present invention, can make to high finished product rate the good Submount of soldered joint with semiconductor device 7.
Embodiment 1
Below, illustrate in greater detail the present invention based on embodiment.
At first, the manufacture method to Submount describes.
The 55mm that will have high thermal conductivity (230W/mK) is square, grinding is carried out by lapping device in the two sides of the sintered aluminum nitride substrate 2 of thickness 0.3mm, utilizes burnishing device to implement fine finishining and grinds, and the mean roughness (Ra) that makes aluminium nitride substrate 2 is 0.07 μ m.
Aluminium nitride substrate after grinding 2 is cleaned and make cleaning surfacesization, on the whole surface of this substrate 2, pile up the substrate protective layer 3a that constitutes by titanium of 0.05 μ m by vacuum deposition apparatus.
Then, in order to carry out photolithographic Butut, utilize spin coater equably behind the painting erosion resistant agent substrate surface integral body of having piled up substrate protective layer 3a,, utilize the mask alignment device to carry out the contact exposure of gamma line by the baking that oven is stipulated.With the mask design of exposure usefulness be, can be with the square Submount size of 1mm 2500 of Bututs simultaneously.After the exposure, will form the resist dissolving of the part of electrode layer 4a with tetramethyl amine developer solution, substrate protective layer 3a is exposed.
Then, use the vacuum deposition apparatus gold evaporation on the whole, use acetone that resist is all dissolved at substrate surface, thus with the Au beyond the electrode layer 4a by lifting from removing, form the electrode layer 4a of regulation.The thickness of electrode layer 4a is 0.1 μ m, and it is square that its size is that the two sides is 800 μ m.
Same with the forming method of electrode layer 4a, utilize photoetching process and vacuum deposition apparatus, on a part that is formed at aluminium nitride substrate 2 lip-deep electrode layer 4a, form the brazing layer 5a of 5 μ m.The composition of brazing layer 5a is Ag and Sn.Brazing layer 5a is of a size of, and the semiconductor element composition surface is that 400 μ m are square, the Submount composition surface is that 800 μ m are square.
After the formation of brazing layer 5a, the substrate protective layer 3a that will expose from the teeth outwards removes with the diluted hydrofluoric acid etching, and the surface of aluminium nitride substrate 2 is exposed.At last, utilize slicing device to make the size of Submount 1 aluminium nitride substrate 2 that obtains, it is square to be cut to 1mm, has made the Submount 1 of embodiment 1.
Embodiment 2
Except the mean roughness (Ra) that makes aluminium nitride substrate 2 is 0.04 μ m, similarly to Example 1, made the Submount 1 of embodiment 2.
Then, comparative example is described.
(comparative example 1)
Except the mean roughness (Ra) that makes Submount substrate 2 surfaces is 0.13 μ m, use and embodiment 1 and 2 identical manufacture methods, made the Submount of comparative example 1.
(comparative example 2)
After being 0.07 μ m at the mean roughness that makes Submount aluminium nitride substrate 2 surfaces (Ra), the evaporation condition of change electrode layer 4a and intentionally making beyond the surperficial roughening of electrode layer 4a, with with embodiment 1 and 2 identical manufacture methods, made the Submount of comparative example 2.
Each characteristic to the Submount that obtains in the foregoing description and comparative example describes.
Measure the roughness (Ra) on the surface of the surface of Submount substrate 2 of the Submount 1 in embodiment and comparative example, make and electrode layer 4a by the contact pin type roughmeter.Table 1 is the table of each characteristic of expression embodiment and comparative example.As shown in Table 1, the mean roughness (Ra) on Submount substrate 2 surfaces is respectively 0.07 μ m, 0.04 μ m in embodiment 1 and 2, and the surface roughness of electrode layer 4a is respectively 0.06 μ m, 0.03 μ m.With respect to this, the mean roughness on the surface of comparative example 1 and 2 Submount substrate 2 is respectively 0.13 μ m, 0.07 μ m, and the surface roughness of electrode layer 4a is respectively 0.12 μ m, 0.18 μ m.The mean roughness (Ra) on Submount substrate 2 surfaces is below the 0.07 μ m in an embodiment as can be known, and this value of comparative example is about 0.1 μ m.Equally, the mean roughness on electrode layer 4a surface (Ra) is below the 0.06 μ m in an embodiment as can be known, and this value of comparative example is bigger than 0.1 μ m.
[table 1]
Substrate surface roughness (Ra) (μ m) Electrode surface roughness (Ra) (μ m) Soak into autgmentability Peel off state
Embodiment
1 ??0.07 ??0.06 ??1.10 Nothing is peeled off
Embodiment 2 ??0.04 ??0.03 ??1.15 Nothing is peeled off
Comparative example 1 ??0.13 ??0.12 ??1.05 Between electrode layer and brazing layer, peel off
Comparative example 2 ??0.07 ??0.18 ??1.01 Between electrode layer and brazing layer, peel off
The evaluation of the infiltration autgmentability when then, carrying out soldered joint.So-called being somebody's turn to do soaked into autgmentability, is by before and after the fusion of brazing layer 5a, the characteristic that the area change of the brazing layer 5a when observing above brazing layer 5a (the area ratios of front and back) is estimated.Wettability is good more, and the area after the soldering fusion is big more, and the infiltration autgmentability is good more.Particularly, infiltrating evaluation is by with the bottom surface heating of the correct Halogen lamp LED heater of adjustment with Submount 1, brazing layer 5a is fused estimate it diffusible.
As shown in Table 1, embodiment 1 and 2 infiltration autgmentability demonstrate 1.10 and 1.15 this characteristics more than 1.10, and with respect to this, comparative example 1 and this value of 2 are 1.05 and 1.01.Hence one can see that, and the infiltration autgmentability of the brazing layer 5a of embodiment is bigger than comparative example.Under the situation of embodiment,, become the greatly result more than 1.1 so obtain soaking into autgmentability because the surface roughness of electrode layer 4a is less.
Then, Submount and soldered joint semiconductor device to the foregoing description 1,2 and comparative example 1,2 describes.
For the relation of the infiltration autgmentability that makes soldered joint intensity and soldering becomes clear, make make the brazing layer 5a fusion of Submount 1 by heater after, from top configuring semiconductor element 7, the sample that behind joint, cools off.Carry out by estimating with the band disbonded test of table and the observation of peeling off state.Here, use light-emitting diode as semiconductor element 7, sample number all is each 100 in embodiment and comparative example.
Fig. 3 is the figure that the band of expression embodiment 1,2 and comparative example 1,2 is peeled off rate.In the drawings, the longitudinal axis is that band is peeled off rate (%).As seen from the figure, even all band is peeled off peeling off of light-emitting diode 7 do not taken place yet in embodiment 1 and 2.But comparative example 1 and 2 band are peeled off rate and are respectively 8%, 23%, can judge that light-emitting diode 7 peels off easily.The position that the band of comparative example is peeled off all is between brazing layer 5a and the electrode layer 4a, and the engaging force between brazing layer 5a under the situation of comparative example and electrode layer 4a reduces as can be known.
Fig. 4 is (A) optical microscope image of observing from above of the Submount 1 after the band disbonded test of embodiment 1,2 and (B) its key diagram.Multiplying power is 181 times.As shown in Figure 4, engaging on the brazing layer 5a that is formed on the electrode layer 4a that is made of gold has light-emitting diode 7, does not peel off.
Fig. 5 (A), Fig. 5 (B) are respectively the optical microscope image of observing from above and its key diagrams of the Submount 1 after light-emitting diode 7 is peeled off in the band disbonded test of comparative example 1,2.Multiplying power is 181 times.As shown in Figure 5, observed and be formed at regional 5c that the brazing layer 5a on the electrode layer 4a that is made of gold peels off and the brazing layer 5d that peels off, taken place to peel off between electrode layer 4a and brazing layer 5a, light-emitting diode 7 is peeled off as a result.
According to the foregoing description 1,2 and comparative example 1,2, in the Submount 1 that carries semiconductor device 7, by regulating the surface roughness of Submount 2 and electrode layer 4a, with the engaging of semiconductor device 7 in, realized the high wettability of brazing layer 5a, can not use solder flux and semiconductor device 7 is engaged securely with brazing layer 5a.
Then, the 2nd execution mode of the present invention is described.
Fig. 6 is the cutaway view of structure of schematically representing the Submount of relevant the 2nd execution mode.In Submount shown in Figure 6 10, on the two sides or single face of Submount substrate 12, formed brazing layer 13 in part or all the mode that covers Submount substrate 12.Brazing layer 13 is divided into brazing layer 13A and brazing layer 13B, forms different respectively.Brazing layer 13A and brazing layer 13B are because composition is different, so its fusing point is also different.On brazing layer 13 the most surperficial, be formed with soldering protective layer 14.In the illustrated case, represented two kinds of brazing layer 13A, 13B that fusing point is different, but brazing layer is as long as the fusing point difference can be made of also two or more a plurality of brazing layers.
The electrode layer 15 high with the adhesiveness of Submount substrate 12 also can be formed at the bottom at brazing layer 13.Between electrode layer 15 and brazing layer 13A, the adhesiveness when forming in order further to improve also can dispose not shown adhesion layer.Can use Ti (titanium) or Pt (platinum) etc. as adhesion layer.On the side of Submount substrate 12, also can form same electrode layer and the two sides of Submount substrate 12 is electrically connected.Also can on the part of electrode layer 15, connect gold thread and form circuit.
Each layer 13A, the 13B of brazing layer 13 is preferably the what is called that does not contain Pb does not have the Pb soldering, more preferably contains the soldering of the two or more element among Ag, Au, Cu, Zn, Ni, In, Ga, Bi, Al, the Sn.
Here, brazing layer 13A and 13B change and form and make the fusing point difference, but as the composition of brazing layer, can use soldering that contains Au and Sn or Ag and Sn or the soldering that contains Ag, Au and Sn.In addition, brazing layer 13 also can be made of two-layer, the one deck in two-layer by the element set of Au become that brazing layer more than 50% constitutes, another layer in two-layer be made up of the element of Au and be lower than 50% brazing layer and constitute.One deck in equally, also can be two-layer by the element set of Ag and Au become that brazing layer more than 50% constitutes, another layer in two-layer be made up of the element of Ag or Au and be lower than 50% brazing layer and constitute.
For electrode layer 15, be preferably metal, more preferably a kind of among Au, Pt, Ag, Cu, Fe, Al, Ti, the W.As soldering protective layer 14, be preferably Au, Pt, the such noble metal of Ag, be preferably Au especially.
Then, the installation of the semiconductor element that the Submount that utilizes the 2nd execution mode is carried out describes.
Fig. 7 is the cutaway view of schematically representing the structure of mounting semiconductor element on the Submount of Fig. 6.On the Submount 10 of Fig. 7, semiconductor element 7 is arranged by brazing layer 13 soldered joint.Semiconductor element 7 comprise the such light-emitting component of laser diode or light-emitting diode, diode, high frequency amplify or switch in the such active element of the transistor that uses or thyristor, integrated circuit etc.
The feature of the Submount 10 of the 2nd execution mode is: have the different two or more brazing layer 13 of fusing point and be located at the soldering protective layer 14 of the superiors of this brazing layer 13.Here, brazing layer 13 is made of fusing point different two- layer 13A, 13B, and the fusing point of the brazing layer 13A of electrode layer 5 sides is than the brazing layer 3B height that forms above it, and the fusing point of soldering protective layer 4 is all higher than the fusing point of brazing layer 13A, 13B.And soldering protective layer 4 is the metals that are melted in brazing layer 13A, 13B.
In the case, if heat with engaging of brazing layer 13 in order to carry out semiconductor element 7, the brazing layer 13B that then fusing point is minimum fuses at first, then brazing layer 13A fusion.If the brazing layer 13B that fusing point is minimum reaches fusion beginning temperature and begins fusion, then the soldering protective layer 14 of the upside of brazing layer 13B produces to the phase counterdiffusion of the liquid phase of brazing layer 13B and begins fusion.Equally, if the minimum brazing layer 13B of fusing point begins fusion, the higher brazing layer 13A of fusing point then takes place begin fusion to the phase counterdiffusion of its liquid phase.If making the temperature of brazing layer 13A, 13B and 4 fusions of soldering protective layer is complete melting temperature, then finish in the moment fusion that reaches complete melting temperature by heating, by cool to room temperature, semiconductor element 7 engages securely with brazing layer 13.
In the Submount 10 of the 2nd execution mode; because brazing layer 13 is the different multi-ply constructions of fusing point; the superiors of brazing layer 13 are covered by soldering protective layer 14; so with situation that semiconductor element 7 engages under; the fusion of fusion beginning temperature, soldering protective layer 14 begins temperature, the complete equal step-down of melting temperature, and the result can reduce junction temperature.That is, by rise to junction temperature during in brazing layer 13 is fused more than being divided into for two stages, can improve the fusion of brazing layer 13 self, and the soldering protective layer 14 that is provided with for the oxidation that prevents the surface is easily fused.According to this execution mode, can provide on the basis that makes semiconductor element 7 actions, have the Submount 10 of enough bond strengths at low temperatures.Thereby, can form the less joint of thermal stress.That is the residual heat strain that takes place in the time of, can reducing cooling when engaging.Therefore, use the thermal stress in the semiconductor device of Submount 10 to diminish, can improve the performance and the life-span of semiconductor device.
Embodiment 3
Below, illustrate in greater detail the present invention based on embodiment 3 and 4.At first the manufacture method to the Submount of embodiment 3 describes.
The two sides of the aluminium nitride sintered base plate (55mm is square, and 0.3mm is thick) by lapping device grinding high thermal conductivity (230W/mK).In addition, fine finishining is ground and is to use burnishing device to implement.12 cleanings of aluminium nitride sintered base plate after grinding are made cleaning surfacesization, in order to carry out photolithographic Butut, after utilizing surface that spin coater is coated on Submount substrate 12 equably with resist on the whole, with the baking that oven is stipulated, utilize the mask alignment device to carry out the contact exposure of gamma line.The mask design of exposure usefulness is, can be with the square Submount size of 1mm 2500 of Bututs simultaneously.After exposure, will Submount substrate 12 be exposed as the resist dissolving of the part of electrode layer with developer solution.
By the Ti of vacuum deposition apparatus evaporation 0.05 μ m, follow the Au of evaporation 0.1 μ m.Use acetone that resist is all dissolved, Au beyond the electrode layer 15 and Ti are lifted from removing, form electrode layer 15 with predetermined pattern.The size of electrode layer 15 all is that 800 μ m are square on the two sides.
Then, utilize photoetching process and possess the vacuum deposition apparatus of two electron guns, on the part of the electrode layer 15 of the face side of Submount 12, form brazing layer 13 and soldering protective layer 14, form pattern.The composition of brazing layer 13 is Au and Sn, by two electron guns while evaporation Au and Sn, forms the brazing layer 13A with specific thickness and regulation composition.Then, change the evaporation condition, form the brazing layer 13B of specific thickness to change the composition of brazing layer.Use Au as soldering protective layer 14.The size of brazing layer 13 is, it is square that the face of bond semiconductor element 7 is made as 400 μ m, and it is square, last that the composition surface, the back side of Submount substrate 12 is made as 800 μ m, for Submount substrate 12 being divided into the Submount size of regulation, it is square to use slicing device to be cut to 1mm.
As shown in table 2, the element ratio of components of the brazing layer 13A of embodiment 3 is Au: Sn=18.6: 81.4, and its thickness is 3.5 μ m.The composition of brazing layer 13B is Sn100%, and its thickness is 0.5 μ m.The thickness of the Au layer of soldering protective layer 14 is 0.05 μ m.It is Au that the element of the integral body of these brazing layers 13A, 13B and soldering protective layer 14 is formed: Sn=18.0: 82.0, and the total of thickness is 4.05 μ m.
[table 2]
Figure G2009101680478D00271
Embodiment 4
Except the composition difference of brazing layer, use the Submount 1 of the method manufacturing embodiment 4 identical with embodiment 3.The brazing layer 3A of embodiment 4 and the element of 3B are formed score Wei Au: Sn=6.3: 93.7, Au: Sn=70.0: 30.0.The element of the integral body of brazing layer 13A, 13B and soldering protective layer 4 is formed identical with embodiment 3, is Au: Sn=18.0: 82.0, and the total of thickness is 4.05 μ m (with reference to table 2).Like this, in embodiment 3 and 4, it is to contain the brazing layer of 50% above Au and be lower than 50% brazing layer respectively that the element of brazing layer 13A and 13B is formed.
Then, comparative example 3 and 4 is described.
(comparative example 3)
Except brazing layer 13 being made 1 layer, the element of brazing layer 13 is formed being adjusted to Au: Sn=16.5: 83.5, use the operation identical to make Submount with embodiment 3.It is Au that the element of the brazing layer 13A of comparative example 3 and the integral body of soldering protective layer 14 is formed identical with embodiment 3: Sn=18.0: 82.0, and the total of thickness is 4.05 μ m.
(comparative example 4)
As a comparative example 4, make the Submount of structure same.Except not using soldering protective layer 14, will making the double-layer structural that the Au by the Sn of 3.56 μ m and 0.49 μ m constitutes, use the operation identical to make Submount with embodiment 3 as the layer of brazing layer 13.It is Au that the element of brazing layer 13 integral body of comparative example 4 is formed identical with embodiment 3: Sn=18.0: 82.0, and the total of thickness is 4.05 μ m.In addition, as above-mentioned embodiment 3 and 4 and comparative example 13A, 13B shown in, the composition of soldering protective layer 14 and brazing layer 13 or brazing layer integral body and thickness are all identical under any situation.
Each characteristic to the Submount of manufacturing in embodiment 3,4 and comparative example 3,4 describes.
Carry out the fusion state of the brazing layer 13 that on above-mentioned Submount 10, forms and the bond strength when being bonded on semiconductor element 7 on the Submount 10 is estimated.For the fusion state of brazing layer 13, serviceability temperature is regulated the bottom surface heating of correct Halogen lamp LED heater with Submount 10, makes brazing layer 3 fusions, the fusion behavior of Visual Confirmation brazing layer 13.In addition, in order to confirm melting temperature, utilize differential thermal analysis device (DSC:Differential ScanningCalorimetry) to measure the fusion situation.
Table 3 is tables of the fusion state of expression embodiment 3,4 and comparative example 3,4, represents the melting temperature of the material self of each brazing layer, the fusion order of brazing layer and the melting temperature of dsc measurement.
[table 3]
Figure G2009101680478D00291
In embodiment 3, according to visualization, brazing layer 13B fusion, then brazing layer 13A fusion.According to dsc measurement, brazing layer 13B begins fusion under 242 ℃, and then soldering protective layer 14 fuses among the brazing layer 13B near 260 ℃, and the temperature that whole brazing layers 13 begins to fuse is 270 ℃, and it is 280 ℃ that whole brazing layers 13 all fuses.
In embodiment 4, according to visualization, brazing layer 13A fuses at first, then brazing layer 13B fusion.According to dsc measurement, brazing layer 13A then comprises that whole brazing layer 13 of soldering protective layer 14 fuses since 230 ℃ of fusions near 270 ℃, and it is 280 ℃ that whole brazing layers 13 all fuses.
In comparative example 3, according to dsc measurement, the fusion of brazing layer 13 itself is near 275 ℃, and soldering protective layer 14 is near fusions 277 ℃, and fusing fully is 285 ℃, than embodiment 3,4 height.
In comparative example 4, according to visualization, the brazing layer 13A that is made of the Sn individual layer fuses at first.According to dsc measurement, under 242 ℃, begin fusion as the brazing layer 13A of Sn individual layer, and be since 280 ℃ of fusions as the brazing layer 13 of Au individual layer, it is 315 ℃ that soldering is fused fully, than embodiment 3,4 height.In addition, according to the dsc measurement of comparative example 4 as can be known, near about 280 ℃, there is the heating peak value, taken place and the different phenomenon of fusion phenomenon.
Then, the bond strength evaluation to embodiment 3,4 and comparative example 3,4 describes.
In order to investigate soldered joint intensity, after brazing layer 13 fusions that make Submount 10 by heater, from upper bond semiconductor element 7, cooling behind joint and produce sample.Then, estimate with the band disbonded test of band and the observation of peeling off state.The band disbonded test is identical with the method for generally using in the adhesion strength of metal is measured, and the band of use adopts the band with certain bonding force.With that the electrode peeled off has taken place is bad as engaging because of the band disbonded test in the electrode of the semiconductor element 7 that engages, with the ratio of bad number as engagement state.Use light-emitting diode as semiconductor element 7, sample number all is each 100 in embodiment 3,4 and comparative example 3,4.
Table 4 be expression embodiment 3,4 and comparative example 3,4 joint the band during light-emitting diode 7 peel off the table of rate.For each embodiment 3,4 and comparative example 3,4, junction temperature is engaged semiconductor element 7 270～300 ℃ of variations, implement girdle tests.
[table 4]
Figure G2009101680478D00301
In embodiment 3, it is respectively 8%, 5%, 3% that 270 ℃, 275 ℃, 280 ℃ band is peeled off rate, and peeling off of semiconductor element 7 do not taken place under the junction temperature more than 285 ℃.
In embodiment 4, it is respectively 15%, 7%, 3% that 270 ℃, 275 ℃, 280 ℃ band is peeled off rate, and peeling off of semiconductor element 7 do not taken place under the junction temperature more than 285 ℃.
In comparative example 3, it is respectively 60%, 20%, 15%, 4% that 270 ℃, 275 ℃, 280 ℃, 285 ℃ band is peeled off rate, and peeling off of semiconductor element 7 do not taken place under the junction temperature more than 290 ℃.
On the other hand, in comparative example 4, it is to become 5% from 80% that the band till 270 ℃～300 ℃ is peeled off rate, even at 300 ℃ of joints peeling off of semiconductor element 7 taken place also.
According to the foregoing description 3,4 and comparative example 3,4; in the Submount 10 that possesses the two-layer brazing layer that constitute 3 different and soldering protective layer 4 by fusing point; make the fusion of brazing layer 13 begin about 230～240 ℃ the low temperature that temperature is a low temperature, can carry out fusion by stages by the two-layer brazing layer that constitutes.Therefore, can make the fusion fully that comprises soldering protective layer 14 become 280 ℃, semiconductor element 7 can be engaged securely with brazing layer 13.
Then, the structure to the Submount of the 3rd execution mode of the present invention describes.
Fig. 8 is the cutaway view of structure of schematically representing the Submount of the 3rd execution mode of the present invention.The Submount 20 of this execution mode has Submount substrate 22, cover part or all of Submount substrate 22 and be formed on the electrode layer 23 on the upper surface of Submount substrate 22 and be formed on the lip-deep brazing layer 24 of this electrode layer 23.On the opposite face of the upper surface with carrying element of Submount 20, be formed with electrode layer 25 and brazing layer 26, so that part or all of the back side of the Submount substrate 22 of its covering clad metal radiator.Here, on Submount substrate 22 on, the position that forms the brazing layer 24 of electrode layer 23 is under the situation of light-emitting diode etc., both can be that whole face also can be an electrode pattern at element.In addition, also can on the part of electrode layer 23, connect gold thread or aluminum steel with being connected of outside terminal, to form circuit in order to carry out.Electrode layer 23 and electrode layer 25 are same materials, and in addition, brazing layer 24 and brazing layer 26 also can be same material.The formation element of brazing layer 24 can be to comprise at least a above metal material among Au, Ag, Cu, Zn, In, Ga, Bi, Fe, Pb, Ti, Al, Sb, the Ni and the alloy of Sn, but is preferably no Pb soldering especially.
The composition of the formation element of brazing layer 24 is preferably the composition of the eutectic composition of the formation element that departs from separately.And, make have the solidus temperature that begins to fuse from brazing layer 24 and become the melting temperature scope of the liquidus temperature of liquid phase to fusing fully, be temperature difference.The preferred composition of regulating brazing layer 24 is so that this melting temperature scope is more than 10 ℃.As long as this melting temperature scope is programming rate under the reflux when also considering semiconductor device engaged and heating-up time and suitably set so that it becomes the most suitable just passable.
Characteristic when showing that Differential scanning calorimetry is estimated the molten condition of brazing layer 24 is described.
In the case, when the heating of brazing layer 24, can obtain being enough to carry out the liquid phase of soldered joint with the peak value of the initial hot temperature of absorption differential.If heat again, then reach the temperature that expression absorbs the peak value of the hot temperature of differential, and then can access sufficient liquid phase at high temperature side.In the differential thermal behavior with brazing layer 24 heating the time, preferably make the temperature of initial demonstration differential heat fluctuation and expression fully the temperature that finishes of the differential heat fluctuation of fusion difference than 10 ℃ greatly.Under this temperature difference is situation below 10 ℃, owing to can not make the melting temperature scope of brazing layer 24 enough big, so be not preferred.In the differential thermal behavior when above-mentioned brazing layer is heated, between the temperature of the initial differential heat fluctuation end that shows the temperature of differential heat fluctuation and represent to fuse fully, also can have the differential thermal peak point more than 2.
The formation element of electrode layer 23 is preferably metal, further preferably comprises at least a among Au, Pt, Ag, Cu, Fe, Al, Ti, W, the Ni.Submount substrate 22 can use any among AlN, SiC and the Si.In addition, on the side of Submount substrate 22, also can form with above-mentioned same electrode layer 23 and the upper surface of Submount substrate 22 is electrically connected with lower surface.
Then, the installation of the cutaway view that utilizes Fig. 9 semiconductor element that the Submount with above-mentioned the 3rd execution mode is carried out describes.As shown in Figure 9, on Submount 20 of the present invention, semiconductor element 7 is arranged by brazing layer 24 soldered joint.So-called semiconductor element comprises the such active element of the such light-emitting component of laser diode or light-emitting diode, diode, the transistor that uses or thyristor, integrated circuit etc. in high frequency amplification or switch.
The feature of this Submount 20 is, in the Submount 1 that engages semiconductor element 7 such as light-emitting component, forms brazing layer 24 by the alloying state with the composition of the eutectic composition that departs from formation element separately, and the melting temperature scope of brazing layer 24 is broadened.Like this by making consisting of of brazing layer 24 depart from the composition of eutectic composition, can be with the melt temperature scope of brazing layer 24 with respect to the situation that in eutectic composition, only limits to 1 of eutectic temperature, expand to from the fusion of representing by solidus temperature and begin temperature to the fusion end temp of representing by liquidus temperature.Therefore,, then become the state that in brazing layer 24, contains liquid phase,, the counterdiffusion mutually with the electrode of semiconductor element 7 can take place, can easily engage so can infer when having engaged semiconductor element 7 if fusion begins more than the temperature.
Below the manufacture method of the Submount of above-mentioned the 3rd execution mode is described.
At first prepare Submount substrate 22, grinding is carried out with lapping device in its two sides, use enforcement fine finishining grindings such as burnishing device.Submount substrate after grinding 22 is cleaned, carry out cleaning surfacesization, for the circuit pattern with regulation on the face of the element mounting side of Submount substrate 2 forms electrode layer 23 and carries out the Butut operation.In the Butut operation, use photoetching process, on the surface of the Submount substrate 22 beyond the zone of the film that will form electrode layer 23, form resist film.
Then, by the metal level of vacuum vapour deposition formation as electrode layer 23.As vacuum evaporation, can use methods such as electron beam evaporation plating method, electrical resistance heating, sputtering method.Then, on the upper surface of Submount substrate 22, form electrode layer 23 by lifting from operation.Particularly, by anticorrosive additive stripping liquid controlling, the resist film that will form in above-mentioned Butut operation utilizes the swelling of resist film with the metal level of evaporation on resist film and removes.Thus, can on Submount substrate 22, form electrode layer 23 with predetermined pattern.As anticorrosive additive stripping liquid controlling, can use acetone, isopropyl alcohol or other anticorrosive additive stripping liquid controllings.With the cleaning surfacesization of electrode layer 23, be used for forming the Butut operation of the brazing layer 24 of predetermined pattern.In Butut, can use photoetching process.Here, in the cleaning of electrode layer 23, can adopt ozone in wet-cleaned or plasma or the UV irradiation to decompose such dry type and clean.
Then, with brazing layer 24 film forming.In the film forming of brazing layer 24, be preferably the method for each element that constitutes the alloy brazed of raw material from vapor deposition source evaporation independently.For example, under the situation that brazing layer 24 is made of Au and 2 yuan of such alloys of Sn, can form by the electron beam evaporation plating method of using two kinds of vapor deposition source.In the film forming of raw material, also can make and be heated by resistive vapour deposition method.In addition, except vacuum vapour deposition, also can use sputtering method or coating process etc.Here, the composition of brazing layer 24 designs so that its film that becomes regulation is formed according to the evaporation rate and the film formation speed of each raw material, as long as carry out evaporation so that the composition of the depth direction of brazing layer 24 becomes evenly just passable by control evaporation rate separately.In addition, the composition in the face of brazing layer 24 preferably keeps the shape of arch (dome) and the evaporation mechanism of raw material to make it even by the substrate of optimizing in the evaporation coating device.
The act of carrying out brazing layer 24 is from operation, and the pattern that carries out brazing layer 24 on electrode layer 23 forms.Particularly, the resist film that will form in above-mentioned Butut operation utilizes the swelling of resist film to remove with the brazing layer 24 of evaporation on this resist film by anticorrosive additive stripping liquid controlling.Thus, can on electrode layer 23, form brazing layer 24 with predetermined pattern.As anticorrosive additive stripping liquid controlling, can use acetone, isopropyl alcohol or other anticorrosive additive stripping liquid controllings.
Rear side at Submount substrate 22 also forms electrode layer 25 and brazing layer 26, and is last, and Submount substrate 22 is cut apart with the size of regulation.Figure 10 is a partial sectional view of schematically representing the slicing process before cutting apart in the manufacture method of Submount of the present invention.As shown in figure 10, by the cuttings such as microtomy of having used diamond disk, the position 37 (slice) that separate dashed line is represented, can access the Submount 20 of desired size with the Submount substrate 31 before the cutting apart of said method manufacturing.This microtomy also can be to use the scriber of laser or the method for fusing.
According to the manufacture method of the Submount 20 of the 3rd execution mode, can high finished product rate ground make the good Submount 20 of soldered joint with semiconductor element 7.
Embodiment 5
Below, illustrate in greater detail the 3rd execution mode based on embodiment 5.At first, the manufacture method to the Submount of embodiment 5 describes.
(two sides of 170～270W/mK) sintered aluminum nitride substrate 22 is by the lapping device grinding, so that mean roughness (Ra) becomes below the 0.2 μ m, uses burnishing device to carry out fine finishining and grinds with high thermal conductivity.Aluminium nitride substrate 22 after grinding undertaken cleaning surfacesization by the wet-cleaned method, on the face that carries element one side, utilize photoetching process to cover the zone that does not form electrode layer 23 with resist film.Form the pattern of electrode layer 23, so that the size of Submount 1 becomes 1mm * 2mm is square.
Then, the Au layer is stacked into the thickness of 0.2～0.4 μ m, uses acetone to lift from operation, form electrode layer 23 as stripper by vacuum deposition apparatus.Same with electrode layer 23, use photoetching process and vacuum vapour deposition, by lifting from forming brazing layer 24.At first, the electron beam evaporation plating device of the evaporation source by possessing Au and Sn forms brazing layer 24 being formed on the Au aluminium nitride substrate 22 lip-deep electrode layers 23.The composition of this brazing layer 24 is adjusted to, make accumulation brazing layer 24 consist of Au: Sn=20: 80 (elements than), and be adjusted to and make its eutectic composition that departs from Au-Sn ratio.This make this composition brazing layer 24 by the fusing point of liquidus temperature definition and Au: Sn=70 as the eutectic composition of Au-Sn: the fusing point of 30 (elements than) is identical, in addition the purpose that compares with comparative example described later.
Then, use acetone to lift from operation, form the pattern of brazing layer 24 as stripper, last, utilize slicing device to be cut to the rectangle of 1mm * 2mm the aluminium nitride substrate 22 that obtains, made the Submount 20 of embodiment.
Then, comparative example 5 is described.
(comparative example 5)
Except the composition with brazing layer 24 is adjusted to Au as eutectic composition: Sn=30: 70 (elements than), use the operation identical to make Submount with embodiment 5.
Each characteristic to the Submount that obtains in embodiment 5 and comparative example 5 describes.
At first, measure the melting temperature scope of the brazing layer 24 that on the Submount 1 of embodiment 5 and comparative example 5, forms.Measurement is to carry out by the following method: with brazing layer 24 heating, the measurement of the melting temperature scope of brazing layer 24 is carried out in the visualization and the differential scanning calorimetry (DSC:Differential Scanning Calorimetry) of the fusion state by having used heating microscope.Particularly, in dsc measurement, measure the temperature differential thermal peak that changes mutually take place when heating, will from corresponding to the initial peak of solidus to corresponding to the peak value of liquidus curve as the melting temperature scope.
Figure 11 is result's the figure of the dsc measurement of expression embodiment 5, transverse axis represent temperature (℃), the longitudinal axis is represented differential heat (μ W), a side is the endothermic reaction.As shown in Figure 11, under the situation of embodiment 5, since the fusion (with reference to the arrow A of Figure 11) of 219 ℃ of brazing layers 24, melt temperature is 285 ℃ (with reference to arrow B of Figure 11) fully.
Figure 12 is result's the figure of the dsc measurement of expression comparative example 5.The transverse axis among the figure and the longitudinal axis are identical with Figure 11.As shown in Figure 12, under the situation of the Au-Sn of the eutectic composition of comparative example 5, fusion beginning temperature is 277 ℃, and melting temperature is 287 ℃ fully, and the melting temperature scope is 10 ℃ (with reference to arrow C, D of Figure 12).
Table 5 is tables of measurement result of the melting temperature of expression embodiment 5 and comparative example 5.
[table 5]
Figure G2009101680478D00361
As shown in Table 5, the melting temperature scope of the brazing layer 24 of embodiment 5 is 66 ℃, and on the other hand, the brazing layer of comparative example 5 is eutectic compositions, and the melting temperature scope is 10 ℃.Can judge that thus it is 219 ℃ that the fusion of the brazing layer 24 of embodiment 5 begins temperature range, than low 58 ℃ of comparative example 5, the melting temperature scope till the complete melting temperature is 66 ℃ a bigger temperature range.
Submount and soldered joint semiconductor element to embodiment 5 and comparative example 5 describes.In order to investigate soldered joint intensity, utilize heater to make brazing layer 24 fusion of Submount 20 after, from upper bond semiconductor element 7, engage the back cooling with the perparation of specimen, estimate with band disbonded test of being with and the observation of peeling off state.The band disbonded test is carried out similarly to Example 3.As semiconductor element 7, the light-emitting diode that uses electrode to have the square size of 300 μ m, sample number all is each 100 in embodiment and comparative example.
As shown in table 5, in embodiment 5, the band when making junction temperature be changed to 240 ℃, 255 ℃ is as can be known peeled off rate and is respectively 99%, 38%, can fully engage under 265 ℃～290 ℃.
On the other hand, in comparative example 5, being with under 240 ℃～265 ℃ and peeling off rate is 100%, can not engage, and be 15% under 285 ℃, being with under 290 ℃ and peeling off rate is 0%.Like this, in comparative example 5, just can not engage if temperature is not risen to 290 ℃.
Figure 13 is in embodiment 5, (A) optical microscope image of observing from above of the Submount 20 of band after the disbonded test and (B) its key diagram.Multiplying power is 181 times.As shown in Figure 13, engaging on the brazing layer 24 that is formed on the electrode layer 23 that is made of Au has light-emitting diode 7, does not peel off.
Figure 14 is in comparative example 5, (A) optical microscope image of observing from above of the Submount 20 of light-emitting diode 7 after peeling off and (B) its key diagram in the band disbonded test.Multiplying power is 181 times.Can observe regional 4a that the brazing layer 24 that forms peels off and the brazing layer 24b that peels off by Figure 14 on the electrode layer 23 that is made of Au, can know between electrode layer 23 and brazing layer 24 and take place to peel off that light-emitting diode 7 is peeled off as a result.
According to the foregoing description 5 and comparative example 5 as can be known, in Submount 20, depart from eutectic composition by the composition that makes the brazing layer 24 that is used for engaging light-emitting diode 7, allowing that junction temperature reaches under 290 ℃ the situation, in embodiment 5, between 265～290 ℃ 25 ℃ temperature range, can with respect to this, in comparative example, can only engage down not with the joint of peeling off at 290 ℃.Like this, in embodiment 5, can enlarge the junction temperature scope of semiconductor element 7 and brazing layer 24, and can engage at low temperatures.
Then, with reference to the cutaway view of Figure 15, the structure of the Submount 30 of relevant the 4th execution mode is described.
The Submount 30 of the 4th execution mode as shown in figure 15, on the single face or two sides of Submount substrate 32, be formed with electrode layer 33 in part or all the mode that covers Submount substrate 32, on the regulation position on the surface of this electrode layer 33, be formed with brazing layer 34.The position of electrode layer 33 both can be whole of electrode layer under the situation of light-emitting diode etc., also can be electrode pattern.In addition, also can on the part of electrode layer 33, connect gold thread and form circuit.Submount substrate 32 can use the higher aluminium nitride of pyroconductivity, carborundum, diamond IIa etc.In addition, on the side of Submount substrate 32, also can form with above-mentioned same electrode layer and the upper surface of Submount substrate 32 is electrically connected with lower surface.Electrode layer 33 is preferably metal, can use in gold, platinum, silver, copper, iron, aluminium, titanium, the tungsten any especially.Brazing layer 34 is preferably and does not use plumbous no Pb soldering.And then, can preferably use the soldering that contains the two or more elements in silver, gold, copper, zinc, nickel, indium, gallium, bismuth, aluminium, the tin.
The feature of the Submount 30 of the 4th execution mode is, the amount of the interface by making Submount substrate 32 and electrode layer 33 and the carbon of near interface is below the normal concentration, improves the adhesiveness of Submount substrate 32 and electrode layer 33.In addition, in the present invention, comprise that interface and near interface all are called near interface.Also can make the electrode layer 33 and the amount of the carbon of the near interface of brazing layer 34 is below the normal concentration, to improve adhesiveness.
Here, the concentration as the carbon of impurity is that for each near interface of Submount substrate 32, electrode layer 33, brazing layer 34, the amount that makes carbon is 1 * 10 20Atoms/cm 3Below.If surpass this scope, the adhesiveness variation of each near interface of Submount substrate 32, electrode layer 33, brazing layer 34 then is so be not preferred.Thus, can will engage securely between Submount substrate 32 and the electrode layer 33 and as described later especially between Submount 30 and the semiconductor device 7.
Figure 16 is the cutaway view of structure of Submount 40 of schematically representing the variation of 4th execution mode different with Figure 15.The difference of Submount 15 and Submount 30 shown in Figure 15 is to be provided with substrate protective layer 35 in part or all the mode that covers Submount substrate 32 between Submount substrate 32 and electrode layer 33.This substrate protective layer 35 is to cover whole lip-deep layer at first in the manufacturing of Submount 30, is the protective layer that prevents to corrode because of etching etc. the surface of Submount substrate 32 in the operation of electrode layer 33 on forming substrate protective layer 35 and brazing layer 34.As substrate protective layer 35, be the metal that can prevent the corrosion of Submount substrate 32, and be preferably the metal different with electrode layer 33, can use in titanium, platinum, nickel, tungsten, molybdenum, silver, copper, iron, aluminium, the gold any.
In Submount shown in Figure 16 40, be 1 * 10 by making the Submount substrate 32 and the amount of the carbon of the near interface of substrate protective layer 35 20Atoms/cm 3Below, can carry out the adhesion of Submount substrate 32 and substrate protective layer 35 well.And then, be 1 * 10 by making the electrode layer 33 and the amount of the carbon of the near interface of brazing layer 34 20Atoms/cm 3Below, can improve the adhesiveness of this near interface.
And then as their variation, Submount 42 that also can be as shown in figure 17 is such, by adhesion layer 36 is clipped between electrode layer 33 and the brazing layer 34, improves the adhesiveness of electrode layer 33 and adhesion layer 36, adhesion layer 36 and each interlayer of brazing layer 34.As adhesion layer 36, can be the metal same with aforesaid substrate protective layer 35, can preferably use titanium.
As above-mentioned variation, Submount 44 that also can be as shown in figure 18 is such, for oxidation of preventing brazing layer etc. and also form soldering protective layer 37 on brazing layer 34.
Then the installation of the semiconductor device that the Submount that utilizes the 4th execution mode is carried out with reference to Figure 19 describes.In Figure 19, represented the situation of semiconductor device lift-launch on Submount shown in Figure 16 40, but for other Submounts 30,42,44 too.
As shown in figure 19, on Submount 40 of the present invention, by brazing layer 34a soldered joint semiconductor device 7.Semiconductor element is the such active element of the such light-emitting component of laser diode or light-emitting diode, diode, the transistor that uses in high frequency amplification or switch or thyristor, integrated circuit etc.
The feature of the Submount 30,40,42,44 of the 4th execution mode is; the near interface of the near interface by making Submount substrate 32 and electrode layer 33, Submount substrate 32 and substrate protective layer 35, to also have the electrode layer 33 and the amount of the carbon of the near interface of brazing layer 34 be below the afore mentioned rules amount; improve the adhesiveness of each vicinity, interface, improve the zygosity of Submount 30 and semiconductor device 7.In addition, owing to can not use the so-called adhesion layer that in the past always used, so can reduce the manufacturing process and the materials used of Submount 30,42,44.Therefore, can provide Submount cheaply.
Then, the manufacture method to the Submount of above-mentioned the 4th execution mode describes.Below, the manufacture method of Submount shown in Figure 16 40 is described.
At first, prepare Submount substrate 32, by its two sides of lapping device grinding, use burnishing device etc. to implement fine finishining and grind, the mean roughness that makes Submount substrate 32 surfaces is for being lower than 0.1 μ m, more preferably being lower than 0.05 μ m.
Carry out the surface cleanization of Submount substrate 32.This surface cleanization preferably uses plasma incineration of ultraviolet and ozone facture and oxygen etc. etc. to carry out, and will remove attached to the lip-deep carbon compound of Submount substrate 32, and making concentration of carbon is below the afore mentioned rules value.
Form substrate protective layer 35a on the whole on Submount substrate 32 surfaces of having carried out surface clean.This substrate protective layer 35a can form by the vapour deposition method that uses vacuum deposition apparatus or sputtering unit.By above-mentioned cleaning surfacesization, can make Submount substrate 32 and connecting airtight of substrate protective layer 35a become good.
Then, carry out photolithographic Butut.Particularly, equably behind the painting erosion resistant agent,, use the mask alignment device to carry out the contact exposure of gamma line to the whole spin coater that uses in the surface of Submount substrate 32 with the baking that oven is stipulated.After exposure,, will substrate protective layer 35a be exposed as the resist dissolving of the part of electrode layer 33a with the developer solution of tetramethyl amine.
Then,, use acetone that resist is all dissolved by the metal of evaporations such as vacuum deposition apparatus as electrode layer 33a, thus with the metal beyond the electrode layer 33a by lifting from removing, form the electrode layer 33a of regulation.Before the formation of this electrode layer 33a, preferably carry out the surface cleanization of substrate protective layer 35a, will remove attached to the lip-deep carbon compound of substrate protective layer 35a, the concentration of carbon that makes electrode layer 33a surface is below the afore mentioned rules value.This surface cleanization can be undertaken by ultraviolet and ozone processing or oxygen plasma ashing method etc.Thus, can improve the adhesiveness of substrate protective layer 35a and electrode layer 33a.
Same with the formation of above-mentioned electrode layer 33a, the act of having used photoetching process and vacuum vapour deposition from, on the part of electrode layer 33a, form brazing layer 34a.At this moment, preferably, before the vacuum evaporation of carrying out brazing layer, to the surface of the electrode layer 33a that exposes and above-mentionedly similarly carry out surface cleanization, to remove attached to the lip-deep carbon compound of electrode layer 33a, the concentration of carbon that makes electrode layer 33a surface is below the afore mentioned rules value.Thus, can improve the adhesiveness of electrode layer 33a and brazing layer 34a.Then, remove by etching, the surface of Submount substrate 32 is exposed remaining in the Submount substrate 32 surperficial substrate protective layer 35a that go up and expose.At last, the Submount substrate that obtains 32 is used slicing devices etc. be divided into the size of the Submount 30 of regulation.
Like this; in the present embodiment; before forming Submount substrate 32, substrate protective layer 35a, electrode layer 33a, brazing layer 34a; to remove attached to the lip-deep carbon compound that exposes with ultraviolet and ozone processing or oxygen plasma ashing method by each region surface that these are exposed; make that to be present in its lip-deep concentration of carbon be below the afore mentioned rules value, can improve the adhesiveness between each layer that is formed on the Submount substrate 32.In addition, forming between electrode layer 33a and the brazing layer 34a under the situation of adhesion layer, also can carry out the cleaning surfacesization of electrode layer 33a and make concentration of carbon before form brazing layer 34a be below the setting.And then, forming under the situation of soldering protective layer 37 on the brazing layer 34a, also can carry out the cleaning surfacesization of brazing layer 34a and make concentration of carbon be below the setting.
More than the manufacture method of the Submount 40 of a variation of the 4th execution mode is illustrated, but also can similarly make for other Submount 30,42,44.For example, in Submount 44, under the situation of inserting adhesion layer 36, the surface treatment that needs only the carbon that reduced electrode layer 33a surface before forming adhesion layer 36 is just passable.In addition, in each Submount 30,40,42,44, under the situation of inserting soldering protective layer 37, the surface treatment that needs only the carbon that reduced brazing layer 34 surfaces before the formation of soldering protective layer 37 is just passable.
Embodiment 6
At first, the manufacture method to the Submount 30 of embodiment 6 describes.
Grinding is carried out by lapping device in the two sides of the sintered aluminum nitride substrate 2 of the 55mm of high thermal conductivity (230W/mK) is square, thickness 0.3mm, uses burnishing device to implement fine finishining and grinds.
Then, in order to carry out photolithographic Butut, use spin coater equably behind the painting erosion resistant agent on the whole,, use the mask alignment device to carry out the contact exposure of gamma line with the baking that oven is stipulated at substrate surface.With the mask design of exposure usefulness be, can be with the square Submount size of 1mm 2500 of Bututs simultaneously.After exposure, will Submount substrate 32 be exposed as the resist dissolving of the part of electrode layer 33a with tetramethyl amine developer solution.Carry out cleaning surfacesization to remove the carbon on Submount substrate 32 surfaces of exposing by oxygen plasma ashing treatment (pressure 1Pa, high frequency power 300W, processing 2 minutes), come gold evaporation by vacuum deposition apparatus.
Then, utilize acetone that resist is all dissolved, thereby the Au beyond the electrode layer 33a is lifted from removing, form the electrode layer 33a of regulation.The thickness of electrode layer 33a is 0.1 μ m, and its size all is that 800 μ m are square on the two sides.
33a is same with electrode layer, use photoetching process and vacuum deposition apparatus, the part that is formed on aluminium nitride substrate 2 lip-deep electrode layer 33a is reduced the cleaning surfacesization of carbon by oxygen plasma ashing treatment (pressure 1Pa, high frequency power 300W, handled 2 minutes), form the brazing layer 34a of 3.3 μ m.The composition of brazing layer 34a is Ag and Sn.Brazing layer 34a is of a size of, and the semiconductor element composition surface is that 400 μ m are square, and the Submount composition surface is that 800 μ m are square.At last, use slicing device, make the aluminium nitride substrate 32 that obtains become the size of Submount 2, it is square to be cut to 1mm, produces the Submount 30 of embodiment 6.
Embodiment 7
The cleaning surfacesization except handle the formation that (atmospheric pressure, 240W, 30 minutes) carry out each layer by ultraviolet and ozone before, produce Submount 30 similarly to Example 6.
Embodiment 8
Except electrode layer 33a is formed the thickness 2 μ m, produce Submount 30 similarly to Example 6.
Then, comparative example 6 is described.
(comparative example 6)
Except the surface treatment of not carrying out the oxygen plasma ashing treatment among the embodiment 6 and carry out producing the Submount of comparative example 6 similarly to Example 6 in the past the surface clean.With expression in table 6 such as the thickness of the electrode layer of the foregoing description 6～8 and comparative example 6 and the concentration of carbon of near interface described later.
[table 6]
Figure G2009101680478D00421
Then, each characteristic at embodiment 6～8 and comparative example 6 and the Submount that obtains is described.
At first, in embodiment 6,7 and comparative example 6, make in the operation of Submount,, measure concentration of carbon by ESCA (ElectronSpectroscopy for Chemical Analysis) method for each sample before forming brazing layer 34a on the electrode layer 33a.The concentration of carbon ratio is to standardize by the golden peak strength that the carbon peak strength is used as the electrode layer 33a of bottom in each sample to calculate.
Figure 20 represents the result by the concentration of carbon ratio of the electrode layer surface before the formation brazing layer 34a of ESCA measurement embodiment 6,7 and comparative example 6.The concentration of carbon of the longitudinal axis among the figure is to standardize by the golden peak strength that the carbon peak strength is used as the electrode layer 33a of bottom to calculate than in embodiment 6,7 and comparative example 6.As shown in Figure 20, the concentration of carbon on the surface of electrode layer 33a than in the embodiment 6 that has carried out the oxygen plasma ashing treatment for about 0.028, in having carried out the embodiment 7 that ultraviolet and ozone handles, be about 0.025.On the other hand, in the comparative example 6 that does not carry out these surface cleaning processing, the concentration of carbon on the surface of electrode layer 33a is than for about 0.085, compares with embodiment 6 and 7 to be about 3 times.
Then, the concentration of carbon of the brazing layer 34a after the Submount of measuring embodiment 6～8 and comparative example 6 by SIMS (Secondary Ion Mass Spectroscopy) is made with respect to depth direction.For the near interface of analyzing electrode layer 33a and brazing layer 34a accurately, it is 0.1 μ m that embodiment 6 and 7 makes the thickness of electrode layer 33a cross thin, so make electrode layer 33a layer thickening in embodiment 8, implements SIMS and measures.
To be expression measure in the sample of embodiment 6 figure as a result that the concentration of carbon with respect to the depth direction of brazing layer 34a distributes with SIMS to Figure 21.The longitudinal axis is represented concentration of carbon (atom/cm 3), transverse axis is represented the distance (μ m) of depth direction.In the drawings, the left side of the near interface that is illustrated by the broken lines is a brazing layer 34a side, and the right side is an electrode layer 33a side.As shown in Figure 21, the concentration of carbon of the near interface of electrode layer 33a and brazing layer 34a is 1 * 10 20Atoms/cm 3, the concentration of carbon in the brazing layer 34a is 1 * 10 16Atoms/cm 3Below.In addition, analyzing lower limit is 5 * 10 15Atoms/cm 3
To be expression measure the figure as a result of concentration of carbon of the near interface of the electrode layer 33a of embodiment 6～8 and comparative example 6 and brazing layer 34a with SIMS to Figure 22.The longitudinal axis is represented the concentration of carbon (atom/cm of embodiment 6～8 and comparative example 6 3).As shown in Figure 22, the concentration of carbon of the near interface of embodiment 6～8 and comparative example 6 is respectively 1 * 10 20Atoms/cm 3, 9 * 10 19Atoms/cm 3, 3.2 * 10 19Atoms/cm 3, 3 * 10 20Atoms/cm 3, in embodiment 6～8,, can make the concentration of carbon of near interface be reduced to about below 1/3 with respect to comparative example 6.
Then, the adhesiveness to each layer of the Submount of embodiment 6～8 and comparative example 6 describes.On the Submount of embodiment 6～8 and comparative example 6, directly adhere to estimate and estimate with the band disbonded test of band and the observation of peeling off state with band.Here, sample number all is each 100 in embodiment 6～8 and comparative example 6.
Figure 23 is the figure that the band of expression embodiment 6～8 and comparative example 6 is peeled off rate.In the drawings, the longitudinal axis is that band is peeled off rate (%).As shown in Figure 23, in embodiment 6～8, not with peeling off peeling off of the brazing layer 34a that causes.But it is 65% that the band of comparative example 6 is peeled off rate, can judge that brazing layer 34a peels off easily.And the position after the band of comparative example 6 is peeled off all is between electrode layer 33a and the brazing layer 34a, and under the situation of comparative example 6, the engaging force between electrode layer 33a and the brazing layer 34a reduces as can be known.
Figure 24 (A), Figure 24 (B) are respectively to the Submount 30 made in embodiment 6 optical microscope image of observing from above and its key diagram with the Submount after the disbonded test 30.Multiplying power is 181 times.As shown in Figure 24, being formed with Butut on the electrode layer 33a that is made of gold is square brazing layer 34a, does not peel off.
Figure 25 (A), Figure 25 (B) be respectively to the Submount in comparative example 6, made 30 with disbonded test after, the optical microscope image of observing and its key diagram of the Submount 30 of brazing layer 34a after peeling off from above.Multiplying power is 181 times.As shown in Figure 25, among the brazing layer 34a on being formed at the electrode layer 33a that is made of gold, its part is peeled off, and only can observe unstripped regional 34c, has taken place to peel off between electrode layer 33a and brazing layer 34a.
According to the foregoing description 6 and comparative example 6 as can be known, in the Submount 30 that carries semiconductor device 7, between electrode layer 33a and brazing layer 34a, taken place to peel off.
According to the foregoing description 6～8 and comparative example 6, in the Submount 30 that carries semiconductor device 7, the concentration of carbon of the near interface by regulating electrode layer 33a and brazing layer 34a, by the concentration of carbon of adjusting, can improve the adhesiveness of brazing layer 34a to electrode layer 33a with the near interface of electrode layer 33a.
Then, the structure to the Submount of the 5th execution mode of the present invention describes.
Figure 26 is the cutaway view of structure of schematically representing the Submount of relevant the 5th execution mode of the present invention.As shown in figure 26, in the Submount 50 of present embodiment, on the upper surface of Submount substrate 52, be formed with part or all the electrode layer 53 that covers Submount substrate 52, on the regulation position on these electrode layer 53 surfaces, be formed with brazing layer 54.On the other hand, on the face of the opposition side of the upper surface of the semiconductor element mounted thereon of Submount 50, be formed with electrode layer 55 and brazing layer 56, with part or all of Submount substrate 52 back sides that cover the clad metal radiator.
Here, being formed on electrode layer 53 lip-deep brazing layers 54 is under the situation of light-emitting diode etc., both can be whole at element, also can be electrode pattern.In addition, also can on the part of electrode layer 53, connect gold thread or aluminium and be used to carry out and being connected of outside terminal, and form circuit.Electrode layer 53 and electrode layer 55 also can be identical materials.In addition, brazing layer 54 and brazing layer 56 can be formed by identical materials.
The ratio of components of the element of this brazing layer 54 of the formation of above-mentioned brazing layer 54 changes on the depth direction of brazing layer 54.That is, constitute brazing layer element depth direction ratio of components, be ratio of components distribute (following suitably be called to form distribute) be not uniformly, be that uneven composition distributes.
Figure 27 and Figure 28 are respectively the figure that fusing point distributes and composition distributes that schematically represents the brazing layer 54 of Figure 26.In the drawings, the surface that transverse axis represents to establish brazing layer 54 is the distance (arbitrary scale) of 0 o'clock depth direction, and the longitudinal axis is represented the composition (arbitrary scale) of fusing point and brazing layer respectively.One of feature of the present invention is, as shown in figure 27, be arranged to make brazing layer 54 with the semiconductor element engage side, be the fusing point T of surperficial 54A side ABe fusing point T than the back side 54B side of brazing layer BLow composition.
Under the situation that such brazing layer 54 is made of metal A and B, as shown in figure 29, make the composition of metal A higher in its face side, side makes its composition lower overleaf.And, opposite with metal A in metal B, make composition lower in the face side of brazing layer, it is higher that side makes its composition overleaf.Although having expressed the linearity of forming that is changed to changes, thereby form the situation that uneven composition distributes, but the variation of forming also can be surface from brazing layer 54 to the back side for example song linearly or stage shape ground change continuously, thereby form uneven composition distribution.Thus, can make the fusing point T of the face side 54A of brazing layer AFusing point T than its rear side 54B B Low.Brazing layer 54 can use by multiple and constitute the soldering that element constitutes.About the formation element of brazing layer 54, can be to contain at least a above metal material among Au, Ag, Cu, Zn, In, Ga, Bi, Fe, Pb, Ti, Al, Sb, the Ni and the alloy of Sn, and particularly preferably be no Pb soldering.
Then, the example to the composition of brazing layer 54 describes.
Figure 29 is the figure of a part that schematically represents the equilibrium state diagram of brazing layer 54, is the so-called phasor of the more side of Sn of the brazing layer 54 that is made of Ag and Sn.In the drawings, transverse axis is represented the composition (element %) of Sn, the longitudinal axis represent temperature (℃).In brazing layer 54, if make the composition (element ratio) of face side 54A be Ag: Sn=6: 94, then can make fusing point T ABecome about 250 ℃.If make the composition (element ratio) of the back side 54B of brazing layer be Ag: Sn=14: 86, then can make fusing point T BBecome about 300 ℃.Thereby, if the composition of Sn is reduced at the face side 54A of brazing layer height and towards rear side 54B, then can make the fusing point T of the face side 54A of brazing layer AFusing point T than its rear side 54B BLow.
If set the composition of above-mentioned brazing layer 54 as described above, then having formed uneven composition on the above-below direction of brazing layer 54 distributes, distribute the scope of temperature that generation brazing layer 54 begins to fuse and the temperature of fusing fully so can in brazing layer 54, produce fusing point.In the case, the fusing point of the face side 54A of brazing layer is preferably bigger than 10 ℃ with the difference of the fusing point of the rear side 54B of brazing layer.Under the following situation of this value, owing to having climbed of the brazing layer 54 that can not prevent from effectively in the engaging of described later and semiconductor element, to produce, so be not preferred.Thus, the melting range of brazing layer 54 can be enlarged, the adjusting of the amount of liquid phase of generation in brazing layer 54 can be carried out.
Formation element as electrode layer 53 is preferably metal, more preferably comprises at least a among Au, Pt, Ag, Cu, Fe, Al, Ti, W, the Ni.As Submount substrate 52, can use among AlN, SiC and the Si any.In addition, also can on the side of Submount substrate 52, also form and above-mentioned same electrode layer 53, thereby the upper surface of Submount substrate 52 is electrically connected with lower surface.
Then, the installation of the semiconductor element that the Submount that utilizes the 5th execution mode is carried out describes.
As shown in figure 30, on Submount 50 of the present invention, by brazing layer 54 soldered joint semiconductor elements 7.So-called semiconductor element is the such active element of the such light-emitting component of laser diode or light-emitting diode, diode, the transistor that uses in high frequency amplification or switch or thyristor, integrated circuit etc.
One of feature of the Submount 50 of the 5th execution mode is, in the Submount 50 of the semiconductor element 7 that engages light-emitting component etc., form distribution by in brazing layer 54, being provided with, make the fusing point of its face side 54A lower, enlarge the melting temperature scope of brazing layer 54 than the fusing point of rear side 54B.Therefore, in the engaging of brazing layer 54 and semiconductor element 7, the face side 54A of initial brazing layer 54 becomes liquid phase, so if compare with the situation of the brazing layer of even composition, then can reduce the initial amount of liquid phase that produces.If the face side 54A of brazing layer is for more than the fusion beginning temperature, then the face side 54A in the brazing layer 54 becomes the state that contains liquid phase, so when semiconductor element 7 is engaged, can infer the counterdiffusion mutually of easy generation and the electrode of semiconductor element 7, can easily engage.
Thus, according to Submount 50 of the present invention, can reduce the amount of climbing to the soldering on the semiconductor element 7.Thereby, in the such element of semiconductor laser diode, can prevent short trouble effectively, realize the raising of rate of finished products.
Below the manufacture method of the Submount of above-mentioned the 5th execution mode is described.
At first, prepare Submount substrate 52, grinding is carried out by lapping device in its two sides, use enforcement fine finishining masks such as burnishing device.Submount substrate after grinding 52 is cleaned and carry out cleaning surfacesization, for the circuit pattern with regulation on the face of the element mounting side of Submount substrate 52 forms electrode layer 53 and carries out the Butut operation.The Butut operation is used photoetching process, forms resist film on the surface of the Submount substrate 52 beyond the zone of the film that will form electrode layer 53.
To be formed on the whole surface of the Submount substrate 52 that comprises resist film by vacuum vapour deposition etc. as the metal level of electrode layer 53.As vacuum evaporation, can use the method for electron beam evaporation plating method, resistance evaporation method, sputtering method etc.On the upper surface of Submount substrate 52, form electrode layer 53 by lifting from operation.Particularly, the resist film that will form in above-mentioned Butut operation utilizes the swelling of resist film to remove with the metal level of evaporation on resist film by anticorrosive additive stripping liquid controlling.Thus, can on Submount substrate 52, form the electrode layer 53 of pattern with regulation.As anticorrosive additive stripping liquid controlling, can use acetone, isopropyl alcohol, reach other anticorrosive additive stripping liquid controllings.
With the cleaning surfacesization of electrode layer 53, be used for forming the Butut operation of the brazing layer 54 of predetermined pattern.In Butut, can use photoetching process.In the cleaning of electrode layer 53, can use ozone in wet-cleaned or plasma or the UV irradiation to decompose such dry type and clean.
Then, with brazing layer 54 film forming.In this film forming, preferably constitute the method for element as each of the alloy brazed of raw material from vapor deposition source evaporation independently.For example, under the situation that brazing layer 54 is made of Ag and 2 yuan of such alloys of Sn, can form by the electron beam evaporation plating method of using two vapor deposition source.In the film forming of raw material, also can make and be heated by resistive vapour deposition method.In addition, except vacuum vapour deposition, also can use sputtering method or coating process etc.Here, the composition of brazing layer 54 can design the composition so that its film that becomes regulation distributes according to the evaporation rate and the film formation speed of each raw material, by controlling each evaporation rate, ratio of components is changed on the depth direction of brazing layer 54, distribute thereby form uneven composition.In addition, distribution preferably keeps the shape of arch and the evaporation mechanism of raw material to make it even by the substrate of optimizing in the evaporation coating device in the face of the composition of each degree of depth of brazing layer 54.
Then, the act of carrying out brazing layer 54 is from operation, and the pattern that carries out brazing layer 54 on electrode layer 53 forms.Particularly, the resist film that will form in above-mentioned Butut operation utilizes the swelling of resist film to remove with the brazing layer 54 of evaporation on resist film by anticorrosive additive stripping liquid controlling.Thus, can on electrode layer 53, form the brazing layer 54 of pattern with regulation.As anticorrosive additive stripping liquid controlling, can use acetone, isopropyl alcohol, reach other anticorrosive additive stripping liquid controllings.Rear side at Submount substrate 52 also forms electrode layer 55 and brazing layer 56, at last Submount substrate 52 is cut apart with the size of regulation.
Figure 31 is a partial sectional view of schematically representing the slicing process in the manufacture method of Submount of Figure 26.As shown in figure 31, by the cuttings such as microtomy of having used diamond disk, the slice 37 that separate dashed line is represented, can access the Submount 50 of desired size with the Submount substrate 51 of said method manufacturing.This microtomy also can be to use the scriber method of laser or the method for fusing.According to the manufacture method of Submount 50 of the present invention, can make to high finished product rate the good Submount 50 of soldered joint with semiconductor element 7.
Embodiment 9
Below illustrate in greater detail the 5th execution mode of the present invention based on embodiment 9.At first, the manufacture method to the Submount of embodiment 9 describes.
(grinding is carried out by lapping device so that mean roughness (Ra) becomes below the 0.2 μ m in the two sides of 170～270W/mK) sintered aluminum nitride substrate 52 with high thermal conductivity, use burnishing device to carry out fine finishining and grind, the aluminium nitride substrate 52 after grinding undertaken cleaning surfacesization by the wet-cleaned method.
On the face that carries component side, the zone that will not form electrode layer 53 by photoetching process covers with resist film.Form the pattern of electrode layer 53, so that the size of Submount 50 becomes 1mm * 2mm is square.Then, by vacuum deposition apparatus the Au layer being piled up is the thickness of 0.2～0.4 μ m, uses acetone to lift from operation as stripper, forms electrode layer 53.
Same with electrode layer 53, use photoetching process and vacuum vapour deposition, by lifting from forming brazing layer 54.At first the electron beam evaporation plating device of the evaporation source by possessing Ag and Sn forms brazing layer 54 being formed on the aluminium nitride substrate 52 lip-deep electrode layers 53.The composition of this brazing layer 54 is to form to have gradient, so that the composition of its face side 54A and rear side 54B becomes Ag: Sn (element ratio)=6: 94 and Ag: Sn=14 respectively: 86, its thickness is 10 μ m.
Then, use acetone to lift from operation, form the pattern of brazing layer 54 as stripper, last, use slicing device to be cut to 1mm * 2mm rectangle the aluminium nitride substrate 52 that obtains, produce the Submount 50 of embodiment 9.
Then, comparative example is described
(comparative example 7)
Except in brazing layer 54, in composition, uneven distribution is not set and beyond the uniform composition of making Ag: Sn (element than)=6: 94 distributes, produce Submount by the operation identical with embodiment 9.
(comparative example 8)
Except in brazing layer 54, in composition, uneven distribution is not set and beyond the uniform composition of making Ag: Sn (element than)=14: 86 distributes, produce Submount by the operation identical with embodiment 9.
Then, each characteristic to the Submount that obtains in embodiment 9 and comparative example 7,8 describes.
Brazing layer 544 when at first, measuring the joint of the Submount 1 in embodiment 9 and comparative example 7,8, obtain climbed highly h.Figure 32 is the cutaway view of having climbed height h of schematically representing brazing layer 54.As shown in the figure, having climbed height h is to the height of the peak of brazing layer from the electrode bottom of semiconductor device 7.In the measurement of having climbed height h of brazing layer 54, with brazing layer 54 heating, under each junction temperature, semiconductor element is engaged, measure the height of having climbed of brazing layer 54 at this moment by light microscope or scanning electron microscope.
The measurement result of height h has been climbed in the soldering of table 7 expression embodiment 9 and comparative example 7,8.
[table 7]
Figure G2009101680478D00501
As shown in Table 7, in embodiment 9,, can engage since 270 ℃ making junction temperature when changing for 220～315 ℃.245,270,295,315 ℃ soldering climbed the height h be respectively 0.9 μ m, 1.5 μ m, 4.8 μ m, 8.7 μ m.
On the other hand, under the situation of comparative example 7, can engage since 245 ℃ as can be known, it is respectively 8.2 μ m, 9.1 μ m, 9.1 μ m, 9.4 μ m that height h has been climbed in 245,270,295,315 ℃ soldering.Because the brazing layer 54 of comparative example 7 is uniform compositions, so under any temperature of 245～315 ℃, compare with embodiment 9, soldering has been climbed height h and has all been become big.
In addition, under the situation of comparative example 8,,, just can not engage if do not reach 290 ℃ so fusing point is higher because the Ag that brazing layer is formed amount is more.And 295,315 ℃ soldering has been climbed height h and has been respectively 0.5 μ m, 8.2 μ m as can be known.
Submount and soldered joint semiconductor element to embodiment 9 and comparative example 7,8 describes.
In order to investigate soldered joint intensity, after brazing layer 54 fusions of heater,, engage the back cooling to make sample from upper bond semiconductor element 7 with Submount 50, estimate with the band disbonded test of band and the observation of peeling off state.The band disbonded test is identical with the method for generally using in the adhesion strength of metal is measured, and the band of use adopts the band with certain bonding force.With that the electrode peeled off has taken place is bad as engaging because of the band disbonded test in the electrode of the semiconductor element 7 that engages, with the ratio of bad number as engagement state.As semiconductor element 7, the light-emitting diode that uses electrode to have the square size of 300 μ m, sample number all is each 100 in embodiment 9 and comparative example 7,8.
As shown in Figure 8, in embodiment 9, be under 220 ℃ and 245 ℃ at junction temperature, band is peeled off rate and is respectively 97% and 19%, does not take place but peel off rate from 270 ℃ to 315 ℃ band at each temperature.
In addition, in comparative example 7, being with under junction temperature is 220 ℃ and peeling off rate is 97%, does not take place but peel off rate from 245 ℃ to 315 ℃ band at each temperature.On the other hand, in comparative example 8, junction temperature be 225 ℃ and 245 ℃ down band to peel off rate be 100% and can not engage, under 270 ℃ and 295 ℃, be respectively 95%, 35%, be 0% under 315 ℃, promptly can not have band and peel off rate ground and engage.
[table 8]
Figure G2009101680478D00511
According to the foregoing description 9 and comparative example 7,8, in Submount 50, in order to engage light-emitting diode 7 composition of brazing layer 54 is changed on depth direction, making it have uneven composition distributes, allowing that junction temperature reaches under 315 ℃ the situation, can engage between 270～315 ℃ 45 ℃ temperature range in embodiment 9.In comparative example 7, between 245～315 ℃ 70 ℃ temperature range, can engage, with respect to this, in comparative example 8, can only engage down at 315 ℃.In addition, under the situation of embodiment 9, it is littler than the situation of comparative example 8 and comparative example 9 to make under not with arbitrary junction temperature of peeling off soldering climb height h.Particularly, be that it is 1.5 μ m that height h has been climbed in the soldering of embodiment 9, with respect to this, is about about 9 μ m in comparative example 8 under 270 ℃ the situation at junction temperature.
Like this, in embodiment 9, can enlarge the junction temperature scope of semiconductor element 7 and brazing layer 54, and, if be made as the low temperature that can engage, then compare and can reduce soldering and climbed highly h with comparative example 7.
The present invention is not limited to the described light-emitting diode of the foregoing description, the DH structure of GaAs-GaAlAs class, chip structure, packaging structure, so long as the semiconductor device that has the semiconductor device of backplate or have a Submount just can be suitable for, can carry out various changes in the described invention scope of claims, these changes are also contained in the scope of the present invention certainly.For example, the combination and the composition thereof of alloy material are not limited to Au-Sn, and in addition, the uneven composition of alloy distributes and is not limited to the Ag-Sn of embodiment.Semiconductor device is not limited in the light-emitting diode that uses base (stem), obviously can use in having adopted various lead frames and mounted on surface package semiconductor device.

Claims (6)

1, a kind of Submount, it is to cover brazing layer on the Submount substrate, thereby comes the Submount of bond semiconductor element by described brazing layer, it is characterized in that,
The ratio of components that constitutes the element of described brazing layer changes on the depth direction of brazing layer.
2, Submount as claimed in claim 1 is characterized in that, the ratio of components of described brazing layer changes on the depth direction of brazing layer, so that it is lower than the fusing point of its rear side to engage the fusing point of face side of described semiconductor element.
3, Submount as claimed in claim 2 is characterized in that, the fusing point of the face side of described brazing layer is bigger than 10 ℃ with the difference of the fusing point of rear side.
4, as each described Submount in the claim 1～3, it is characterized in that the material that constitutes described brazing layer is to comprise at least a above metal material among Au, Ag, Cu, Zn, In, Bi, Fe, Pb, Ti, Al, Sb and the Ni and the alloy of Sn.
5, Submount as claimed in claim 1 is characterized in that, the material that constitutes described Submount substrate is any in aluminium nitride, carborundum and the silicon.
6, a kind of manufacture method of Submount, thus it is to be constituted the brazing layer that element constitutes and covered the manufacture method that on the Submount substrate semiconductor element is bonded on the Submount on the described brazing layer by multiple, it is characterized in that,
Form described brazing layer by following mode: every kind by the evaporation brazing layer constitutes element so that ratio of components changes on the depth direction of brazing layer.
CN 200910168047 2005-03-18 2006-03-17 Submount and method for manufacturing same Expired - Fee Related CN101656236B (en)

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