CN101652853A - 用于电路装置的钝化层及其制造方法 - Google Patents
用于电路装置的钝化层及其制造方法 Download PDFInfo
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- CN101652853A CN101652853A CN200880011449A CN200880011449A CN101652853A CN 101652853 A CN101652853 A CN 101652853A CN 200880011449 A CN200880011449 A CN 200880011449A CN 200880011449 A CN200880011449 A CN 200880011449A CN 101652853 A CN101652853 A CN 101652853A
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- dielectric layer
- electronic device
- substrate surface
- circuit arrangement
- parylene
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Abstract
根据本发明的一个实施例,一种用于钝化电路装置的方法大体上包括:提供具有衬底表面的衬底;在所述衬底表面上形成电子器件;用第一电介质层覆盖所述衬底表面和电子器件。所述第一电介质层由总体上防潮材料制成,该防潮材料的湿气渗透率小于0.01克/平方米/天、吸湿性小于0.04%、介电常数小于10、介电损耗小于0.005、击穿电压强度大于8百万伏/厘米、表面电阻率大于1015欧姆-厘米、缺陷密度小于0.5/平方厘米。
Description
技术领域
本发明总体上涉及电路装置和电路板,更具体地,涉及一种用于电路装置和/或电路板的钝化系统及其制造方法。
背景技术
具有一体地形成于衬底上的电子器件的电路装置已经被广泛接受了,因为其可以提供广泛的应用。这些电路装置的应用可包括在受保护环境中的操作不容易进行、成本高和/或限制系统性能的应用。对于这些应用,可使用钝化技术使得所述其间的电气性能得到改进并且可保护电路装置的器件免受例如潮湿、湿气、颗粒物或离子杂质(诸如由含钠、氯的气体、元素或化合物所产生)。这些技术不再需要高成本的密封包装或封装并允许在附近对电路功能进行封装,从而可具有更高的封装密度、重量更轻和更高的频率性能。
发明内容
根据本发明的实施例,一种用于使电路装置钝化的方法总体上包括:提供具有衬底表面的衬底,该衬底表面上形成有电子器件;和将第一电介质层覆盖在所述衬底表面和所述电子器件上。所述第一电介质层由总体上防潮材料制成,该防潮材料的湿气渗透率小于0.01克/平方米/天、吸湿性小于0.04%、介电常数小于10、介电损耗小于0.005、击穿电压强度大于8百万伏/厘米、表面电阻率大于1015欧姆-厘米。
根据本发明的另一实施例,一种电路装置总体上包括衬底和第一电介质层。所述衬底具有衬底表面,该衬底表面上形成有至少一个电子器件。第一电介质层由总体上防潮材料制成,该防潮材料的湿气渗透率小于0.01克/平方米/天、吸湿性小于0.04%、介电常数小于10、介电损耗小于0.005、击穿电压强度大于8百万伏/厘米、表面电阻率大于1015欧姆-厘米。
本发明的这些实施例可提供多个技术优点。一些、一个或所有实施例可具有下列优点。根据一个实施例,提供一种系统和方法,使得具有在不同处理步骤期间形成于衬底上的电子器件或其它器件的电路装置具有钝化作用。为介电应用提出的技术使得在一些实施例中衬底或晶片上的绝对厚度得到精确控制并且保证厚度均匀性,同时在三维特征上具有高级正形性(superior conformality)。对厚度精确控制导致高级电气性能和高级的防潮性和防污性。使用所提出的技术不再需要传统的密封封装技术和包装,还改进了密封和非密封应用中的性能和可靠性。
其它技术优点对于本领域技术人员是显然的。
附图说明
从结合附图进行的详细说明,将对本发明的实施例具有更完整的理解,其中:
图1是根据本发明的教导的一体化地结合有钝化系统的电路装置的一个实施例的侧视图;
图2是示出执行几个步骤以制造图1的实施例的流程图;
图3是本发明的多个晶片级实施例的汇总表;
图4A到4D是在制造图1的电路装置的各个步骤期间所示出的视图,所述电路装置可根据本发明的教导制造;
图5A和5B是用于本发明的电路组件的钝化层系统的一个实施例的剖视图;
图6是示出执行几个步骤以制造图5A和5B中的实施例的流程图;
图7是本发明的某个组件级实施例的汇总表;和
图8是具有根据本发明另一实施例的钝化系统的晶体管的部分放大视图。
具体实施方式
参见附图,图1示出了根据本发明的教导构造的电路装置10的一个实施例。电路装置10总体上包括具有衬底表面14的衬底12,多个电子器件16一体地形成于衬底表面14上。图1的衬底12可由适于制造电路装置10的任何半导体材料形成,例如可以是硅(Si)、砷化镓(GaAs)、氮化镓(GaN)、锗(Ge)、碳化硅(SiC)或磷化铟(InP)。所述材料的每一种都可设置在总体上平坦的表面14中,电子器件16可形成于表面14上。
电子器件16可包括可形成于衬底表面14上的任意元件,其例如为晶体管、电容器、电阻、电感等。在所示出的具体实施例中,电子器件16可以是多个晶体管16a、电容器16b和电阻16c;然而,电路装置10可包括其它类型的电子器件,不会偏离本发明的教导。在一个实施例中,晶体管16a可以是分别具有源极区S、栅极区G和漏极区D的假晶高电子迁移率晶体管(pHEMT)装置。空气桥18a示出为连接每个晶体管16a的源极区S。另一空气桥18b设置为用于电容器16b的电连接。空气桥18a和18b在这里可以被称为附加器件18。附加器件18可指代出于多种目的与器件16重叠的任何合适元件,所述目的例如但不限于,器件16的电连接、热传导和/或结构加强。
与衬底表面14和电子器件16重叠的是第一电介质层22、第二电介质层24和第三电介质层26。如下详细所述,第一电介质层22、第二电介质层24和第三电介质层26可操作为使衬底12和器件16及18对于例如潮湿、湿气、颗粒物、腐蚀性材料或离子杂质(诸如钠、钾、氯)钝化。
电路装置的已知实现方式通过直接在电子器件上和衬底表面上设置电介质层从而为电子器件提供了对于有害污染物的钝化。该电介质层可由绝缘材料形成,例如氮化硅(Si3N4)或二氧化硅(SiO2)。然而,这些公知的介电材料在防潮性方面总体上小于预期。从而,氮化硅材料的使用需要较厚的一层从而为未受保护的环境中或未密封环境中使用的电路装置提供合适的保护。该方法的问题在于尽管材料的厚度较大,电路组件还是只能达到中等的钝化。此外,较大的厚度可能会不利地影响电路装置的性能,因为所述装置的活性区域(例如晶体管的源极S、栅极G和漏极D)之间的节间电容将会增大。此外,较厚一层的氮化硅或其它传统电介质导致应力较大,这可能会导致装置或电介质断裂、分层和/或压电效应,降低装置的性能。
作为防潮的厚氮化硅的替代方式,已经提出了多种方法,所述方法使用具有例如碳化硅的化学气相沉积(CVD)或氧化铝的原子层沉积(ALD)材料的第二或第三钝化层,随后是一层二氧化硅。在第一层氮化硅的顶部上使用额外的碳化硅或ALD保护层进一步增大了与下层的氮化硅有关的节间电容从而降低装置的性能。而且,氮化硅和/或碳化硅仍然可能随着时间而受到腐蚀,因为其具有很大的吸湿性。
还公知第一电介质层22可为栅极区提供对于后续处理步骤中可能会出现的电子陷阱和污染物的保护。因此,在栅极制成之前和/或之后马上应用第一电介质层22。因而,后续的制造步骤(例如空气桥18和RF以及DC导体的形成或连接)可能会留下露出的金属线,这些金属线可能会由于颗粒物、电化学或电镀腐蚀而短路。提出来解决这些露出的金属线的潜在腐蚀问题的方法已经包括氮化硅或碳化硅的化学气相沉积。与传统的化学气相沉积处理相关的一个问题可能是与电介质覆盖层有关的视线沉积(line-of-sight deposition)。因而,空气桥下的区域可能并未合适地覆盖并从而容易在存在湿气时受到腐蚀或者形成泄漏电流。此外,第二保护层的氮化硅和/或碳化硅可能易于因湿气而降低性能。在氮化硅层上使用原子层沉积涂层将会在三维表面特征上提供保性,但是,如前所述,其也将会增大节间电容,并降低装置的性能。某些实施例,例如高性能微波和毫米波单晶片微波集成电路可能并不能容忍射频,(RF)性能有明显降低。
在本发明的一个实施例中,电介质层22和24可设置为实现湿气防渗透材料优于已知介电材料的防潮性能。在具体实施例中,电介质层22和24可设置为实现湿气防渗透材料,其具有优于已知介电材料的击穿电压特性。即,使用具有较高击穿电压特性的材料可能会允许电介质层22和24形成为薄于传统所使用的厚度从而实现类似的击穿电压性能。由于这些特性,明显薄于已知钝化系统的一层介电材料可沉积在电子器件16、附加器件18和衬底表面14上,从而提供防潮和防污染的钝化作用。
在一个实施例中,第一电介质层由总体上防潮材料制成,该防潮材料的湿气渗透率小于0.01克/平方米/天、吸湿性小于0.04%、介电常数小于10、介电损耗小于0.005、击穿电压强度大于8百万伏/厘米、表面电阻率大于1015欧姆-厘米。在具体实施例中,第一电介质层22可由氧化铝(Al2O3)形成。铝可以以连续的方式沉积为较薄的一层。在另一实施例中第一电介质层22可由其它材料形成,例如高密度氮化硅、氧化钽、氧化铍和氧化铪。
在具体实施例中,第一电介质层22由铝形成并且具有位于50到2000埃的范围内的厚度。在此厚度范围内,第一电介质层22可为电路装置10提供合适的防潮保护,而不会对电子器件16的表观电容带来不利的影响。在一个实施例中,该层的厚度可以精确地控制为保持根据多个实施例构造的多个电路装置10的可重复性能。
第二电介质层24可操作为使附加器件18钝化。第二电介质层24的应用为并未由第一电介质层22所钝化的附加器件18提供了钝化。在附加器件18为空气桥的具体实施例中,在形成空气桥之前应用第一电介质层22对于第一电介质层22的厚度提供了精确的控制,第一电介质层22可能在随后的空气桥的形成期间限定空气腔20。此外,第二电介质层24可为第一电介质层22的可能会由其它处理步骤(例如锯、划线槽等)不利地损坏的部分提供钝化或者提供与其它装置的互连件。
第二电介质层24可由同样的介电材料制成,但是在一些实施例中,可由上面针对第一电介质层22描述的介电材料制成。在其它实施例中,第二电介质层24还可由下面针对第三电介质层26描述的任何材料制成。在一个实施例中,第二电介质层24可具有位于50到2000埃范围内的厚度。下面针对图3更详细地描述其它具体实施例。
尽管铝可以防潮,其表面在湿度较大和/或冷凝的湿气时可能会出现化学腐蚀。从而,可提供第三电介质层26。第三电介质层26可由对于较大湿度、湿度长期有和/或冷凝湿气和蒸汽渗透的情形化学稳定的任何材料制成。在一个实施例中,第三电介质层26可由二氧化硅(SiO2)形成。在其它实施例中,第三电介质层26可由聚对二甲苯形成。聚对二甲苯C、聚对二甲苯F(poly-tetrafluoro-p-xylylene)、芳香氟化(aromatic fluorinated)VT-4、聚对二甲苯(特殊涂层系统公司的商标)或其它氟化聚对二甲苯类的膜可防止湿气到达第一电介质层22和/或第二电介质层24并可用于第三电介质层26。与其它聚对二甲苯相比,这些材料可展示极强的阻湿特性并在较大的温度范围内保持功能稳定性。这些材料不会由于暴露于高温而出现大的薄膜应力(film stress)。这些材料还可具有比二氧化硅更低的介电常数。在一个实施例中,第三电介质层26可具有位于100到1000埃范围内的厚度。除了这些聚对二甲苯材料,具有下面描述的用于针对图5的层156或158的任何材料均可用于第三电介质层26。
从而,电路装置10的钝化可由第一电介质层22、第二电介质层24和可选的第三电介质层26提供。这些层22、24和26中的每一层均可足够薄从而不会不利地影响电路装置10的操作性能,同时提供对于包括湿气的气体、液体和固体污染物合适的保护。
图2示出一组步骤,可执行所述步骤来根据本发明制造电路装置10的一个实施例。在步骤100中,开始用于提供电气和环境保护涂层系统的方法。在步骤102中,可使用已知的集成电路处理在衬底表面14上形成一个或多个电子器件16。在步骤104中,可在衬底表面14和电子器件16上沉积第一电介质层22。在一个实施例中,第一电介质层22可具有位于50到2000埃范围内的厚度。第一电介质层22可包括如上所述的某些材料。
步骤106到110可提供一种用于在电路装置10上形成一个或多个附加器件18的方法。在步骤106中,为了提供用于安装附加器件18的接触表面,可将第一电介质层22的选定表面从电路装置10蚀刻掉。接下来在步骤108中,在这些接触表面上形成一个或多个附加器件18。第二电介质层24然后可沉积在第一电介质层22上和已经于步骤110中形成于电路装置10上的任何附加器件18上。在一个实施例中,第二电介质层24可具有位于50到2000埃范围内的厚度。从而,第一电介质层22和第二电介质层24的总厚度可位于100到4000埃范围内。
在一个实施例中,在步骤112中,黏附促进剂可施加在第二电介质层24上从而提高第三电介质层26与第二电介质层24之间的粘附力。在一个实施例中,黏附促进剂可以是单独使用或结合Y-氯丙基三乙氧基硅烷(gamma-methacryloxypropyltrimethoxysilane)使用的一层二氧化硅;然而,也可使用其它黏附促进剂。第三电介质层26然后可在步骤114中施加在第二电介质层24上。在一个实施例中,第三电介质层26的厚度可位于100到1000埃的范围内。
在步骤116中,完成用于应用钝化层的方法,然后可使用电路装置10。步骤100到116描述了用于制造电路装置10的方法的实施例,其中,在多个处理步骤中应用电介质层22和24。通过使用该方法,可方便地对与空气腔20中的电子器件16相邻的第一电介质层22的厚度进行控制。通过在形成附加器件18(例如空气桥)之前应用第一电介质层22,通过使用本领域中已知的多种沉积技术可以方便地控制靠近电子器件16的第一电介质层22的厚度。
图3是对本发明的可以提供与已知的钝化系统相比更好的电气性能和增强的环境保护的多个实施例1到5的汇总表。实施例1到5每个都示出了可用于制造第一电介质层22、第二电介质层24和第三电介质层26的各种材料组合(例如铝、二氧化硅和/或聚对二甲苯F、芳香氟化VT-4、聚对二甲苯或其它氟化聚对二甲苯类的膜)。
如上针对图1所述,实施例1到5中的第一电介质层22可由总体上防潮材料制成,该防潮材料的湿气渗透率小于0.01克/平方米/天、吸湿性小于0.04%、介电常数小于10、介电损耗小于0.005、击穿电压强度大于8百万伏/厘米、表面电阻率大于1015欧姆-厘米。在一个具体实施例中,第一电介质层22由铝形成,与其它已知材料(例如标准的氮化硅或二氧化硅)相比,其具有较低的湿气渗透率、较小的离子迁移率和较高的击穿电压强度特性。第一电介质层22可由多种沉积处理制成,例如物理气相沉积(PVD)、化学气相沉积(CVD)和原子层沉积。可使用原子层沉积,因为其提供了较精确的厚度控制、衬底表面14和器件16和18上较好的均匀度,并消除了在电介质层沉积器件的物理或辐射产生的损害。
如上针对图1所述,根据指定装置和/或组件的封装方法,可增加其它介电保护层。电介质层22、24和26的厚度也可随着装置设计、操作频率和性能需求而变化。图3中示出的实施例1到5可以特别适用于射频(RF)集成电路,其例如可包括场效应晶体管(FET)(包括假晶高电子迁移率晶体管(pHEMT))和双极晶体管(例如异质结双极晶体管(HBT)。一般地,较小的电介质层厚度提高与介电载荷效应相关的装置性能(例如节间电容),增大集成电容器单位面积内的电容从而减小电容器尺寸。较大的电介质层厚度减小湿气渗透率并提高对于颗粒物、物理产生的损害、离子杂质和无论固相、液相还是气相的腐蚀性污染物的保护。图3中示出的电介质层22、24和26的厚度可以适应于射频(RF)集成电路,其中,节间电容的控制和介电载荷效应的控制对于电路性能都较为重要。也可根据本发明的公开选择材料和厚度的其它组合。
图3的实施例1仅使用了由铝制成的第一电介质层22。实施例1可提供增强的电气性能,因为其单个电介质层的节间电容最小,同时为图1的晶体管16a的源极区S、栅极区G和漏极区D提供了电气、物理和环境保护。实施例1还可在密封或非密封环境下提供与已知材料(例如氮化硅或二氧化硅)相比更强的电气性能。因为可使用与传统氮化硅或二氧化硅相比更薄的电介质层,所以可以提供更强的性能。实施例1在系统级对温度和/或湿度进行部分控制的环境中也是有利的,对温度和/或湿度进行部分控制最小化甚至消除活性电路上的水凝和/或最小化甚至消除活性电路暴露于高温或湿气的情形从而延长使用时间。在系统级通过除湿器或干燥剂进行湿度控制可实现这种保护。
实施例2提供了由铝形成的第一电介质层22和第二电介质层24。第二电介质层24覆盖了未受保护的附加器件18(例如空气桥和金属线),其可能在第一电介质层22形成后才形成。实施例2在密封的或较不严重的潮湿环境中也可以是有利的,在所述环境中可能会出现对于导电或腐蚀性固体、液体或气体材料的保护。
实施例3和4提供了可由如上所述的二氧化硅、聚对二甲苯F聚对二甲苯或其它氟化聚对二甲苯类的膜制成的第三电介质层26。由二氧化硅、聚对二甲苯F、聚对二甲苯或其它氟化聚对二甲苯类的膜制成的第三电介质层26为第一电介质层22和第二电介质层24提供对于可能会击穿第一电介质层22和/或第二电介质层24并暴露下层器件16和18的大湿度、湿度较长和/或冷凝湿气的保护。聚对二甲苯F或聚对二甲苯可具有小于二氧化硅的介电常数,并从而对于电气性能具有较小的影响。聚对二甲苯F或聚对二甲苯与ALD沉积二氧化硅类似,能够气相沉积并高度保形地渗透到最小凹陷中并可以在空气桥和其它大高宽比凹陷的附加器件18之下以较为均匀的厚度施加。由铝制成的第一电介质层22和/或第二电介质层24还可用作黏附促进剂,因为聚对二甲苯F、聚对二甲苯甚至与黏附促进剂一样可良好地粘到许多表面上。如上所述,黏附促进剂可在沉积第三电介质层26之前施加到第二电介质层24上。黏附促进剂可以是能够提高第三电介质层26的粘性的任何合适材料,并且在一个具体实施例中,是单独使用或结合Y-氯丙基三乙氧基硅烷使用的一层二氧化硅。二氧化硅提供了用于粘接到例如Y-氯丙基三乙氧基硅烷的黏附促进剂的理想表面,并良好地粘接到铝和聚对二甲苯F或聚对二甲苯
实施例5使用聚对二甲苯F或聚对二甲苯作为图1的第二电介质层24。聚对二甲苯F或聚对二甲苯覆盖了未受保护的其它特征(例如空气桥和厚金属线),所述特征可能在第一电介质层22形成后才形成。聚对二甲苯F或聚对二甲苯还可保护下层的第一电介质层22免受湿气冷凝的渗透或腐蚀。聚对二甲苯F或聚对二甲苯的优点在于与二氧化硅或其它无机材料相比具有较小的介电常数并且低于大多数有机材料。
图4A到4D是示出根据本发明的教导制造电路装置40的各个阶段期间的截面图。电路装置40大体上与图1中的电路装置10相同。在图4A中,具有衬底表面44的衬底42示出为具有栅极凹陷、用于多个晶体管指部(finger)46a的栅极金属、用于电容器46b的底盖和电阻器46c。隔离注入事先已经完成以形成用于晶体管46a和电阻46c的活性槽区域48。如上结合图1所述,在一个实施例中,晶体管46a可以是假晶高电子迁移率晶体管(pHEMT)。图4A的电子器件46和相关衬底42可以根据图2的步骤100制造。
图4B示出图4A的电路装置40,其中第一电介质层50已经根据步骤102施加。如图可见,每个电子器件46可能会暴露于总体上的视线沉积,从而允许第一电介质层50具有均匀的沉积厚度。即,访问电子器件的特征一般不会遇到例如空气桥54的其它装置。
图4C示出电路装置40的结果,在其上对图4B的电路装置40执行步骤104到108。接触表面52可通过从第一电介质层50蚀刻掉一部分而形成,用于安装附加器件54(例如空气桥)。空气桥可用于制造到源晶体管指部46a的平行连接从而增大输出功率并用于制造到电容器46b的顶板的连接。
图4D示出图4C的电路装置40,其中已经根据步骤110到114应用了第二电介质层56和第三电介质层58,以钝化衬底表面44、电子器件46和附加器件54。从而,提供一种系统和一种方法,使得具有附加器件54的电路装置40可以有效地密封免受有害污染物的影响,同时不会牺牲电路装置40的性能。
图5A和5B示出电路板组件160的一个实施例,其可以根据本发明的教导的另一实施例来钝化。电路板组件160一般包括电路装置140和几个安装到电路板161的分开的电子器件164和170。电路板组件160还可具有几个组件级的特征,包括板迹线162和无线互连件166,其提供电路装置140与电子器件164和170之间的电气连接。电路板组件160上的是电介质层156和第二电介质层158。电路装置140具有电介质层150,电介质层150在装配到电路板上之前在装置制造器件施加。如下所述,通过在制造的组件级阶段应用第二电介质层156和/或第三电介质层158,钝化可在制造的组件级为电路板组件160的电路装置140与电子器件164和170提供保护。
电路板161可以是任何合适的装置,其中多个分开的电子器件164和170可以安装在其上。一般地,电路板161的结构可以是刚性或柔性衬底,从而以固定的物理相互关系固定分开的电子器件164和170。在一个实施例中,电路板161具有总体上平坦形状的外表面168,其上可使用粘合剂172(例如各向同性导电粘合剂)或焊料安装分开的电子器件164和170以及电路装置140。电路板161还可具有由导电材料形成的板迹线162,用于使得分开的电子器件164和170彼此互连件和/或连接到电路装置140。电路装置140可以类似于图1的电路装置10和图4A到4D的电路装置40。
分开的电子器件164和170是指彼此单独制造的电子器件。即,每个分开的电子器件164或170可以在衬底上根据具体的处理制造,所述具体的处理可以与设置在电路板组件160上的其它分开的电子器件不同。分开的电子器件的例子包括但不限于电阻、电容器、电感、二极管、晶体管等。
电路装置140和分开的电子器件164和170可以在电路板161上通过使用板迹线162和/或互连件166彼此电连接以产生任何所需的效果。电路装置140和分开的电子器件164和170可在制造的装配阶段设置在电路板161上。电路装置140可如上针对图1的第一电介质层22和/或第二电介质层24所述由第一电介质层150和/或第二电介质层156所覆盖。
在多数情形中,在晶片级的制造后,电路装置140的其它处理技术也是有利的。例如,电路装置140可由晶片通过使用锯或其它切割工具切断,其中可能会形成划线槽。从电路装置140到器件164的互连件166可能在组件级形成,可能会产生例如如上所述的有害的污染物。从而,在划线槽、装置边缘和互连件166中缺少电介质层保护可能导致电路装置140容易受到湿气腐蚀、颗粒物或其它污染物。
电路板161还可能需要环境保护以在非密封封装中和/或不能合适地控制物理颗粒物的情形中可靠地执行。已知的钝化系统使用一层较厚的聚对二甲苯C、D或N,其厚度可能例如为10微米(100,000埃)或更大。对于微波和毫米波电路,这层较厚的聚对二甲苯可能并不满意,其中,介电载荷可能会改变和/或降低电路性能。聚对二甲苯C、D或N不可能很好地承受高温。在高功率装置可能暴露于其中的高温环境中,可能会增加聚对二甲苯C、D或N的结晶度。结晶度增加会增大聚对二甲苯膜中以及聚对二甲苯与电路板组件160的界面中的应力。这种应力增大可能导致聚对二甲苯分层,从而导致失效或性能降低。
本发明的一个实施例提供了在制造的组件级而不是晶片级阶段第二电介质层156和/或第三电介质层158的应用。通过结合晶片级覆盖以及组件级覆盖,组件级的特征(例如分开的电子器件164和170、电路装置140、板迹线162、金属互连件166、划线槽、小片边缘)和到电路板组件160的外部互连件(例如线或带式连接器)以及其它组合器件都能够同时被覆盖。而且,通过使用本发明的某些实施例,所需电介质层厚度在许多情形中可能是使用聚对二甲苯、二氧化硅或氨甲酸乙酯涂层的已知钝化系统的大小低两个量级以上。在某些实施例中,这种减小的厚度从而可能使电路性能的降低最小化。
根据一个实施例,第二电介质层156和/或第三电介质层158可以涂上一层介电材料,其弹性模量小于3.5Gpa、介电常数小于3.0、介电损耗小于0.008、击穿电压强度大于2百万伏/厘米、温度稳定性为300℃、无孔膜大于50埃、憎水接触角大于45°、并能够在3D结构之上或之下保形沉积的厚度均匀性小于或等于30%。该介电材料可以在制造的组件级阶段施加,以使电路板161、板迹线162、电路装置140、分开的电力期间164和170以及组件级特征对于环境钝化。该介电材料可以作为第二电介质层156或第三电介质层158施加。该介电材料一半对于气态或液态水化学稳定,从而保护第一电介质层150和/或第二电介质层156。该介电材料相对于上述其它已知的钝化材料具有极佳的阻潮性能并且在较大的温度范围内功能上稳定。该介电材料还具有比其它已知钝化材料更小的本征介电常数。在一个实施例中,第三电介质层26可具有位于约100到1000埃范围内的厚度。在一个实施例中,该介电材料是聚对二甲苯F、芳香氟化VT-4、聚对二甲苯或其它氟化聚对二甲苯类。
该实施例的涂层材料可以承受比使用聚对二甲苯C、D或N的已知钝化系统更高的温度,从而在暴露于极限温度时性能不像已知系统那样迅速降低。附加的组件级电介质层还可对活性装置区域增加额外的保护。通过适当地选择在制造的晶片级施加的第一电介质层150以及在制造的组件级施加的第二电介质层156和/或第三电介质层158,电路板组件160的钝化可适于多种应用。
此外,第一电介质层150由铝、氧化钽、氧化钡、氧化铪或高密度氮化硅以及这些材料与二氧化硅的奈米级夹层膜(nanolaminate)形成、从而根据本发明的教导通过控制奈米级夹层膜层或其它合适材料的厚度而调节介电常数,第一电介质层150能够延迟锡晶须生长,锡晶须生长是与使用低铅焊接方法有关的内在问题。锡晶须生长与湿气的出现以及可能由湿气更加恶化的应力条件有关。
图6示出一组步骤,可执行所述步骤以制造针对图5A和5B示出并描述的电路装置160的一个实施例。在步骤200中,开始用于提供电气和环境保护涂层系统的方法。在步骤202中,一个或多个电子器件146可使用已知的集成电路制造处理形成于衬底142上。在步骤204中,第一电介质层150和/或第二保护156可以沉积在衬底142和电子器件146上。步骤202和204描述了可在制造的晶片级阶段执行的步骤。
步骤206到214描述了可在制造的组件级阶段执行的步骤。在步骤206中,电路装置142可安装到电路板161上。在步骤208中,一个或多个分开的电子器件164和170和/或一个或多个组件级特征(例如互连件166)可形成于电路板161上。此外,其它电路特征(例如划线槽或小片边缘)也可形成于电路装置140上。
在步骤210中,第二电介质层156和/或第三电介质层158然后可分别沉积在第一电介质层150和/或第二保护156以及已经形成于电路板组件160上的任何分开的电子器件或组件级特征上。在一个实施例中,第二电介质层156或第三电介质层158可由聚对二甲苯F或聚对二甲苯制成。在一个具体实施例中,其中第二电介质层156和/或第三电介质层158由聚对二甲苯F或聚对二甲苯制成并与由铝制成的下层相邻,黏附促进剂可施加在第二电介质层156和第三电介质层158之间。在其它实施例中,黏附促进剂可以是单独使用或结合Y-氯丙基三乙氧基硅烷使用的一层二氧化硅。
在步骤212中,已经完成施加钝化层的方法,从而接着可使用电路板组件160。
图7示出多个实施例1a到2c,其中,示出了可以在制造的晶片级阶段和组件级阶段施加的第一电介质层150、第二电介质层156和第三电介质层158的各种组合。实施例1a到2c使用了在制造的晶片级阶段形成的第一电介质层150。如上针对图3所述,第一电介质层150的材料和施加方法与图3的实施例1到5的类似。
图7的实施例1a、1b、1c、1d、1e具有在组件级沉积的第二电介质层156,因此,第二电介质层156可为在制造的组件级期间增加或修改的组件级特征提供保护。在制造的组件级期间增加或修改的组件级特征的例子包括衬底142的处理、电路板器件164和170的增加和形成互连件166。
实施例1a示出由铝制成的第二电介质层156。组件级的第二电介质层156的应用可提供与已知的有机电介质层相比增强的环境保护,因此可最小化在组件级增加的器件上的介电载荷效应。这种效应随着运行频率增大到微波和毫米波频率将变得更为重要。
实施例1b使用由聚对二甲苯F或聚对二甲苯制成的第二电介质层156并且不具有第三电介质层158。在此具体实施例中,可在施加第二电介质层156之前施加黏附促进剂。对于电路板组件160的操作,实施例1b可提供较小的电气冲击,因为聚对二甲苯F或聚对二甲苯的介电常数低。实施例1c使用了由二氧化硅制成的第二电介质层156并且不具有第三电介质层158。
实施例1d使用了由铝制成的第二电介质层156并且具有由聚对二甲苯F或聚对二甲苯制成的第三电介质层158。如前所述,铝层提供了对于电路组件160和对于聚对二甲苯F或聚对二甲苯较好的附着力,特别是结合黏附促进剂(例如单独使用或结合Y-氯丙基三乙氧基硅烷使用的一层二氧化硅)使用时。
实施例2a、2b、2c具有在晶片级施加的第一电介质层150和第二电介质层156以及在制造的组件级施加的第三电介质层158。使用该处理的某些实施例可提供的优点在于,所述装置在晶片级可电测量并且只有良好的小片才提供到组件级。
本发明的其它实施例包括由本领域公知的技术沉积的高密度(大于2.5克/立方厘米)和/或低含水量(小于15原子量百分比)氮化硅或二氧化硅膜的较薄的起始层,所述技术包括传统的化学气相沉积(CVD)、高密度等离子增强CVD技术(包括电子回旋加速器共振等离子增强CVD(ECR CVD)、电感耦合等离子增强CVD(ICPECVD)、高密度感应耦合等离子化学气相沉积(HDICPCVD)、活性磁控管反应溅射、热金属线化学气相沉积或使用无水前体气体的PECVD的沉积)。高密度和/或低含水量氮化硅本身可具有较高的击穿电压以及较强的防水渗透性。传统化学气相沉积或高密度等离子化学气相沉积技术的选择可基于电路板组件的装置结构。由氮化硅或二氧化硅制成的起始层在本领域中已经得到了良好的研发和定性,以减小电荷陷阱和其它表面界面缺陷。沉积在起始氮化硅或二氧化硅层上的第一电介质层将提供如上所述的改进的性能和保护效果。该实施例的例子在图8中示出。
图8是示出器件216的放大视图,在此具体情形中,其为一个场效应晶体管(FET)。器件216具有源极216s、栅极216g和漏极216d,其由气隙217彼此分开。为了实现优良的性能,气隙217由栅极凹陷和栅极几何形状的设计结合电介质层222和氮化硅制成的薄起始层221来保持。如此可见,第一电介质层222和薄起始层221的总厚度保持了气隙217,使得节间电容Cgs和Cgd可以减小。在一个具体实施例中,该钝化层包括氮化硅制成的厚度范围为25到400埃的薄层221、和铝制成的厚度范围为50到2000埃的低渗透层222。第一介电保护层222还可由如上所述与第一电介质层22相同的任何材料制成。
已经证明,氮化硅对于微波装置在装置稳定性方面是较好的特征电介质层。铝也已经证明在防潮和击穿电压方面是较好的电介质层。这两种材料的组合以及在本发明中描述的合适厚度和物理特性可产生优于已知钝化系统的增强的钝化系统。在一个实施例中,一薄层氮化硅可与奈米级夹层膜一起使用。奈米级夹层膜可包括铝和二氧化硅、铝和聚对二甲苯F、芳香氟化VT-4、聚对二甲苯或其它氟化聚对二甲苯类的膜或铝与丙烯酸的交替层。在其它实施例中,奈米级夹层膜可包括铝和气相沉积特氟龙(PTFE)以及丙烯酸单体的交替层。
特别是在较低温度条件下沉积和由原子层沉积时,氮化硅、二氧化硅和铝具有较低的介电常数。较低的介电常数还最小化了节间电容、已覆盖和未覆盖装置之间的性能变化,并导致了高频性能的改善。
其它材料也可替代根据本发明的教导的图1到8中示出的材料。可能适于这些应用的其它保护介电材料也可包括但不限于标准密度氮化硅、高密度氮化硅、氧化钽和氧化钡、氧化铪。
尽管本发明已经以几个实施例进行了描述,本领域技术人员可建议许多变化、改变、变换、转换和改进,并且本发明试图覆盖落入所附带的权利要求的精神和范围内的这些变化、改变、变换、转换和改进。
Claims (38)
1.一种用于制造集成电路的方法,包括:
提供具有衬底表面的衬底;
在所述衬底表面上形成电子器件,所述电子器件至少包括晶体管或电容器;
用由铝制成的第一电介质层覆盖所述衬底表面和电子器件,所述第一电介质层具有位于约50到2000埃范围内的厚度;
从所述衬底表面或所述电子器件蚀刻掉所述第一电介质层的一部分以形成接触表面;
在所述接触表面上形成空气桥;
用由铝制成的第二电介质层覆盖所述第一电介质层、所述电子器件和所述空气桥,所述第二电介质层具有位于约50到2000埃范围内的厚度;
将黏附促进剂施加到所述第二电介质层;和
2.如权利要求1所述的方法,其中,施加黏附促进剂的所述步骤包括施加由单独使用或结合Y-氯丙基三乙氧基硅烷使用的一层二氧化硅制成的黏附促进剂黏附促进剂。
3.如权利要求1所述的方法,其中,提供衬底的所述步骤包括提供由下列材料组成的组中选择的材料制成的衬底:硅(Si)、砷化镓(GaAs)、氮化镓(GaN)、锗(Ge)、碳化硅(SiC)和磷化铟(InP)。
4.一种方法,包括:
提供具有衬底表面的衬底;
在所述衬底表面上形成电子器件;和
用由总体上防潮材料制成的第一电介质层覆盖所述衬底表面和电子器件,该防潮材料的湿气渗透率小于0.01克/平方米/天、吸湿性小于0.04%、介电常数小于10、介电损耗小于0.005、击穿电压强度大于8百万伏/厘米、表面电阻率大于1015欧姆-厘米。
5.如权利要求4所述的方法,其中,用第一电介质层覆盖所述衬底表面和电子器件还包括用由铝制成的第一电介质层覆盖所述衬底表面和电子器件。
6.如权利要求5所述的方法,其中,用由铝制成的第一电介质层覆盖所述衬底表面和电子器件还包括用由铝制成的厚为50到2000埃范围内的第一电介质层覆盖所述衬底表面和电子器件。
7.如权利要求4所述的方法,其中,用第一电介质层覆盖所述衬底表面和电子器件还包括用由从高密度氮化硅、氧化钽、氧化钡、氧化铪和铝中选择的材料制成的第一电介质层覆盖所述衬底表面和电子器件。
8.如权利要求4所述的方法,还包括:
从所述衬底表面或所述电子器件蚀刻掉所述第一电介质层的一部分以形成接触表面;
在所述接触表面上形成空气桥;
用第二电介质层覆盖所述第一电介质层、所述电子器件和所述空气桥。
9.如权利要求8所述的方法,其中,所述第二电介质层由介电材料制成,所述介电材料的弹性模量小于3.5Gpa、介电常数小于3.0、介电损耗小于0.008、击穿电压强度大于2百万伏/厘米、温度稳定性为3000℃、无孔膜大于50埃、憎水接触角大于45°、并能够在三维(3D)结构之上或之下保形沉积的厚度均匀性小于或等于30%。
12.如权利要求8所述的方法,还包括用第三电介质层覆盖所述第二电介质层。
13.如权利要求12所述的方法,其中,用第三电介质层覆盖所述第二电介质层还包括用由聚对二甲苯制成的第三电介质层覆盖所述第二电介质层。
14.如权利要求12所述的方法,其中,用第三电介质层覆盖所述第二电介质层还包括用由二氧化硅制成的第三电介质层覆盖所述第二电介质层。
17.如权利要求15所述的方法,其中,用由铝、氧化钽、氧化钡、氧化铪或氮化硅制成的第三电介质层覆盖所述第二电介质层包括用由铝、氧化钽、氧化钡、氧化铪或氮化硅制成的厚为100到1000埃范围内的第三电介质层覆盖所述第二电介质层。
18.如权利要求12所述的方法,还包括,在用第三电介质层覆盖所述第二电介质层的步骤之前,将黏附促进剂施加到所述第二电介质层。
19.如权利要求17所述的方法,其中,施加黏附促进剂的所述步骤包括施加由单独使用或结合Y-氯丙基三乙氧基硅烷使用的一层二氧化硅制成的黏附促进剂。
20.如权利要求4所述的方法,还包括,在用第一电介质层覆盖所述衬底表面和电子器件的步骤之前,在所述衬底表面和电子器件上施加一层氮化硅或二氧化硅的起始层,所述氮化硅或二氧化硅的起始层具有位于25到400埃范围内的厚度。
21.如权利要求4所述的方法,其中,形成电子器件包括在所述衬底上至少形成晶体管或电容器。
22.如权利要求8所述的方法,其中,形成附加器件包括在所述衬底表面或所述电子器件上形成空气桥。
23.一种电路装置,包括:
具有衬底表面的衬底;
至少一个电子器件,其在所述衬底表面上形成;
形成于所述至少一个电子器件上的第一电介质层,所述第一电介质层由总体上防潮材料制成,该防潮材料的湿气渗透率小于0.01克/平方米/天、吸湿性小于0.04%、介电常数小于10、介电损耗小于0.005、击穿电压强度大于8百万伏/厘米、表面电阻率大于1015欧姆-厘米。
24.如权利要求23所述的电路装置,其中,所述第一电介质层由铝制成。
25.如权利要求23所述的电路装置,其中,所述第一电介质层厚约50到2000埃。
26.如权利要求23所述的电路装置,其中,所述第一电介质层由从高密度氮化硅、氧化钽、氧化钡、氧化铪和铝中选择的材料制成。
27.如权利要求23所述的电路装置,还包括形成于所述衬底上或者所述至少一个电子器件上的至少一个附加器件以及形成于所述衬底表面、第一电介质层和所述至少一个附加器件上的第二电介质层。
29.如权利要求27所述的电路装置,还包括在所述第二电介质层上形成第三电介质层。
30.如权利要求29所述的电路装置,其中,所述第三电介质层由聚对二甲苯制成。
31.如权利要求29所述的电路装置,其中,所述第三电介质层由铝、氧化钽、氧化钡、氧化铪或氮化硅制成。
32.如权利要求23所述的电路装置,还包括在所述衬底表面和所述第一电介质层之间形成起始层,所述起始层由从氮化硅和二氧化硅组成的组中选择的材料制成。
33.如权利要求23所述的电路装置,还包括设置在所述第一电介质层与所述衬底表面和电子器件之间的一薄层氮化硅,所述一薄层氮化硅具有位于25到400埃范围内的厚度。
34.如权利要求23所述的电路装置,其中,至少一个电子器件从由晶体管和电容器组成的组中选择。
35.如权利要求23所述的电路装置,其中,所述附加器件是空气桥。
36.如权利要求23所述的电路装置,还包括在所述第一电介质层和所述第二电介质层之间的黏附促进剂。
37.如权利要求36所述的电路装置,其中,所述黏附促进剂是Y-氯丙基三乙氧基硅烷。
38.如权利要求23所述的电路装置,还包括位于所述衬底表面和所述第一电介质层之间的一层氮化硅或二氧化硅的起始层,所述氮化硅或二氧化硅的起始层具有位于25到400埃范围内的厚度。
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CN103826671A (zh) * | 2011-06-02 | 2014-05-28 | 又荣医疗有限公司 | 具有升温功能的与血液透析、血液透析滤过、血液滤过或腹膜透析相关的装置 |
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IL223399A0 (en) | 2013-02-03 |
EP2118926A2 (en) | 2009-11-18 |
WO2008097724A3 (en) | 2008-11-20 |
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