CN1110855C - 半导体器件及其钝化方法 - Google Patents
半导体器件及其钝化方法 Download PDFInfo
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- 239000010410 layer Substances 0.000 title claims abstract description 94
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000012044 organic layer Substances 0.000 title claims abstract description 19
- 238000007789 sealing Methods 0.000 title claims description 5
- 238000002161 passivation Methods 0.000 claims abstract description 36
- 239000012212 insulator Substances 0.000 claims abstract description 23
- 230000007797 corrosion Effects 0.000 claims abstract description 14
- 238000005260 corrosion Methods 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000009413 insulation Methods 0.000 claims description 20
- 239000004642 Polyimide Substances 0.000 claims description 15
- 229920001721 polyimide Polymers 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 238000001020 plasma etching Methods 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 230000032798 delamination Effects 0.000 abstract description 14
- 239000002184 metal Substances 0.000 abstract description 8
- 238000005538 encapsulation Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229920002292 Nylon 6 Polymers 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 150000002466 imines Chemical class 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
一种无机封层及其制造方法,该无机封层供在集成电路器件钝化过程中密封有机层用。这种封层的结构可以在线绝缘层的所有平面后端(BEOL)中在反应离子腐蚀(RIE)边缘上形成无机/无机钝化封层。边封层的作用是防止钝化层从集成电路器件或导电环脱层。脱层会导致多条充满潮气的通道的形成和集成电路器件金属线路的腐蚀,从而使集成电路失灵。
Description
本发明总的说来涉及半导体的加工,更具体地说,涉及半导体加工成集成电路器件的过程中最后进行钝化的领域。
半导体圆片的加工可分成多组不同的工序,这些工序通常叫做:线路前端(FEOL);线路中间(MOL)和线路后端(BEOL)。圆片加工的BEOL工序组中最终工序的其中一道工序是在整个圆片上被覆上一层钝化保护层。钝化工序包括在整个集成电路(IC)器件上淀积一层钝化保护层。钝化层的作用是机械保护加工好的圆片在运输、搬运和最后封装过程中免受外部环境的影响。边封层是芯片有源区与切片通道之间易受潮而损坏的部位。受潮损坏会改变圆片上各IC芯片集成电路的电气性能,从而使器件失灵。最后,除去各钝化区,形成切片区,以便将圆片切割成一片片的IC芯片。
用硅绝缘表面上形成的诸如聚酰亚胺之类的有机绝缘层形成BEOL时,当这个聚酰亚胺钝化层因应力的作用而剥落(脱层)或在边封区裂开时,困难就来了。在最后加工圆片的聚酰亚胺钝化层的过程中,用象反应离子腐蚀(RIE)之类的方法腐蚀钝化层,使金属接地垫上的端子转接(TV)垫和边封通道区与硅绝缘体连通。边封通道是一些外露的硅绝缘层没有聚酰亚胺被覆着的部位,最后是要切割的。正是钝化层的这个无被覆层的边封通道成问题。举例说,聚酰亚胺钝化层用RIE腐蚀过的边缘,其吸收的水分量可能比大块聚酰亚胺钝化区多达15%,从而使各边缘膨胀,最后与硅绝缘体脱层。随着各边缘的脱层,钝化层与硅绝缘体之间产生毛细管似的分离现象,形成了潮气聚集的场所,使IC器件中形成一条条充满潮气的通道。这些通道使离子可自由运动,从而被吸入有源芯片区,不可避免地使IC器件内腐蚀,最终导致失灵。
迄今提出的保护钝化层腐蚀过的边缘使其不致因剥落或裂开而脱层的方法有各色各样。例如,一种方法提出在第一聚酰亚胺钝化层用RIE腐蚀过的边缘被覆上第二聚酰亚胺层,然后再湿法腐蚀第二聚酰亚胺层,使通道和TV垫再连通。这种方法的缺点是,(A)要花更多的时间,(B)费用大,(C)需要用额外的掩模来进行湿腐蚀,因而违反了电路布图的基本准则。因此,集成电路器件需要有一个钝化层经改进的边封区。
本发明包括一种埋置在象聚酰亚胺之类的有机钝化结构中的无机绝缘层,例如氮化物或氧化物,以及在无机绝缘体形成FEOL、MOL和BEOL层的方法。BEOL层制成象聚酰亚胺之类的有机钝化层。BEOL层被覆上一层象氮化物或氧化物之类的无机层,无机层最后再被覆上一层有机机械钝化层。机械钝化层经过腐蚀形成多个窗口,使BEOL金属垫和各区外露,形成多条切片通道。各BEOL层在金属垫和各切片通道区的边缘被覆上诸如氮化物或氧化物之类的无机绝缘体,从而形成BEOL有机聚酰亚胺的无机密封。
上述钝化层和边封层及其制造方法无需使用另外的掩模和湿腐蚀,因而比起现行的方法来,既省时又节约开支。此外,本发明的方法形成的边封层密度大,相比之下,采用湿腐蚀法时形成的边封层就要大得多。
从下面对最佳实施例的详细说明、附图和所附的权利要求书不难清楚了解本发明的许多其它优点和特点。
下面就本发明非局限性的一些实施例参照附图更详细地说明本发明的内容。附图中,同样的编号表示同样的元件,其中:
图1是集成电路(IC)器件结构的示意图,示出了平面钝化层与IC绝缘层脱层的情况;
图2是IC器件钝化之后在无机绝缘体上淀积有机层的示意图;
图3是图2的顶视图;
图4是IC器件在有机层上淀积无机层之后进行钝化的示意图;
图5是IC器件在无机层上淀积另一层有机层之后进行钝化的示意图;
图6是IC器件经过腐蚀限定端子转接(TV)垫和边封通道之后进行钝化的示意图;
图7是IC器件在淀积第二无机层之后进行钝化的示意图;
图8是IC器件在腐蚀之后进行钝化的示意图;
图9是IC器件在腐蚀之后进行钝化的另一个实施例的示意图。
本发明是就一些具体实施例详细说明的。然而,应该理解的是,这些实施例仅仅是举例说明而已,本发明并不局限于这些实施例。本领域的技术人员都知道,在不脱离下面权利要求书精神实质和范围的前提下是可以对上述实施例进行修改和更改的。应该理解的是,在谈到各层的相互关系时,“敷在其上”或“被覆状态”一词是指层叠着的各层位置彼此靠近,但可能彼此接触或不接触。举例说,如果第一层位于第二层“上”,则第三层可能安置在第一和第二层之间,也可能不安置在第一和第二层之间。应该理解的是,“层”一词可表示经各种加工工序形成的芯片区。
参看图1。本发明要谈的是导电环30、M3、S2、M2、S1、M1组成的钝化层10与诸如二氧化硅(SiO2)无机玻璃绝缘层20之类的无机层脱层11危害有源芯片的问题。此外,本发明还将谈到金属垫区M3、S2、M2、S1、M1中的脱层问题。参看图9。如果不设封层44,有机绝缘体45会与M3、40(与图1类似)脱层。
参看图3,图中示出了有源芯片9的顶视图。图2是芯片9沿图3中的A-A′线截取的剖视图。图2中,BEOL是用半导体工业中通常使用的多种方法中的任一方法形成的。金属层M3、M2、M1是在加工作为环绕有源芯片的金属“护环”30的柱形金属接头S2、S1的过程中形成的。
参看图4。诸如二氧化硅、氮化物、氮化硅、氮氧化硅或硼氮化硅之类的无机绝缘层12用化学汽相淀积法(CVD)沉积在有机聚酰亚胺层10上。为与聚酰亚胺有机物相适应,最好采用二氧化硅或氮化硅(温度≤350℃)。
参看图5,层13采用有机聚酰亚胺层(厚约为2微米)。有机层10和有机层13通常为同一种材料。采用同一种材料的好处是容易制造。
如图6中所示,采用光致抗蚀掩模(图中未示出)使窗口14通到导电环30的M3和边封通道区15。在最佳的方法中,辐射敏感材料或光致抗蚀剂组成的薄层(图中未示出)淀积在有机层13上。接着将光致抗蚀剂暴露在含图形信息的高能粒子流(光子、电子、X射线或离子)中。暴露的被覆层分解后,留下窗口14,15。接着,最好用O2反应离子腐蚀(RIE)之类的干腐蚀法将各层腐蚀掉。
如图7中所示,无机材料(最好是二氧化硅或氮化硅)层16用CVD保形淀积法淀积。有一点很重要,层16与层12化学结合并粘附到起始绝缘体20上,后两者都是无机物,以免钝化层10脱层。因此,二氧化硅(SiO2)层16最好与SiO2层12化学结合。
如图8中所示,层16最好用RIE腐蚀以形成将有机体10与SiO2之类的无机体12,16,20密封的封层。这时可以搬运和/或运输圆片。接着,圆片可以在叠层之间切片,形成一片片的IC芯片而不致使钝化层脱层。
参看图9。图中示出了另一种IC芯片的分层方式。这里不是象图1中所示的那样将单一的无机绝缘体12淀积到有机层10上,而是将一层诸如聚酰亚胺之类的有机层45和象氧化物(例如氧化硅)、氮化物、氮化硅、氮氧化硅或硼氮化硅之类的无机层42淀积到有机层40和导电环M3上。在有机层45与环M3接触处,可能会出现与图1中11类似的脱层。无机封层44避免了这个脱层。无机封层44与导电环M3及无机层42粘合,形成无机/无机封层,起防止脱层的作用。
虽然本发明可采用不同形式的实施例,但这里展示了本发明的一些最佳实施例。但不言而喻,这里公开的内容仅权是本发明原理的实例而已,并没有将本发明局限于所举实施例的意思。
Claims (16)
1.一种集成电路器件,包括:
第一无机绝缘层;
一层有机绝缘层,淀积在所述第一无机绝缘层上;
第二无机绝缘层,淀积在所述有机绝缘层上;
一层无机绝缘封层,密封着所述第一无机绝缘层与所述第二无机绝缘层之间的所述有机绝缘层。
2.如权利要求1所述的集成电路器件,其特征在于,所述有机绝缘层为聚酰亚胺。
3.如权利要求1所述的集成电路器件,其特征在于,所述第一和第二无机绝缘层选自由二氧化硅和氮化硅组成的物质组。
4.如权利要求1所述的集成电路器件,其特征在于,它还包括淀积在所述第二无机绝缘层上的第二有机绝缘层。
5.如权利要求1所述的集成电路器件,其特征在于,所述有机绝缘层内还形成有导电环。
6.一种钝化集成电路器件的方法,其特征在于,它包括下列步骤:
配备第一无机绝缘层;
在所述第一无机绝缘层上淀积上一层有机绝缘层,以形成绝缘层;
在所述有机绝缘层上淀积上第二无机层;
在所述各层中腐蚀出多个窗口;
在所述各腐蚀层上淀积第三无机层;
腐蚀所述第三层,从而形成无机/无机封层,密封所述有机层。
7.如权利要求6所述的方法,其特征在于,淀积有机绝缘层的步骤还包括淀积聚酰亚胺的步骤。
8.如权利要求6所述的方法,其特征在于,所述淀积第二和第三无机层的步骤还包括下列步骤:
淀积选自由氧化硅和氮化硅组成的物质组的无机层。
9.如权利要求6所述的方法,其特征在于,所述腐蚀步骤都采用反应离子腐蚀法。
10.一种防潮密封半导体器件的钝化层的方法,其特征在于,它包括下列步骤:
配备第一无机绝缘层;
在所述无机绝缘层上淀积一层有机层;
在所述有机层上淀积上第二无机层;
在所述各层中用各向异性腐蚀法腐蚀端子转接垫区和边封通道区;
在所述各区上淀积上第三无机层;和
用各向异性深腐蚀法腐蚀所述第三无机层,形成无机封层。
11.如权利要求10所述的方法,其特征在于,所述有机层内还形成有导电环。
12.如权利要求10所述的方法,其特征在于,它还包括下列步骤:
在第一有机层与第一无机层之间淀积第二有机层,且其中所述无机封层密封着导电环与所述第一无机层之间的所述第二有机层。
13.如权利要求10所述的方法,其特征在于,所述无机层选自由二氧化硅和氮化硅组成的物质组。
14.如权利要求10所述的方法,其特征在于,所述腐蚀步骤还包括反应离子腐蚀。
15.一种集成电路器件,包括:
一个有源芯片区,包括
第一无机绝缘层;
一层有机绝缘层,淀积在所述第一无机绝缘层上;
第二无机绝缘层,淀积在所述有机绝缘层上;
一个导电环,环绕所述有源芯片区;和
一个无机封层,用以将所述无机绝缘层密封到所述导电环上,其中所述无机绝缘封层密封所述有机绝缘层。
16.如权利要求15所述的集成电路器件,其特征在于,所述无机绝缘层为二氧化硅或氮化硅。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US724,877 | 1996-10-03 | ||
US08/724,877 US5861658A (en) | 1996-10-03 | 1996-10-03 | Inorganic seal for encapsulation of an organic layer and method for making the same |
US724877 | 1996-10-03 |
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Publication Number | Publication Date |
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CN1190796A CN1190796A (zh) | 1998-08-19 |
CN1110855C true CN1110855C (zh) | 2003-06-04 |
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CN97118202A Expired - Fee Related CN1110855C (zh) | 1996-10-03 | 1997-09-02 | 半导体器件及其钝化方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US5861658A (zh) |
JP (1) | JPH10112459A (zh) |
KR (1) | KR100257429B1 (zh) |
CN (1) | CN1110855C (zh) |
MY (1) | MY115683A (zh) |
SG (1) | SG71037A1 (zh) |
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US5861658A (en) | 1999-01-19 |
SG71037A1 (en) | 2000-03-21 |
CN1190796A (zh) | 1998-08-19 |
US5854141A (en) | 1998-12-29 |
JPH10112459A (ja) | 1998-04-28 |
KR19980032241A (ko) | 1998-07-25 |
MY115683A (en) | 2003-08-30 |
KR100257429B1 (ko) | 2000-05-15 |
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