CN101638212A - Wafer-level vacuum encapsulation wire interconnecting structure of micro electro mechanical system and manufacturing method thereof - Google Patents
Wafer-level vacuum encapsulation wire interconnecting structure of micro electro mechanical system and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a wafer-level vacuum encapsulation wire interconnecting structure of a micro electro mechanical system and a manufacturing method thereof, belonging to a wire interconnectingstructure of a micro electro mechanical system and a manufacturing method thereof. The invention solves the problems that the prior interconnecting structure has high alignment precision requirement and can not ensure the corrosion depth consistency, and improves the vacuum degree retentivity and realizes the electrical signal communication. In the interconnecting structure, a through hole is arranged on a silicon basal plate, an insulation layer is arranged on the surfaces of the through hole and the silicon basal plate, a metal electrode passes through the through hole and seals the throughoff, an intermediate layer is arranged between the metal electrode and the insulation layer, a cover plate is bonded with the silicon basal plate, and a space in the cover plate is a vacuum chamber used for placing an MEMS component. The method for manufacturing the wafer-level vacuum encapsulation wire interconnecting structure comprises the following steps: etching the through hole, making the insulation layer, the intermediate layer and the metal electrode, making a welding ring or forming an annular groove by corrosion, bonding, and the like. The invention has high sealing quality, long vacuum retention time, small bonding stress, good reliability and lower cost, and can greatly promote the commercial popularization of a wafer-level MEMS vacuum encapsulation technology.
Description
Technical field
The invention belongs to the wire interconnecting structure and the manufacture method thereof of MEMS (MEMS), particularly a kind of MEMS wafer level Vacuum Package interconnection structure and manufacture method thereof.
Background technology
All need to carry out Vacuum Package when much having the MEMS device fabrication of important application background.The damping of gas when adopting Vacuum Package can reduce the mechanical moving element motion based on devices such as the gyroscope of resonance structure, micro-acceleration gauge, little high accuracy tactics oscillator, micro-filter, micro-ultrasonic sensor, microorganism molecular mass detectors, greatly improve the quality factor of device, thereby improve the performance of device, and the energy that whole micro-system consumes reduces greatly also.The MEMS Vacuum Package is exactly the encapsulation technology that a kind of cavity that adopts sealing provides high airtight vacuum environment.It can form a vacuum environment around radio frequency, inertia, microelectronic vacuum class MEMS product chips, guarantee that micro-structural wherein has good vibration performance (for example making various mechanical resonators that high quality factor is arranged), make its energy operate as normal, and improve its reliability.Therefore, vacuum sealing technique has become the common technology that has a strong impact on these MEMS device performances and has enabled technology.Vacuum Package can be divided into device level Vacuum Package and wafer level Vacuum Package.Advantages such as the wafer level Vacuum Package has low cost, high yield, and the vacuum retentivity is good have important application prospects.In the wafer level Vacuum Package, because the inside and outside environment of vacuum chamber is isolated, the connection of the device signal of telecommunication in the vacuum chamber must realize by the interconnection of lead.Wire interconnects generally adopts the longitudinal hole type and two kinds on the type of laterally sunkening cord.
People such as Wang Yuchuan study (functional material and device journal in the literary composition in wafer level level Hermetic Package and through hole perpendicular interconnection, 107-4252 (2006) 06-469-05) kind of a wafer level level Hermetic Package structure is proposed: the mode etching through hole of at first on the silicon cover plate, using KOH wet etching and deep reaction ion etching (DIRE) combination, the thick insulating barrier of 1.5 μ m is made in thermal oxide then, next from bottom to top electroplates Cu to metallize in the realization hole.Select for use metal Sn to do bonding material, metal Ni layer is the barrier layer, and the Ni/Sn duplicature is realized with electric plating method; At last the substrate of cover plate and its below is finished pure Sn scolder bonding, and on the plated through-hole of cover plate, make the plumber's solder salient point.The shortcoming of this scheme is: the vacuum retentivity is bad, and manufacture craft needs higher alignment precision, can not guarantee the uniformity of the wet etching degree of depth in addition so that influence follow-up dry etching etc.
Different with traditional interconnection (as the lead-in wire bonding), interconnecting silicon through holes is by forming at silicon chip or etching through hole on glass.This interconnection technique is because be the two ends of vertical connecting circuit, thus be electrically connected that distance is short, usable floor area is also less, density is high, parasitic, effect such as crosstalk is also less.The making of through hole perpendicular interconnection mainly partly is made up of metallization in via etch and the hole two.The method of etched hole mainly contains two kinds on silicon chip at present, and a kind of is wet etching, though this method cost is lower, is difficult to erode away the hole in homogeneous aperture; Another kind is a dry etching, and the depth-to-width ratio that this method advantage is etched hole is higher, and shortcoming is that etch period is long, cost is very high.Metallized method mainly contains motlten metal and fills (MMSM) method and galvanoplastic in the hole, though the better requirement height to equipment of motlten metal completion method effect; The relative simple cheap of galvanoplastic, and the relatively good control of technology, also fine to the effect of through hole.
Summary of the invention
The invention provides a kind of MEMS wafer level Vacuum Package interconnection structure, and provide its manufacture method, the existing interconnection structure alignment precision of solution is had relatively high expectations, wet etching can not guarantee the conforming problem of corrosion depth, when making vacuum chamber keep vacuum for a long time, realize the connection of the inside and outside signal of telecommunication of vacuum chamber.
A kind of MEMS wafer level Vacuum Package interconnection structure of the present invention, has insulating barrier on the silicon substrate surface, has metal electrode on the insulating barrier, the silicon substrate upper surface has weld-ring or is used for the cannelure of anode linkage, cover plate and silicon substrate are at weld-ring or cannelure position bonding, space between cover plate and the silicon substrate is a vacuum chamber, is used to place the MEMS device; It is characterized in that:
Have through hole on the described silicon substrate, through-hole inner surface has insulating barrier, and described metal electrode passes through hole and with its sealing, has the intermediate layer between metal electrode and the silicon substrate, and metal electrode plays MEMS device and extraneous signal of telecommunication interconnection effect.
Described MEMS wafer level Vacuum Package interconnection structure is characterized in that:
Described intermediate layer comprises adhesion layer, diffusion impervious layer and metal seed layer successively; Described adhesion layer material adopts a kind of among Ta, TaN, Cr, Ti, TiN, Ni, Ti/W, Al, Cu, Pd, the Mo;
Described metal seed layer is identical with metal electrode material, adopts a kind of among Au, Cu, Ag, W or the Al.
Described MEMS wafer level Vacuum Package interconnection structure is characterized in that:
The shape of described through hole can be circle or rectangle, and the through hole sectional area is 0.785～200000 μ m
2
Described insulating layer material is SiO
2Perhaps Si
3N
4In one or both; Described cover plate materials is silicon or glass.
During encapsulation, the MEMS device places between the metal electrode on the silicon substrate of the present invention, the MEMS device is drawn pin and is linked to each other with each metal electrode, metal electrode plays MEMS device and extraneous signal of telecommunication interconnection effect, so both guaranteed the connection of the MEMS device signal of telecommunication, guaranteed also that the MEMS device was operated in the vacuum environment.
The manufacture method of a kind of MEMS wafer level of the present invention Vacuum Package interconnection structure comprises:
Step 1, be to use the dry etching through hole on 10～1000 μ m silicon substrates at thickness;
Step 2, make insulating barrier making on the silicon substrate of through hole, thickness is 0.1～5 μ m;
Step 3, make the intermediate layer on insulating barrier, the intermediate layer covers around described through-hole wall and the aperture; The intermediate layer comprises adhesion layer and metal seed layer successively, and each layer thickness is 5～5000nm;
Step 6, under vacuum atmosphere, cover plate and silicon substrate are finished bonding in weld-ring or cannelure position.
Described manufacture method is characterized in that:
In the described step 1, the shape of described through hole can be circle or rectangle, and the through hole sectional area is 0.785～200000 μ m
2
In the described step 2, described insulating layer material is SiO
2Perhaps Si
3N
4In one or both;
In the described step 3, described adhesion layer material adopts a kind of among Ta, TaN, Cr, Ti, TiN, Ni, Ti/W, Al, Cu, Pd, the Mo;
Described metal seed layer is identical with metal electrode material, adopts a kind of among Au, Cu, Ag, W or the Al;
In the described step 6, described cover plate materials is silicon or glass, and the bonding mode is a kind of in gold silicon eutectic bonding, scolder bonding or the silex glass anode linkage.
Vacuum Package interconnection structure of the present invention adopts the through hole perpendicular interconnection and finishes on the basis of wafer level technology, adopt the encapsulation of cover plate and silicon substrate bonding, via etch has adopted dry etching, solve wet etching and can not guarantee the conforming problem of etching depth, electroplating technology has been adopted in metallization in the hole, at the plated-through hole upper and lower sealing property of larger-size fine and close Cu electrode salient point with further assurance encapsulation arranged all, adopt the mode that vertically connects up to finish the electrical interconnection of packaging and external environment, realize interconnection and the requirement that seals in the encapsulation, the airtight quality height, the vacuum retention time is long, bonding stress is little, good reliability, and cost is lower, can greatly promote the commercialization of wafer-level MEMS vacuum sealing technique to promote.
Description of drawings
Fig. 1 is a structural representation of the present invention;
Fig. 2 removes schematic top plan view behind the cover plate for Fig. 1;
Fig. 3～Figure 10 is a process chart of the present invention.
Mark among the figure:
Silicon substrate 1, through hole 2, insulating barrier 3, intermediate layer 4, metal electrode 5, silicon cover plate 6, gold solder ring 7, cannelure 8.
The specific embodiment
The present invention is further described below in conjunction with embodiment and accompanying drawing.
As shown in Figure 1 and Figure 2, the embodiment of the invention 1 resulting interconnection structure, have through hole on the silicon substrate 1, through hole and silicon substrate surface have insulating barrier 3, and metal electrode 5 passes through hole and with its sealing, has intermediate layer 4 between metal electrode and the insulating barrier, silicon substrate 1 upper surface has gold solder ring 7, cover plate 6 and silicon substrate 1 are at gold solder ring 7 position bondings, and the space between cover plate and the silicon substrate is a vacuum chamber, is used to place the MEMS device.
Below be the embodiment of the inventive method.
Embodiment 1, and order comprises:
Step 1, as shown in Figure 3, thickness be on the 10 μ m silicon substrates 1 with dry etching through hole 2, the hole be a circle, the aperture is 1 μ m, sectional area 0.785 μ m
2
Step 2, is as shown in Figure 4 made insulating barrier 3 on the silicon substrate 1 of making through hole, insulating barrier 3 materials are SiO
2, thickness is 0.1 μ m;
Step 3, is as shown in Figure 5 made intermediate layer 4 on insulating barrier, intermediate layer 4 covers around described through-hole walls and the aperture; The intermediate layer comprises adhesion layer Cr and metal seed layer Cu successively, and wherein each layer thickness is 5nm;
Step 6, is as shown in Figure 8 finished the gold silicon eutectic bonding with silicon cover plate and silicon substrate in gold solder ring 7 positions under vacuum atmosphere
Embodiment 2, comprising:
Step 1, as shown in Figure 3, thickness be on the 1000 μ m silicon substrates 1 with dry etching through hole 2, the hole is a circular port, the aperture is 500 μ m, sectional area 196250 μ m
2
Step 2, is as shown in Figure 4 made insulating barrier 3 making on the silicon substrate of through hole, insulating layer material is Si
3N
4, thickness is 5 μ m;
Step 3, is as shown in Figure 5 made intermediate layer 4 on insulating barrier, intermediate layer 4 covers around described through-hole walls and the aperture; Intermediate layer 4 comprises adhesion layer Ni and Au metal seed layer successively, and wherein each layer thickness is 5000nm;
Step 6, is as shown in figure 10 finished anode linkage with glass cover-plate and silicon substrate in cannelure 8 positions under vacuum atmosphere.
Claims (5)
1. MEMS wafer level Vacuum Package interconnection structure, has insulating barrier on the silicon substrate surface, has metal electrode on the insulating barrier, the silicon substrate upper surface has weld-ring or is used for the cannelure of anode linkage, cover plate and silicon substrate are at weld-ring or cannelure position bonding, space between cover plate and the silicon substrate is a vacuum chamber, is used to place the MEMS device; It is characterized in that:
Have through hole on the described silicon substrate, through-hole inner surface has insulating barrier, and described metal electrode passes through hole and with its sealing, has the intermediate layer between metal electrode and the insulating barrier, and metal electrode plays MEMS device and extraneous signal of telecommunication interconnection effect.
2. MEMS wafer level Vacuum Package interconnection structure as claimed in claim 1 is characterized in that:
Described intermediate layer comprises adhesion layer and metal seed layer successively; Described adhesion layer material adopts a kind of among Ta, TaN, Ta, TaN, TiN, Cr, Ti, Ni, Ti/W, Al, Cu, Pd, the Mo;
Described metal seed layer is identical with metal electrode material, adopts a kind of among Au, Cu, Ag, W or the Al.
3. MEMS wafer level Vacuum Package interconnection structure as claimed in claim 1 or 2 is characterized in that:
The shape of described through hole can be circle or rectangle, and the through hole sectional area is 0.785～200000 μ m
2
Described insulating layer material is one or both among SiO2 or the Si3N4; Described cover plate materials is silicon or glass.
4. the manufacture method of the described MEMS wafer level of claim 1 Vacuum Package interconnection structure comprises:
Step 1, be to use the dry etching through hole on 10～1000 μ m silicon substrates at thickness;
Step 2, make insulating barrier making on the silicon substrate of through hole, thickness is 0.1～5 μ m;
Step 3, make the intermediate layer on insulating barrier, the intermediate layer covers around described through-hole wall and the aperture; The intermediate layer comprises adhesion layer and metal seed layer successively, and each layer thickness is 5～5000nm;
Step 4, power on to be coated with at the metal seed layer of through hole and make needed metal electrode, metal electrode is full of and protrudes through hole, and the salient point of metal electrode covers through hole;
Step 5, the salient point covering intermediate layer in addition of removing metal electrode on the silicon substrate make weld-ring on silicon substrate upper surface insulating barrier; Perhaps form cannelure, expose silicon substrate at the bottom of the cannelure at silicon substrate upper surface etching insulating layer;
Step 6, under vacuum atmosphere, cover plate and silicon substrate are finished bonding in weld-ring or cannelure position.
5. manufacture method as claimed in claim 4 is characterized in that:
In the described step 1, the shape of described through hole can be circle or rectangle, and the through hole sectional area is 0.785～200000 μ m
2
In the described step 2, described insulating layer material is one or both among SiO2 or the Si3N4;
In the described step 3, described adhesion layer material adopts a kind of among Ta, TaN, Cr, Ti, TiN, Ni, Ti/W, Al, Cu, Pd, the Mo;
Described metal seed layer is identical with metal electrode material, adopts a kind of among Au, Cu, Ag, W or the Al;
In the described step 6, described cover plate materials is silicon or glass, and the bonding mode is a kind of in gold silicon eutectic bonding, scolder bonding or the silex glass anode linkage.
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| CN102064149A (en) * | 2010-10-21 | 2011-05-18 | 日月光半导体制造股份有限公司 | Semiconductor device with through guide hole, packaging structure thereof and manufacturing method of packaging structure |
| CN102363520A (en) * | 2011-11-04 | 2012-02-29 | 中国科学院半导体研究所 | Wafer level three-dimensional encapsulation method for micro-electro-mechanical system (MEMS) device |
| CN102583218A (en) * | 2012-03-06 | 2012-07-18 | 华中科技大学 | Silicon-based airtight packaging casing |
| CN102820268A (en) * | 2011-06-10 | 2012-12-12 | 中国科学院微电子研究所 | Bonding structure and preparation method thereof |
| CN102842531A (en) * | 2011-06-23 | 2012-12-26 | 新科金朋有限公司 | Semiconductor device and method of forming interconnect structure over seed layer |
| US8786098B2 (en) | 2010-10-11 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor element having conductive vias and semiconductor package having a semiconductor element with conductive vias and method for making the same |
| CN104817052A (en) * | 2014-02-03 | 2015-08-05 | 精工爱普生株式会社 | MEMS device and method for manufacturing the same |
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| CN107532931A (en) * | 2015-04-23 | 2018-01-02 | 东京瓦斯株式会社 | Gas meter, flow meter system and heating amount estimation method |
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| CN109399551A (en) * | 2018-09-26 | 2019-03-01 | 广西桂芯半导体科技有限公司 | Wafer-level package structure and packaging method |
| CN110723712A (en) * | 2019-10-18 | 2020-01-24 | 中国航空工业集团公司西安飞行自动控制研究所 | MEMS device structure and manufacturing method |
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| CN111599740A (en) * | 2020-04-16 | 2020-08-28 | 绍兴同芯成集成电路有限公司 | Ladder-shaped/gentle slope-shaped wafer bonding glass carrier plate framework |
| CN113825719A (en) * | 2019-02-22 | 2021-12-21 | 门罗微系统公司 | Fully symmetric multi-throw switch using conformal clamping holes |
| CN114111474A (en) * | 2021-12-07 | 2022-03-01 | 北京智芯传感科技有限公司 | MEMS impact sheet and wafer-level preparation method thereof |
| CN115290713A (en) * | 2022-07-15 | 2022-11-04 | 广东芯阅科技有限公司 | Electrochemical sensitive chip based on metalized through hole substrate technology and preparation method thereof |
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2009
- 2009-09-08 CN CN200910306690A patent/CN101638212A/en active Pending
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| US8786098B2 (en) | 2010-10-11 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor element having conductive vias and semiconductor package having a semiconductor element with conductive vias and method for making the same |
| CN102064149A (en) * | 2010-10-21 | 2011-05-18 | 日月光半导体制造股份有限公司 | Semiconductor device with through guide hole, packaging structure thereof and manufacturing method of packaging structure |
| CN102820268A (en) * | 2011-06-10 | 2012-12-12 | 中国科学院微电子研究所 | Bonding structure and preparation method thereof |
| CN102842531A (en) * | 2011-06-23 | 2012-12-26 | 新科金朋有限公司 | Semiconductor device and method of forming interconnect structure over seed layer |
| CN102842531B (en) * | 2011-06-23 | 2016-09-07 | 新科金朋有限公司 | Semiconductor devices and the method for interconnection structure is formed on Seed Layer |
| CN102363520B (en) * | 2011-11-04 | 2014-04-09 | 中国科学院半导体研究所 | Wafer level three-dimensional encapsulation method for micro-electro-mechanical system (MEMS) device |
| CN102363520A (en) * | 2011-11-04 | 2012-02-29 | 中国科学院半导体研究所 | Wafer level three-dimensional encapsulation method for micro-electro-mechanical system (MEMS) device |
| CN102583218A (en) * | 2012-03-06 | 2012-07-18 | 华中科技大学 | Silicon-based airtight packaging casing |
| CN105514090A (en) * | 2012-06-11 | 2016-04-20 | 日月光半导体制造股份有限公司 | Semiconductor devices shielding electro-magnetic interference and methods of manufacturing |
| CN104817052B (en) * | 2014-02-03 | 2019-04-30 | 精工爱普生株式会社 | Micro-electro-mechanical systems element and its manufacturing method |
| CN104817052A (en) * | 2014-02-03 | 2015-08-05 | 精工爱普生株式会社 | MEMS device and method for manufacturing the same |
| CN105980840A (en) * | 2014-02-06 | 2016-09-28 | ams有限公司 | Method of producing a semiconductor device with protruding contacts |
| CN105980840B (en) * | 2014-02-06 | 2019-07-16 | ams有限公司 | Manufacture the method with the semiconductor devices of projection contacts |
| CN107532931A (en) * | 2015-04-23 | 2018-01-02 | 东京瓦斯株式会社 | Gas meter, flow meter system and heating amount estimation method |
| CN108502841A (en) * | 2018-05-04 | 2018-09-07 | 李扬渊 | A kind of electronic equipment and its manufacturing method that can realize supersonic sensing |
| CN109399551A (en) * | 2018-09-26 | 2019-03-01 | 广西桂芯半导体科技有限公司 | Wafer-level package structure and packaging method |
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| CN110723712B (en) * | 2019-10-18 | 2024-02-13 | 中国航空工业集团公司西安飞行自动控制研究所 | MEMS device structure and manufacturing method |
| CN111137839A (en) * | 2020-01-14 | 2020-05-12 | 清华大学 | Three-dimensional wafer level packaging structure for in-plane motion micro-electro-mechanical system device |
| CN111599740A (en) * | 2020-04-16 | 2020-08-28 | 绍兴同芯成集成电路有限公司 | Ladder-shaped/gentle slope-shaped wafer bonding glass carrier plate framework |
| CN114111474A (en) * | 2021-12-07 | 2022-03-01 | 北京智芯传感科技有限公司 | MEMS impact sheet and wafer-level preparation method thereof |
| CN115290713A (en) * | 2022-07-15 | 2022-11-04 | 广东芯阅科技有限公司 | Electrochemical sensitive chip based on metalized through hole substrate technology and preparation method thereof |
| CN115290713B (en) * | 2022-07-15 | 2023-08-22 | 广东芯阅科技有限公司 | Electrochemical sensitive chip based on metallized through hole substrate technology and preparation method thereof |
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