CN110723712B - MEMS device structure and manufacturing method - Google Patents
MEMS device structure and manufacturing method Download PDFInfo
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- CN110723712B CN110723712B CN201910997993.7A CN201910997993A CN110723712B CN 110723712 B CN110723712 B CN 110723712B CN 201910997993 A CN201910997993 A CN 201910997993A CN 110723712 B CN110723712 B CN 110723712B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 185
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 167
- 239000010703 silicon Substances 0.000 claims abstract description 167
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000000605 extraction Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000007789 sealing Methods 0.000 abstract description 20
- 230000008707 rearrangement Effects 0.000 abstract description 4
- 239000011521 glass Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 4
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-AKLPVKDBSA-N silicon-31 atom Chemical compound [31Si] XUIMIQQOPSSXEZ-AKLPVKDBSA-N 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 229910015365 Au—Si Inorganic materials 0.000 description 1
- 229910017755 Cu-Sn Inorganic materials 0.000 description 1
- 229910017927 Cu—Sn Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/007—Interconnections between the MEMS and external electrical signals
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0058—Packages or encapsulation for protecting against damages due to external chemical or mechanical influences, e.g. shocks or vibrations
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0064—Packages or encapsulation for protecting against electromagnetic or electrostatic interferences
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- General Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Micromachines (AREA)
Abstract
The invention discloses a MEMS device structure and a manufacturing method thereof. The MEMS device structure is formed by bonding an SOI cover plate (18), a silicon structure layer (4') and a silicon through hole piece (6) through silicon. The SOI cover plate (18) comprises a top silicon layer (3) bonded with silicon of the silicon structure layer (4 '), an intermediate buffer layer (2) and a supporting layer (1), silicon wires (21, 24) and electrode bonding anchor points (20, 23, 27) are manufactured on the top silicon layer (3), the electrode bonding anchor points (20, 23, 27) of the top silicon layer (3) and the electrodes (8, 13, 22) of the silicon structure layer (4 ') are respectively communicated through silicon bonding, and the electrodes (8, 13, 22) of the silicon structure layer (4 ') are led out directly or through the silicon wires and the electrode bonding anchor points on the top silicon layer (3) through silicon through holes (14) on a silicon through hole piece (6). The MEMS device structure adopts the silicon through hole to directly lead out the electrode, the SOI cover plate can simultaneously realize interconnection between the electrodes in the cavity and rearrangement and sealing of the silicon through hole electrode, the electric signal is led out conveniently, and the design flexibility is high.
Description
Technical Field
The invention belongs to the technical field of micro-electronics and machinery, and particularly relates to a MEMS device structure and a manufacturing method thereof.
Background
With the development of the internet of things, microelectromechanical systems (Micro Electro-Mechanical Systems, MEMS) devices, such as gyroscopes, accelerometers, pressure sensors, gas sensors, and the like, are gaining attention. In order to protect the core components of the sensor from the interference of external environment, MEMS devices such as resonators, thermal sensors and the like need to be sealed and packaged, and wafer level packaging can realize batch sealing of chips on a wafer, so that the cost of the devices is effectively reduced. At the same time, sealing presents challenges for sealing electrode wiring and signal extraction of devices within the cavity.
The through silicon via (Through Silicon Via, TSV) technology can realize in-situ extraction of signals in the sealed cavity, and the difficulty of extraction of devices is reduced. However, when the device through silicon vias are so close that they are not suitable for in-situ extraction or inter-electrode interconnection is required, the interconnect layer is still required for inter-electrode rewiring.
The bonding mode commonly used for wafer level packaging is anodic bonding, metal dielectric layer bonding, silicon-silicon fusion bonding and the like. The scheme of adopting glass as a sealing layer can directly adopt aluminized wiring inside a glass cavity to realize signal interconnection because the glass is an insulating material. The silicon-glass adopts anodic bonding, the bonding temperature is lower, about 300-500 ℃, and the anodic bonding strength is high, and can directly adopt film metal wire bonding to realize interconnection between electrodes, however, the thermal expansion coefficients of the glass material and the silicon material are not matched, so that the stress problem can be caused, and the environmental adaptability of the sensor is reduced. The metal dielectric layer bonding includes eutectic bonding such as Au-Si, al-Ge, thermocompression bonding such as Au-Au, cu-Cu, and transient liquid phase bonding such as Cu-Sn, au-Sn. The bonding temperature of the metal dielectric layer is lower, generally not exceeding 450 ℃, but in order to adapt to the surface morphology of the device so as to realize good sealing, the thickness of the metal layer is generally several micrometers, thereby bringing additional stress problems and higher cost.
The silicon-silicon fusion bonding is adopted, an external electric field and any adhesive are not needed, and the MEMS device of all silicon can avoid the stress problem caused by mismatch of thermal expansion coefficients of the silicon structural layer and the sealing layer material, and has the potential of high bias stability and good temperature characteristic. However, silicon-silicon bonding requires high bonding surface flatness and surface roughness, and typically requires high temperature annealing (-1000 ℃) and metal materials such as aluminum cannot be used for wiring interconnection schemes in sealed cavities due to temperature limitations. The scheme of wiring on the insulating layer outside the sealing cavity after bonding is easy to be damaged by external environment and external force, and meanwhile, extra stress can be introduced, so that the performance of the device is not improved.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a MEMS device structure and method of fabricating the same that achieves device sealing and electrical connection using through-Silicon via leads and Silicon wires fabricated On top of SOI (Silicon-On-Insulator) Silicon. The bonding scheme is simple and feasible, the signal is led out conveniently, the wiring is flexible, meanwhile, the silicon material is adopted as the electrode wire, the bonding scheme can bear higher temperature, the stress of the device is small, and the temperature characteristic is good.
According to one aspect of the present invention, there is provided a MEMS device structure comprising an SOI cover plate, a silicon structural layer and a through silicon via wafer bonded by silicon-silicon. The silicon structural layer includes a movable structure of the MEMS device and an electrode. The SOI cover plate comprises a top silicon layer bonded with a silicon structure layer, an intermediate buffer layer and a supporting layer. The silicon wire, the electrode bonding anchor point and the sealing ring are manufactured on the top silicon of the SOI cover plate, two ends of the silicon wire are connected with the electrode bonding anchor point, the height of the silicon wire in the top silicon of the SOI cover plate is lower than that of the electrode bonding anchor point and the sealing ring, a certain gap is reserved between the bonded silicon wire and a silicon structure layer of the MEMS device, and the two sides of the silicon wire are etched to the middle buffer layer, so that the silicon wire is electrically isolated from surrounding structures. Considering that the silicon wire and the electrode bonding anchor point are manufactured on the top silicon, the top silicon is low-resistance silicon, and the common resistivity is 0.001-0.1 omega-cm. And the electrode bonding anchor point of the top silicon layer and the electrode of the silicon structure layer are respectively communicated through silicon-silicon bonding, so that interconnection between the electrodes of the device structure layer is realized. The electrode of the silicon structure layer is led out through the silicon through hole on the silicon through hole piece directly or through the silicon wire and electrode bonding anchor point on the top silicon.
In addition, the SOI cover plate may be provided with a ground hole penetrating the support layer and the intermediate buffer layer of the SOI cover plate, communicating with the ground electrode of the silicon structure layer, to interconnect the support layer of the SOI cover plate and the ground electrode of the silicon structure layer, to ground the support layer, functioning to reduce parasitic effects and electrostatic shielding.
In the structure, the SOI cover plate can realize rearrangement of the through silicon via electrode, so that the design flexibility is improved, meanwhile, the silicon material is used as an electrode wire, the higher temperature can be born, the stress of the device is small, and the temperature characteristic is good.
According to another aspect of the present invention, there is provided a method for manufacturing the MEMS device structure described above, the method comprising the steps of: manufacturing a through silicon via piece with a through silicon via; silicon bonding is carried out on the oxidized silicon through hole piece and a silicon wafer with proper thickness, a movable structure of the MEMS device is manufactured on the silicon wafer, and bonding anchor points and electrodes are bonded to form a silicon structure layer bonded with the silicon through hole piece in a silicon-silicon mode; manufacturing an electrode bonding anchor point, a silicon wire and a sealing ring on top silicon of the SOI to form an SOI cover plate; and the silicon-silicon bonding SOI cover plate and the silicon structure layer are plated with conductive metal at the silicon through hole, so that the electrode of the silicon structure layer is led out.
The method further includes the step of forming a ground hole in the SOI cover plate through the support layer and the intermediate buffer layer of the SOI cover plate, thereby interconnecting the support layer of the SOI cover plate and the ground electrode of the silicon structure layer.
The MEMS device structure adopts the silicon through hole to directly lead out the electrode, the SOI cover plate can simultaneously realize interconnection between the electrodes in the cavity and rearrangement and sealing of the silicon through hole electrode, the electric signal is led out conveniently, and the design flexibility is high. The MEMS device is realized by twice silicon-silicon bonding, and has simple process and small stress. The fabrication of silicon conduction bands on the top silicon of the SOI cover plate may be subjected to higher temperatures than metal conduction bands. Meanwhile, compared with the metal wiring outside the cavity, the silicon conduction band wiring in the cavity can avoid the influence of external environment corrosion, external force damage and the like. In addition, the supporting layer of the SOI cover plate can be provided with a grounding hole which is interconnected with a ground electrode in the bonded silicon structure layer, so that parasitic effect can be reduced, and meanwhile, the supporting layer plays a role of electrostatic shielding.
Drawings
FIG. 1 is a cross-sectional view schematically illustrating a structure of a MEMS device in accordance with an embodiment of the invention;
FIG. 2 is a top view of the top silicon of the SOI cover plate in the MEMS device structure shown in FIG. 1;
fig. 3 (a) -3 (n) illustrate a method of fabricating a MEMS device structure according to an embodiment of the present invention.
Detailed Description
The present invention will be further described in detail with reference to the drawings and examples for more clearly understood objects, technical solutions and advantages of the present invention.
Fig. 1 schematically illustrates a MEMS device structure in accordance with an embodiment of the invention, and fig. 2 is a top view of SOI cap top layer silicon in the MEMS device structure shown in fig. 1.
As shown in fig. 1, the all-silicon MEMS device structure of the present embodiment is formed by SOI cover plate 18, silicon structure layer 4' and through-silicon via 6 by silicon-silicon bonding.
The silicon structure layer 4' is a structure layer of the MEMS device, and the movable structure 12, the electrodes 8, 13, 22 and the bonding anchor point 16 of the MEMS device are fabricated according to the design of the MEMS device, wherein the electrode 8 is a ground electrode.
The SOI cover plate 18 includes a top silicon layer 3 silicon-bonded to the silicon structural layer 4', an intermediate buffer layer 2 and a support layer 1, the top silicon layer 3 being low-resistance silicon having a resistivity of typically 0.001 Ω -cm to 0.1 Ω -cm. On the top silicon 3 of the SOI cover 18, silicon conductors 21, 24, electrode bond anchors 20, 23, 27 and sealing rings 17 are fabricated. The electrode bonding anchor points in the top silicon layer 3 correspond to the electrode positions in the silicon structural layer and play roles of fixing and electrode interconnection, and the electrode bonding anchor points 20, 23 and 27 are respectively connected with the electrodes 13, 22 and 8 in the silicon structural layer 4', specifically, the electrode bonding anchor point 20 is connected with the electrode 13, the electrode bonding anchor point 23 is connected with the electrode 22, and the electrode bonding anchor point 27 is connected with the electrode 8. The height of the silicon wires 21, 24 in the top layer of silicon 3 is lower than the electrode bonding anchors 20, 23, 27 to ensure a certain gap between the bonded silicon wires and the silicon structural layer 4' of the MEMS device. The silicon conductors 21, 24 are etched on both sides to the intermediate buffer layer 2 of the SOI cover plate 18, ensuring that the silicon conductors are electrically isolated from surrounding structures. As shown, the silicon wire 21 is connected to the electrode bond anchor 20, 23 so as to communicate with the electrode 13 of the silicon structural layer 4 'via the electrode bond anchor 20, which enables interconnection between the electrode of the silicon structural layer 4' of the MEMS device, such as electrode 22 and electrode 13. In essence, the silicon wire 24 is similar to the silicon wire 21, but the electrode bond anchor to the silicon wire 24 is not shown. The sealing ring 17 is bonded to the bonding anchor 16 of the silicon structural layer 4', the bonding anchor 16 being essentially also a sealing ring.
The through silicon via 6 is silicon bonded to the silicon structural layer 4', the through silicon via 6 is provided with a through silicon via 14 with an electrode hole 9, as shown, the through silicon via 14 on the through silicon via 6 is connected to the electrodes 8, 13 of the silicon structural layer 4', respectively, so that the electrode 8 and the electrodes 22 and 13 of the silicon structural layer 4' are led out through the through silicon via 14 on the through silicon via 6, respectively, and meanwhile, as shown, the electrodes 8, 13 are arranged on the through silicon via 14, respectively, the sealing of the MEMS device can be realized. Further, as shown in the drawing, shallow trenches 10 are provided in the through-silicon via 6 at positions corresponding to the movable structures 12 of the silicon structure layer 4', and supporting bond anchor points 11 are provided at positions corresponding to the electrodes 22.
Therefore, through adopting the silicon through hole to directly lead out the electrode, the SOI cover plate can simultaneously realize interconnection between the electrodes in the cavity and rearrangement of the electrode of the silicon structural layer, so that the flexibility of design is improved, meanwhile, the silicon material is used as an electrode wire, the electrode wire can bear higher temperature, the stress of the device is small, and the temperature characteristic is good.
In addition, the SOI cover 18 may further be provided with a ground hole 25 communicating with the ground electrode 8 of the silicon structural layer 4 'through an electrode bonding anchor point 27 of the SOI cover 18, so as to implement interconnection of the support layer 1 and the ground electrode 8 of the silicon structural layer 4', and ground the support layer 1, thereby having the effect of reducing parasitic effects and electrostatic shielding. In this case, since the grounding of the support layer 1 and the electrode extraction of the silicon structure layer 4' are both extracted from the same side of the MEMS device structure, i.e., the side of the through-silicon via 6, the arrangement of the extraction lines is facilitated. Of course, the ground of the support layer 1 may be led out from the SOI cover plate side alone without the ground electrode 8, but this may cause trouble in the arrangement of the lead wires.
Referring now to fig. 3, and in conjunction with fig. 1, a method of fabricating the MEMS device structure described above is illustrated in detail.
Example 1:
fabrication of through-silicon via (TSV) wafer 6
First, an oxide layer 7 is oxidized on a double-sided polished silicon wafer, and shallow trenches 10, bond anchor points 11, and electrode holes 9 are formed on one side of the silicon wafer by dry etching according to the design of the MEMS device (see fig. 3 (a)). Thereafter, wet etching is performed at the other side of the silicon wafer at a position corresponding to the electrode hole 9, thereby forming a through-silicon via 14 (see fig. 3 (b)). The silicon through hole is formed by etching from the other side, and the method has the advantages of simple and convenient process. Finally, after removing the oxide layer, the entire silicon wafer is reoxidized, forming a new insulating layer 7, and obtaining a through-silicon via 6 (see fig. 3 (c)).
Fabrication of silicon structural layer 4
First, the oxidized through-silicon via wafer 6 and the silicon wafer 4 having a thickness satisfying the design requirements of the MEMS device are subjected to silicon-silicon bonding (see fig. 3 (e)). The silicon wafer 4 can be a silicon wafer of an appropriate thickness obtained by thinning a normal silicon wafer. In this case, the surface of the silicon wafer needs to be polished to achieve surface roughness enabling subsequent silicon-silicon bonding, the work is large, and in the case where the appropriate thickness is small, the operation is difficult. Thereafter, the movable structure 12, the bonding anchor 16, and the electrodes 8 (see fig. 1), 13, and 22 (see fig. 3 (f)) of the MEMS device are fabricated by photolithography and dry etching on the silicon wafer 4 in accordance with the design of the MEMS device.
Fabrication of SOI cover plate 18
First, a layer of silicon oxide 19 is grown on the surface of the SOI wafer, and the silicon is wet-etched or dry-etched into the buffer layer 2 of the SOI wafer to form the ground hole 25 (see fig. 3 (g)). Thereafter, si is grown by LPCVD (Low pressure chemical vapor deposition) 3 N 4 Layer 32, primarily serves to protect the bottom of the hole. Subsequently, photolithography for fabricating electrode bonding anchor points, seal rings, and RIE (reactive ion etching) etching of surface Si are performed on the top layer silicon 3 of the SOI wafer 3 N 4 Layer 32 and SiO 2 Layer 19 (see fig. 3 (h)). Next, the photoresist 33 is uniformly etched on the top layer silicon 3 of the SOI wafer, and the shallow trench 34 is etched using the photoresist 33 as a mask (see fig. 3 (i) and (j)). Then, the surface photoresist 33 is removed to form Si 3 N 4 And SiO 2 As a mask, DRIE (deep reactive ion etching) etching is continued to the buffer layer 2 of the SOI, the silicon wiring 21, the silicon wiring 24 (see fig. 1), and the seal ring 17 (see fig. 3 (k)) are fabricated, and finally Si on the top silicon 3 surface of the SOI wafer is dry etched away 3 N 4 Layer 32 is wet etched to remove surface silicon oxide 19 to form SOI cover plate 18. Of courseThe electrode bonding anchor point, the silicon wire and the sealing ring are manufactured on the top silicon 3 of the SOI wafer, and the dry etching mode or the combination mode of the dry etching and the wet etching can be selected.
Bonding and in-hole metallization
Referring to fig. 3 (l), SOI cover plate 18 is silicon bonded to silicon structural layer 4', and electrode bond anchors 20, 23, 27 are silicon bonded to electrodes 8, 13, 22, respectively, in silicon structural layer 4'. The sealing ring 17 is bonded to the bonding anchor 16 of the silicon structural layer 4', the bonding anchor 16 being essentially also a sealing ring. Thereafter, referring to fig. 3 (m), si on the surface of the support layer 1 of the SOI cover plate 18 is dry etched away 3 N 4 The layer 32 is formed by dry etching or wet etching the buffer layer 2 in the grounding hole 25 to the top silicon 3 through a hard mask, and plating conductive metal 26, preferably aluminum, in the grounding hole 25 of the SOI cover plate 18 through the hard mask, so that the ground electrode 8 of the supporting layer 1 and the silicon structure layer 4' is communicated, and the supporting layer 1 is grounded, thereby having the effects of reducing parasitic effects and electrostatic shielding. Finally, a conductive metal 15, preferably aluminum, is plated through the hard mask in the through-silicon via 14 and annealed to draw the electrode of the silicon structural layer 4' out through the through-silicon via (see fig. 3 (n)).
As above, the fabrication of the MEMS device structure described above is completed.
Example 2:
example 2 differs from example 1 above in that: first, the silicon wafer 4 of which the silicon structure layer 4' is made is obtained by subjecting the oxidized through-silicon via wafer to silicon bonding with the top silicon 31 of another SOI wafer 30, followed by dry etching or chemical mechanical polishing to thin the support layer 29 of the SOI wafer 30 to the buffer layer 28, and then wet etching the buffer layer 28 to the top silicon 31 (see fig. 3 (d) and (e)). Under the condition, the process is simple, the operation is convenient, the thickness uniformity of the silicon wafer is good, but the cost of the SOI wafer is higher; next, the support layer 1 of the SOI cover plate 18 is not grounded, and thus there are no steps of manufacturing the ground hole 25, and realizing metallization in the ground hole 25, and the like. The other steps are the same as in example 1.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims. The non-detailed description of the invention is within the knowledge of a person skilled in the art.
Claims (8)
1. A MEMS device structure, which is formed by mutually bonding a SOI cover plate (18), a silicon structure layer (4 ') and a through silicon via (6), wherein the silicon structure layer (4 ') comprises a movable structure (12) and electrodes (8, 13, 22) of the MEMS device, the SOI cover plate (18) comprises a top silicon (3) silicon bonded with the silicon structure layer (4 '), an intermediate buffer layer (2) and a support layer (1), silicon wires (21, 24) and electrode bonding anchor points (20, 23, 27) are made on the top silicon (3), the electrode bonding anchor points (20, 23, 27) of the top silicon (3) and the corresponding electrodes (13, 22, 8) of the silicon structure layer (4 ') are respectively communicated by silicon bonding, the electrodes (8, 13, 22) of the silicon structure layer (4 ') are led out directly or through the silicon wires and the electrode bonding anchor points on the top silicon structure layer (3) through the through silicon via (14) on the through silicon via (6), wherein ground wires (25) penetrating the SOI cover plate (18) and the support layer (1) are arranged.
2. The MEMS device structure according to claim 1, wherein the top layer silicon (3) is low resistance silicon.
3. The MEMS device structure according to claim 1, wherein the top layer silicon (3) has a resistivity of 0.001 Ω -cm to 0.1 Ω -cm.
4. A method of fabricating a MEMS device structure according to claim 1, comprising the steps of:
manufacturing a through silicon via (6) with a through silicon via (14);
silicon bonding is carried out on the oxidized silicon through hole piece and a silicon wafer with proper thickness, a movable structure and an electrode of the MEMS device are manufactured on the silicon wafer, and a silicon structure layer (4') which is bonded with the silicon through hole piece in a silicon manner is formed;
manufacturing an electrode bonding anchor point and a silicon wire on the top silicon of the SOI sheet to form an SOI cover plate (18);
the silicon-silicon bonding SOI cover plate (18) and the silicon structure layer (4 ') are plated with conductive metal in the silicon through hole (14) to realize the extraction of the electrode of the silicon structure layer (4'),
the method further comprises the step of manufacturing a grounding hole (25) penetrating through the supporting layer (1) and the middle buffer layer (2) of the SOI cover plate (18) on the SOI cover plate (18) to enable the supporting layer (1) of the SOI cover plate (18) to be communicated with the ground electrode (8) of the silicon structure layer (4').
5. The method according to claim 4, wherein the ground hole (25) is formed by etching the support layer (1) of the SOI cover plate (18) to the intermediate buffer layer (2), then etching the inner intermediate buffer layer (2) to the top silicon (3), followed by plating the conductive metal inside.
6. The method of claim 5, wherein the conductive metal is aluminum.
7. The method of claim 4, wherein the silicon wafer of suitable thickness is obtained by thinning to remove the support layer and intermediate buffer layer of the SOI wafer.
8. The method of claim 7, wherein said thinning removing the support layer and the intermediate buffer layer of the SOI wafer comprises dry etching or chemical mechanical polishing the support layer of the SOI wafer to the intermediate buffer layer, followed by wet etching the intermediate buffer layer to the top silicon.
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