CN110467148B - Wafer-level packaging MEMS chip structure and processing method thereof - Google Patents
Wafer-level packaging MEMS chip structure and processing method thereof Download PDFInfo
- Publication number
- CN110467148B CN110467148B CN201910730860.3A CN201910730860A CN110467148B CN 110467148 B CN110467148 B CN 110467148B CN 201910730860 A CN201910730860 A CN 201910730860A CN 110467148 B CN110467148 B CN 110467148B
- Authority
- CN
- China
- Prior art keywords
- layer
- wafer
- silicon
- metal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0006—Interconnects
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Micromachines (AREA)
Abstract
The invention relates to a wafer-level packaging MEMS chip structure and a processing method thereof. Electric signals in the packaging cavity are firstly led out from the side face of the structure through a first layer of lead of a double-layer metal lead arranged on a substrate layer and crossing a substrate bonding sealing ring, after metal eutectic bonding wafer-level vacuum packaging is completed, deep silicon etching is carried out on the position corresponding to a metal electrode on the back face of a substrate wafer to form a through hole, a conductive material is used for filling the through hole or forming a conductive silicon column, and electrode leading-out is carried out on the back face. The structure can be integrated with a signal processing circuit by adopting a flip-chip bonding mode, and compared with a mode of electrically leading out by manufacturing TSV (through silicon via) holes in a packaging cavity, the structure avoids the problem of packaging air tightness caused by filling cavities with insulating media and also avoids the problems of temperature stability and reliability caused by the mismatch of thermal expansion coefficients of filling materials and silicon materials.
Description
Technical Field
The invention belongs to the technical field of manufacturing of Micro Electro Mechanical Systems (MEMS), and particularly relates to a wafer-level packaging MEMS chip structure and a processing method thereof.
Background
The wafer level packaging technology realizes the airtight or vacuum packaging of devices on the whole wafer at one time in a wafer bonding mode, and completes the mechanical and electrical connection among different structural levels of the MEMS chip. The packaging process is simplified, the packaging cost is reduced, and the overall size of the device is greatly reduced. The wafer-level vacuum packaging can protect the movable structure in the MEMS device from water flow and particle pollution in the cutting process to the maximum extent, is beneficial to reducing batch cost, and improves the consistency, yield and reliability of products.
The longitudinal vertical electrode extraction technology is adopted to realize the longitudinal electrical interconnection extraction of wafer level packaging, the three-dimensional stacking of the MEMS device and the IC processing chip can be realized by adopting a Flip chip mode, the overall dimension is greatly reduced, the MEMS product has the advantages of batch, small volume and low cost, and the MEMS device is convenient to be applied to various micro systems.
The MEMS resonator, the MEMS gyroscope, the MEMS infrared sensor and other devices can ensure the optimal performance only when working in a high vacuum state, and the micro movable structures of the MEMS resonator, the inertial device and the like can reduce air damping as much as possible and improve the Q value of resonance when working in a resonance condition by vacuum packaging, so that higher test precision is obtained; MEMS infrared sensors require high vacuum packaging to reduce air convection heat dissipation and thereby increase sensitivity.
In MEMS wafer-level vacuum packaging adopting a longitudinal TSV electrode leading-out mode, electrode leading-out structures such as silicon through holes are the largest risk factors causing vacuum seal leakage. The micro-structure in the vacuum cavity needs to be interconnected with the outside in a silicon through hole mode. In order to meet the requirements of electrical insulation and sealing, the through silicon vias need to be filled with insulating media and conductive materials. One process challenge in filling high aspect ratio deep holes with material is ensuring that no voids are present in the interior. How to ensure the through hole sealing, and the long-term effectiveness, and the satisfaction of the high-vacuum degree wafer level packaging requirement is a key difficult problem which restricts the wafer level vacuum packaging process based on the TSV leading-out mode at present. The high-performance MEMS device needs to work normally in different temperature variation ranges, the thermal expansion coefficient difference among the insulating medium, the conductive material and the silicon material in the TSV through hole filling is large, and gaps are easily generated among interfaces under the action of stress in the temperature variation process, so that vacuum packaging failure is caused. On the other hand, the thermal stress problem caused by large difference of thermal expansion coefficients among materials in the TSV process can also affect the characteristic parameters of the MEMS chip, and the chip characteristic parameters of the chip can drift under different temperature conditions, such as the full-temperature zero drift of the MEMS gyroscope and the accelerometer.
Disclosure of Invention
The invention provides a wafer level packaging MEMS chip structure and a processing method thereof, aiming at solving the problems of poor vacuum packaging tightness and large characteristic parameter drift under different temperature conditions of the wafer level packaging MEMS chip based on the TSV technology in the prior art, and combining the extraction of a transverse electrode and the extraction of a longitudinal TSV vertical electrode. The structure has the advantages that the wafer level packaging of the traditional vertical TSV vertical electrode leading-out mode can be subjected to flip chip bonding and three-dimensional stacking integration easily, and the structure has the advantages of good packaging sealing performance and good temperature stability.
The technical scheme of the invention is as follows:
providing a wafer-level packaging MEMS chip structure, sequentially bonding a substrate layer, a device layer and a cap layer in a wafer bonding mode twice to form a cavity structure, and sealing by a bonding sealing ring; forming a first metal layer along the surface of the substrate layer, and leading out the first metal layer from the back of the substrate layer by using the vertical interconnection structure to form an electrical leading-out passage; the junction of the vertical interconnect structure and the first metal layer is located outside the cavity structure sealed by the bond seal ring.
Preferably, the device layer forms a comb structure; the anchor area structure of the device layer is bonded with the anchor area structure of the substrate layer through metal eutectic bonding to form a cavity covering the lower surface of the comb tooth structure;
the anchor area structure of the device layer supports the cap layer, so that a cavity covering the upper surface of the comb tooth structure is formed after the device layer and the cap layer are bonded; and a silicon oxide layer is arranged on the bonding surface of the cap layer and the device layer, so that the cap layer is insulated from the device layer.
Preferably, a cavity is formed on the substrate layer through corrosion, and an anchor region structure for supporting the device layer is left in the cavity of the substrate layer; different depths are set at different positions of the cavity of the substrate layer, the electrode lead is arranged at the position with the deeper depth, and the detection electrode is arranged at the position with the deeper depth.
Preferably, a second silicon dioxide layer and a first silicon oxide layer are respectively distributed on the upper part and the lower part of the first metal layer on the surface of the substrate layer; the substrate layer anchor area structure is a table top with a certain gradient, and the first metal layer extends to the table top from the lower part of the table top; a second metal layer is distributed on the second silicon dioxide layer at the anchor region structure of the substrate layer and is used as a bonding medium layer; and the second silicon dioxide layer at the anchor region structure of the substrate layer is provided with a through hole, so that the first metal layer is communicated with the second metal layer.
Preferably, on the substrate layer, a city wall-shaped annular table top is formed at the periphery of the chip structure, and a second metal layer is distributed on the annular table top to serve as a bonded dielectric layer to form a bonded sealing ring surrounding the comb tooth structure; the first metal layer extends out of the substrate layer cavity from the substrate layer cavity, and a second silicon dioxide layer is arranged between the first metal layer and the sealing ring, so that the first metal layer is electrically isolated from the bonding dielectric layer at the bonding sealing ring.
Preferably, the second metal layer and the first metal layer are made of different materials, and the resistivity of the material of the second metal layer is smaller than that of the material of the first metal layer; the thickness of the second metal layer is larger than that of the first metal layer; the second metal layer is used as a main wiring layer, and the first metal layer is used as a jumper layer, so that the lead resistance is reduced.
Preferably, the second metal layer is used for preparing a capacitor plate, so that the detection of the movement of the device layer structure in the longitudinal direction is realized.
Preferably, the wafer level packaging structure forms a plurality of packaging cavities, the getter layer is arranged on the second silicon dioxide dielectric layer of the partial packaging cavity of the substrate layer to realize high vacuum packaging, and the air leakage holes are formed in the back of the substrate layer of the partial cavity to realize atmospheric packaging.
Preferably, the getter in the getter layer is one or more of Ti, zr and V, and the thickness is 200nm-2000nm;
preferably, a support structure is arranged outside the device layer bonding sealing ring and in a position corresponding to the vertical interconnection structure, and a longitudinal air isolation groove is formed in the periphery of the support structure to isolate stress between the support structure and the vertical interconnection structure.
Preferably, an air isolation groove is arranged around the substrate layer vertical interconnection structure to isolate the stress of the vertical interconnection structure.
Preferably, the vertical interconnection structure is realized by filling an insulating medium layer in the inner wall of the TSV through hole and filling a metal conductive material in the insulating medium layer; and preparing a metal welding spot outside the TSV through hole.
Preferably, the first metal layer is one or more of tungsten, aluminum, titanium, copper, gold, nickel, chromium, tantalum and cobalt; the second metal layer comprises an adhesion barrier layer and a metal eutectic solder layer, the adhesion barrier layer is made of one or more of Cr, ti, ni and W, and the metal eutectic solder layer is made of one of AuSi, auSn, alGe and CuSn.
Preferably, the depth of the substrate cavity is 2-20 μm, and the thickness of the first silicon oxide layer is 1-3 μm; the thickness of the first metal layer is 100nm-300nm; the thickness of the second silicon dioxide layer is 300nm-600nm, the thickness of the adhesion barrier layer in the second metal layer is 10nm-50nm, and the thickness of the metal eutectic solder layer is 0.5 mu m-2 mu m.
Preferably, the conductive material in the TSV is made of one of Cu, au, W and heavily doped polysilicon, and the insulating medium layer is made of one of silicon oxide, doped silicon oxide, silicon nitride and silicon oxynitride.
Preferably, the growth of the insulating medium layer is realized by an LPCVD method, and the filling of the conductive material is realized by one of electroplating, CVD and PVD methods.
Preferably, the substrate layer is a resistivity silicon wafer; the vertical interconnection structure is led out through the conductive silicon column, an isolation layer is arranged around the conductive silicon column, and the lower end of the vertical interconnection structure is provided with a metal welding spot.
Preferably, the isolation layer is not filled with a medium or is filled with a medium; the filling medium material is selected from silicon oxide, doped silicon oxide, silicon nitride, silicon oxynitride, glass slurry and organic material; the dielectric layer formed by filling the dielectric only covers the surface of the silicon material or is filled with the isolation layer.
The processing method of the wafer-level packaging MEMS chip structure comprises the following steps:
1) Processing the device layer and the cap layer structure;
2) The substrate layer is made of a resistivity silicon wafer, and the upper surface pattern structure is processed;
3) The device layer is respectively bonded with the cap layer and the substrate layer at a wafer level;
4) Etching the TSV through hole;
5) The TSV through holes are filled with insulating medium layers;
6) The insulating medium layer is reversely etched, and the insulating medium layer at the bottom of the through hole is removed;
7) Filling a conductive material in the TSV through hole;
8) Removing the redundant conductive material layer on the back of the substrate layer;
9) Preparing a metal welding spot;
10 Processing and etching an air isolation groove around the vertical interconnection structure of the substrate layer and etching a leakage hole on the back of the substrate layer of a part of the cavity;
11 The wafer is diced to realize the MEMS chip unit structure.
The processing method of the wafer-level packaging MEMS chip structure comprises the following steps:
1) Processing the device layer and the cap layer structure;
2) Processing a pattern structure on the upper surface of the substrate layer;
3) The device layer is respectively bonded with the cap layer and the substrate layer at a wafer level;
4) Preparing a metal welding spot;
5) Longitudinally etching the isolation layer around the metal welding points of the substrate layer to form a conductive silicon column; etching air leakage holes on the back of the substrate layer of part of the cavity;
6) And cutting the wafer to realize the MEMS chip unit structure.
Preferably, the step 1) of processing the device layer and the cap layer structure comprises the following steps:
1.1 oxidizing the silicon wafer of the device layer;
1.2 photoetching and corroding the silicon oxide on the device layer to form a silicon oxide pattern consistent with the anchor area pattern on the bonding surface;
1.3, photoetching and dry etching the silicon wafer of the device layer to form an anchor area pattern;
1.4, directly bonding the device layer silicon wafer and the cap layer silicon wafer by silicon-silicon oxide;
1.5 thinning the device layer silicon wafer;
and 1.6, photoetching and dry etching are carried out on the device layer to form a comb tooth structure on the device layer and an air isolation groove on the periphery of the device layer.
Preferably, the step 2) of processing the graphic structure on the upper surface of the substrate layer comprises the following steps:
2.1 oxidizing a silicon wafer of the substrate layer;
2.2, performing single-side photoetching corrosion on the substrate layer silicon wafer to form a silicon oxide pattern structure on the bonding surface;
2.3 carrying out wet etching on silicon on the substrate layer to form a boss structure of silicon;
2.4, corroding the rest silicon oxide and carrying out secondary oxidation;
2.5 photoetching and corroding silicon oxide, and forming a contact hole in the silicon oxide on the boss structure;
2.6 growing a first metal layer on the bonding surface, and carrying out photoetching corrosion to form an electrode pattern;
2.7 growing silicon oxide with the same thickness on the front and back surfaces of the substrate layer;
2.8, performing front silicon oxide photoetching corrosion to form a contact hole of the metal electrode;
2.9 growing a second metal layer as a bonding medium layer and carrying out photoetching corrosion to form a bonding medium layer pattern;
2.10 growing getter layer and patterning.
Compared with the prior art, the invention has the beneficial effects that:
(1) Compared with a wafer level packaging structure based on a TSV process, the leading-out mode based on the combination of the transverse electrode and the longitudinal TSV electrode, which is provided by the invention, firstly leads out the connection point of the transverse electrode and the longitudinal TSV electrode to the outside of the sealing ring through the arrangement of the transverse electrode, so that air leakage of a cavity structure is avoided, and the cavity structure has better packaging sealing performance. The wafer level packaging structure based on the TSV process avoids the phenomenon that due to the fact that thermal expansion coefficients of materials are not matched, thermal stress is generated on a silicon-insulating medium interface, an insulating medium interface and a conducting material interface in the TSV through hole due to temperature change, materials at the interface creep deformation occurs, gaps are generated finally, and packaging failure is caused.
(2) The invention makes cavities with different depths on the substrate electrode plate and leaves a step structure with a certain gradient as an anchor area and a bonding sealing ring. Different depths can be set at different positions, and the requirements of reducing the parasitic capacitance of the electrode lead and increasing the longitudinal detection capacitance are met respectively.
(3) The lead wire in the bonding cavity adopts double-layer metal wiring, so that the wiring difficulty is greatly reduced, and the MEMS sensor is suitable for MEMS sensor structures with complex circuit structures. A large-area capacitor plate can be prepared on the second metal layer, so that the motion of the mass block in the longitudinal direction can be detected, and the processing of sensors such as a Z-axis accelerometer, an out-of-plane motion gyroscope and the like can be met.
(4) The invention can simultaneously set the getter to realize high vacuum, no getter to realize low vacuum and normal pressure packaging, can simultaneously meet the requirements of different vacuum degrees on MEMS gyroscope, MEMS acceleration and the like on wafer level packaging, and can realize multi-axis integrated MEMS inertial sensor.
(5) The longitudinal TSV is adopted for interconnection outside the bonding sealing ring, the isolation groove is prepared, the influence of flip chip bonding stress on the MEMS sensor can be obviously reduced, and the temperature stability of the device is improved.
Drawings
FIG. 1a is a schematic structural diagram of a wafer-level packaged MEMS chip which is longitudinally interconnected by TSV filling;
FIG. 1b is a schematic structural diagram of a wafer-level packaged MEMS chip adopting TSV longitudinal interconnection of silicon pillars in the invention;
FIGS. 2 a-2 f are flow diagrams of the processing of the device layer microstructure and the cap layer;
FIGS. 3a to 3j are process flow diagrams of the substrate layer;
FIGS. 4 a-4 h are process flow diagrams of the first embodiment after bonding the combination of the cap layer and the device layer to the substrate layer;
FIGS. 5 a-5 d are process flow diagrams of a second embodiment after bonding the combination of the cap layer and the device layer to the substrate layer.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The invention realizes the structure of the wafer-level packaging MEMS chip by electrical leading-out in a mode of combining the leading-out of the transverse electrode and the leading-out of the longitudinal TSV electrode. The chip comprises a substrate layer 1, a device layer 2 and a cap layer 3, wherein the three layers are bonded together to form a cavity structure 5 containing a movable comb tooth microstructure 4. The anchor region structure 7 of the movable comb teeth of the device layer 2 is bonded with the anchor region structure 10 of the substrate layer 1 through metal eutectic bonding, and is led out from the back of the substrate layer 1 through the first electrode lead layer 12 and the vertical interconnection structure 16 outside the bonding sealing ring 6 to form an electrical lead-out passage, so that a wafer-level packaging MEMS device structure which can be integrated by flip chip bonding is realized.
An anchor region structure 7 for supporting the cap layer 3 is formed on the device layer 2, so that a cavity covering the upper surface of the comb tooth structure is formed after the device layer 2 and the cap layer 3 are bonded; and a silicon oxide layer is arranged on the bonding surface of the cap layer 3 and the device layer 2, so that the cap layer 3 is insulated from the device layer 2. An anchor area structure 10 for supporting the device layer 2 is formed on the substrate layer 1, so that a cavity covering the lower surface of the comb tooth structure is formed after the device layer 2 is bonded with the substrate layer 1. The cavities can be set to different depths at different positions, the second metal layer 11 forms electrode leads which are arranged in the deep cavities, and the detection electrodes are arranged in the shallow cavities, so that the requirements of reducing parasitic capacitance of the electrode leads and increasing longitudinal detection capacitance are met respectively.
A first silicon oxide layer 14 and a second silicon oxide layer 13 are arranged on the first metal layer 12 on the surface of the substrate layer 1. The substrate layer 1 anchor structure 10 is a mesa with a slope, and the first metal layer 12 extends from below the mesa to above the mesa. And a second metal layer 11 is distributed on the second silicon dioxide layer 13 at the anchor region structure 10 and is used as a bonding medium layer. The second silicon oxide layer 13 under the anchor position bonding dielectric layer has a through hole so that the first metal layer 12 communicates with the anchor position bonding dielectric layer. On the substrate layer 1, a city wall ring-shaped table top is formed around the chip structure, and a second metal layer 11 is distributed on the city wall ring-shaped table top as a bonding medium layer to form a bonding sealing ring 6 surrounding the comb tooth structure 4. And the first metal layer 12 extends from the substrate layer cavity to the outside of the bonding sealing ring 6, and a second silicon dioxide layer 13 is arranged between the first metal layer 12 and the bonding medium layer, so that the first metal layer 12 is electrically isolated from the bonding medium layer at the bonding sealing ring 6.
And a second metal layer 11 is distributed on the upper surface of the second silicon dioxide layer 13 in the bonding cavity, and the second metal layer 11 is communicated with the first metal layer 12 through a through hole in the second silicon dioxide layer 13, so that two layers of metal wiring are realized. The second metal layer 11 and the first metal layer 11 can be made of different materials, the resistivity of the material of the second metal layer is smaller than that of the material of the first metal layer, low interconnection resistivity is achieved, and the stress of a metal film is reduced by shortening the interconnection length of a single-layer metal lead. The second metal layer 11 can be used for preparing a large-area capacitor plate, so that the movement of the mass block formed by the device layer 2 in the longitudinal direction can be detected, and the processing requirements of sensors such as a Z-axis accelerometer, an out-of-plane movement gyroscope and the like can be met.
The wafer level packaging structure can form a plurality of packaging cavities, the getter layer 15 can be arranged on the second silicon dioxide dielectric layer 13 of a partial cavity of the substrate layer 1, air leakage holes 20 can be manufactured on the back of the substrate layer of the partial cavity, high vacuum and atmospheric pressure packaging can be respectively realized, and the requirement of multi-axis integration of devices with different vacuum packaging requirements such as MEMS gyroscopes, accelerometers and the like can be met. And a support structure is arranged outside the device layer bonding sealing ring 6 and corresponds to the vertical interconnection structure 16, and an air isolation groove 9 is formed around the support structure and used for stress isolation between the MEMS structure chip and the vertical interconnection structure 16.
An air isolation trench 19 is provided around the vertical interconnect 16 of the substrate layer 1 for isolating stress of the vertical interconnect 16.
Example 1
The depth of the cavity of the substrate slice is 2-20 μm, and the thickness of the first silicon oxide layer 14 is 1-3 μm; the first metal electrode layer 15 is one or a combination of more of tungsten, aluminum, titanium, copper, gold, nickel, chromium, tantalum and cobalt, and the thickness is 100nm-300nm; the thickness of the second silicon dioxide layer 16 is 300nm-600nm, the second metal layer 11 also serves as a bonding medium layer and comprises an adhesion barrier layer and a metal eutectic solder layer, the adhesion barrier layer is made of one or a plurality of compositions of Cr, ti, ni and W, and the metal eutectic solder layer is made of one of AuSi, auSn, alGe and CuSn; the thickness of the adhesion barrier layer is 10nm-50nm; the thickness of the metal eutectic solder layer is 0.5-2 μm; a getter layer 18 is also distributed in the cavity on the substrate layer; the getter adopts one or a combination of Ti, zr and V. The thickness of the getter is 200nm-2000nm.
In the present invention, a vertical interconnection structure 16, one implementation form of which is shown in fig. 1a, is implemented by a conductive material in a TSV via, and an insulating dielectric layer 17 is around the conductive metal material. The conductive material in the TSV through hole is made of Cu, au, W and heavily doped polysilicon, and the insulating medium layer is made of silicon oxide, doped silicon oxide, silicon nitride and silicon oxynitride. The growth of the insulating medium layer is realized by an LPCVD mode, and the filling of the conductive material is realized by one mode of electroplating, CVD and PVD.
In another implementation of the vertical interconnect structure 16 of the present invention, as shown in fig. 1b, the longitudinal electrical leads are led out through conductive silicon pillars 21, around which are isolation layers 22. The isolation layer may not be filled with a medium, or may be filled with a medium. The dielectric material can be selected from silicon oxide, doped silicon oxide, silicon nitride, silicon oxynitride, glass slurry and organic materials. The dielectric layer can only cover the surface of the silicon material, and the isolation groove can also be tightly filled.
The processing method of the wafer-level packaging MEMS chip structure based on combination of the transverse electrode lead-out and the longitudinal TSV electrode lead-out comprises three large processes, wherein the first process is processing of a device layer microstructure and a cap layer, and the second process is processing of a substrate layer; and the third is the bonding and longitudinal electrode of the combination of the device layer and the cap layer and the substrate layer.
Example 2
The first process is the processing of the device layer and the cap layer, the processing flow is shown in fig. 2, and the detailed processing process is described in conjunction with fig. 2 as follows:
1) Silicon wafer oxidation of the device layer, as shown in fig. 2a;
2) Photoetching and corroding the silicon oxide to form a silicon oxide pattern which is consistent with the anchor area pattern on the bonding surface, as shown in figure 2b;
3) Photoetching and dry etching are carried out on the silicon wafer of the device layer to form an anchor region pattern, as shown in figure 2 c;
4) Performing silicon-silicon oxide direct bonding on the device layer silicon wafer and the cap layer silicon wafer, as shown in fig. 2 d;
5) Thinning the device layer silicon wafer as shown in fig. 2 e;
6) Photoetching and dry etching are carried out on the device layer to realize the etching of the microstructure on the device layer, as shown in figure 2 f;
the second flow is the processing of the substrate layer, the processing flow is shown in fig. 3, and the detailed processing procedure is described as follows in conjunction with fig. 3:
1) Oxidizing the silicon wafer of the substrate layer, as shown in FIG. 3 a;
2) Performing single-side photoetching corrosion on the substrate layer silicon wafer to form a silicon oxide pattern structure on the bonding surface, as shown in FIG. 3 b;
3) Performing wet etching of silicon on the silicon wafer of the substrate layer to form a boss structure of silicon, as shown in fig. 3 c;
4) Etching off the remaining silicon oxide and performing a second oxidation, as shown in fig. 3 d;
5) Photoetching and corroding the silicon oxide to form a contact hole, as shown in figure 3 e;
6) Growing a metal electrode layer on the bonding surface, and performing photoetching corrosion to form an electrode pattern, as shown in fig. 3 f;
7) Growing silicon oxide with the same thickness on the front and back surfaces of the substrate layer, as shown in FIG. 3 g;
8) Performing single-sided photoetching corrosion to form a contact hole of the metal electrode, as shown in FIG. 3 h;
9) Growing a bonding medium layer and carrying out photoetching corrosion to form a bonding medium layer pattern as shown in FIG. 3 i;
10 Getter layer is grown and patterned as shown in fig. 3 j.
The third process is the bonding of the combination of the device layer and the cap layer and the substrate layer and the subsequent longitudinal electrode leading-out processing, and the detailed processing process is explained as follows:
the third process of the wafer level packaging MEMS chip structure of the vertical interconnect structure as shown in FIG. 1a comprises the following steps:
1) The device layer is wafer level bonded with the cover plate layer and the substrate layer as shown in fig. 4 a;
2) TSV via etching, as shown in FIG. 4 b;
3) The TSV through holes are filled with insulating medium layers, as shown in FIG. 4 c;
4) Etching back the insulating medium layer, and removing the insulating medium layer at the bottom of the through hole as shown in FIG. 4 d;
5) Filling a conductive material in the TSV through hole, as shown in fig. 4 e;
6) Removing the excess conductive material layer on the back of the substrate layer, as shown in fig. 4 f;
7) Preparing a metal welding spot as shown in fig. 4 g;
8) Etching the isolation trench and the leakage hole as shown in FIG. 4 h;
9) And (4) cutting the wafer to realize the single MEMS chip unit structure.
The third process of the wafer level packaging MEMS chip structure of the vertical interconnect structure as shown in FIG. 1b comprises the following steps:
1) The device layer is wafer level bonded with the cover plate layer and the substrate layer as shown in fig. 5 a;
2) Photoetching contact holes, as shown in FIG. 5 b;
2) Sputtering a metal layer, and photoetching and etching to form a metal welding spot as shown in FIG. 5 c;
3) Etching the TSV isolation grooves and the gas leakage grooves, as shown in FIG. 5 d;
4) And (4) cutting the wafer to realize the single MEMS chip unit structure.
Matters not described in detail in the present description are common general knowledge in the art.
While the invention has been described with reference to specific preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims (16)
1. A wafer level packaging MEMS chip structure is characterized in that a substrate layer (1), a device layer (2) and a cap layer (3) are sequentially bonded in a wafer bonding mode twice to form a cavity structure (5), and the cavity structure is sealed through a bonding sealing ring (6); forming a first metal layer (12) along the surface of the substrate layer (1), and leading out the first metal layer (12) from the back surface of the substrate layer (1) by using a vertical interconnection structure (16) to form an electrical leading-out path; the connection position of the vertical interconnection structure (16) and the first metal layer (12) is positioned outside the cavity structure sealed by the bonding sealing ring (6);
the device layer (2) forms a comb tooth structure (4);
the cap layer (3) is supported by the anchor region structure (7) of the device layer (2), so that a cavity covering the upper surface of the comb structure is formed after the device layer (2) and the cap layer (3) are bonded; a silicon oxide layer (8) is arranged on the bonding surface of the cap layer and the device layer to realize the insulation of the cap layer and the device layer;
the vertical interconnection structure (16) is led out through a conductive silicon column (21), an isolation layer (22) is arranged around the conductive silicon column, and a metal welding spot (18) is arranged at the lower end of the conductive silicon column;
a second silicon dioxide layer (13) and a first silicon oxide layer (14) are respectively distributed on the upper part and the lower part of the first metal layer (12) on the surface of the substrate layer (1); the substrate layer (1) is characterized in that the anchor region structure (10) is a table top with a certain gradient, and the first metal layer (12) extends from the lower part of the table top to the upper part of the table top; a second metal layer (11) is distributed on a second silicon dioxide layer (13) at the anchor region structure (10) of the substrate layer (1) and is used as a bonding medium layer; the second silicon dioxide layer (13) at the anchor region structure (10) of the substrate layer (1) is provided with a through hole, so that the first metal layer (12) is communicated with the second metal layer (11);
the resistivity of the material of the second metal layer is smaller than that of the material of the first metal layer;
an anchor area structure (10) used for supporting the device layer (2) is formed on the substrate layer (1), so that a cavity covering the lower surface of the comb tooth structure is formed after the device layer (2) is bonded with the substrate layer (1); the cavity is formed by carrying out wet etching on silicon on a substrate silicon chip;
the depth of the substrate cavity is 2-20 μm, and the thickness of the first silicon oxide layer (14) is 1-3 μm; the thickness of the first metal layer (12) is 100nm-300nm; the thickness of the second silicon dioxide layer (13) is 300nm-600nm, the thickness of the adhesion barrier layer in the second metal layer (11) is 10nm-50nm, and the thickness of the metal eutectic solder layer is 0.5 mu m-2 mu m;
the second metal layer (11) forms an electrode lead and is arranged in the deep cavity, the second metal layer (11) forms a detection capacitor polar plate and is arranged in the shallow cavity, and the detection of the movement of the device layer (2) structure in the longitudinal direction is realized;
according to the wafer-level packaging MEMS chip structure, a plurality of packaging cavities are formed, the getter layer (15) is arranged on the second silicon dioxide layer (13) of the partial packaging cavity of the substrate layer (1) to achieve high-vacuum packaging, and the air leakage holes (20) are formed in the back of the substrate layer of the partial cavity to achieve atmospheric packaging.
2. Wafer-level packaging MEMS chip structure according to claim 1, characterized in that the substrate layer (1) is provided with cavities by etching, leaving inside the substrate layer (1) cavities anchor structures (10) supporting the device layer (2); different depths are set at different positions of the cavity of the substrate layer (1), the electrode lead is arranged at the position with the deeper depth, and the detection electrode is arranged at the position with the shallower depth.
3. The wafer-level packaging MEMS chip structure of claim 1, characterized in that on the substrate layer (1), the periphery of the chip structure forms a city wall-shaped ring mesa, and a second metal layer (11) is laid on the ring mesa as a bonded dielectric layer to form a bonded seal ring (6) surrounding the comb tooth structure (4); the first metal layer (12) extends from the cavity of the substrate layer to the outside of the cavity of the substrate layer (1), and a second silicon dioxide layer (13) is arranged between the first metal layer (12) and the sealing ring (6) so that the first metal layer (12) is electrically isolated from the bonding dielectric layer at the bonding sealing ring (6).
4. The wafer-level package MEMS chip structure of claim 3, characterized in that the second metal layer (11) and the first metal layer (12) are made of different materials; the thickness of the second metal layer is larger than that of the first metal layer; the second metal layer is used as a main wiring layer, and the first metal layer is used as a jumper layer, so that the lead resistance is reduced.
5. The wafer-level packaging MEMS chip structure of claim 1, wherein the getter in the getter layer (15) is one or more of Ti, zr and V, and the thickness is 200nm to 2000nm.
6. The wafer-level package MEMS chip structure of claim 1, characterized in that there is a support structure outside the device layer bond seal ring (6) corresponding to the vertical interconnect structure (16), and a longitudinal air isolation trench (9) is provided at the periphery of the support structure to isolate the stress between the vertical interconnect structure (16).
7. Wafer level packaged MEMS chip structure according to claim 1, characterized in that an air isolation trench (19) is provided around the vertical interconnects (16) of the substrate layer (1) to isolate the stress of the vertical interconnects (16).
8. The wafer-level packaging MEMS chip structure of claim 1, characterized in that the vertical interconnection structure (16) is realized by filling an insulating medium layer (17) on the inner wall of the TSV through hole and filling a conductive material in the insulating medium layer (17); and preparing a metal welding point (18) outside the TSV through hole.
9. The wafer-level package MEMS chip structure of claim 8, wherein the conductive material in the TSV via is one of Cu, au, W and heavily doped polysilicon, and the insulating dielectric layer (17) is one of silicon oxide, doped silicon oxide, silicon nitride and silicon oxynitride.
10. The wafer-level package MEMS chip structure of claim 8, wherein the dielectric layer growth is achieved by LPCVD and the conductive material filling is achieved by one of electroplating, CVD and PVD.
11. Wafer level package MEMS chip structure according to claim 1, characterized in that the substrate layer (1) is a resistivity silicon wafer.
12. The wafer-level packaged MEMS chip structure of claim 11 wherein the isolation layer is not filled with a dielectric or is filled with a dielectric; the filling medium material is selected from silicon oxide, doped silicon oxide, silicon nitride, silicon oxynitride, glass slurry and organic material; the dielectric layer formed by filling the dielectric only covers the surface of the silicon material or is filled with the isolation layer (22).
13. The method for processing a wafer-level package MEMS chip structure according to claim 8, comprising the steps of:
1) processing the structures of a device layer (2) and a cap layer (3);
2) The substrate layer (1) is made of a resistivity silicon wafer, and the upper surface pattern structure is processed;
3) The device layer (2) is respectively bonded with the cap layer (3) and the substrate layer (1) at wafer level;
4) Etching the TSV through hole;
5) The TSV through holes are filled with insulating medium layers;
6) The insulating medium layer is reversely etched, and the insulating medium layer at the bottom of the through hole is removed;
7) Filling a conductive material in the TSV through hole;
8) Removing the redundant conductive material layer on the back of the substrate layer (1);
9) Preparing a metal welding spot (18);
10 Processing and etching an air isolation groove (19) at the periphery of a vertical interconnection structure (16) of the substrate layer (1) and etching a leakage hole (20) at the back of the substrate layer of a part of the cavity;
11 The wafer is diced to realize the MEMS chip unit structure.
14. A method for fabricating a wafer-level packaged MEMS chip structure as claimed in claim 11, comprising the steps of:
1) processing the structures of a device layer (2) and a cap layer (3);
2) Processing a pattern structure on the upper surface of the substrate layer (1);
3) The device layer (2) is respectively bonded with the cap layer (3) and the substrate layer (1) at wafer level;
4) Preparing a metal welding spot;
5) Longitudinally etching the isolation layer (22) around the metal welding point of the substrate layer (1) to form a conductive silicon column (21); etching a leakage hole (20) on the back of a part of the cavity substrate layer;
6) And cutting the wafer to realize the MEMS chip unit structure.
15. A method for processing a wafer-level packaged MEMS chip structure according to claim 13 or 14, wherein the processing of the device layer (2) and cap layer (3) structure in step 1) comprises the following steps:
1.1, oxidizing the silicon wafer of the device layer (2);
1.2 photoetching and corroding the silicon oxide on the device layer (2) to form a silicon oxide pattern consistent with the anchor area pattern on the bonding surface;
1.3, photoetching and dry etching the silicon wafer of the device layer to form an anchor region pattern;
1.4, directly bonding the device layer silicon wafer and the cap layer silicon wafer by silicon-silicon oxide;
1.5 thinning the device layer silicon wafer;
and 1.6, photoetching and dry etching are carried out on the device layer to form a comb tooth structure (4) on the device layer and an air isolation groove (9) at the periphery of the device layer.
16. A method for processing a wafer-level packaging MEMS chip structure according to claim 13 or 14, wherein the processing of the pattern structure on the surface of the substrate layer (1) in step 2) comprises the following steps:
2.1 oxidizing a silicon wafer of the substrate layer;
2.2, performing single-side photoetching corrosion on a substrate layer silicon wafer to form a silicon oxide pattern structure on a bonding surface;
2.3 carrying out wet etching on silicon on the substrate layer to form a boss structure of silicon;
2.4, corroding the rest silicon oxide and carrying out secondary oxidation;
2.5 photoetching and corroding silicon oxide, and forming a contact hole in the silicon oxide on the boss structure;
2.6 growing a first metal layer (12) on the bonding surface, and carrying out photoetching corrosion to form an electrode pattern;
2.7 growing silicon oxide with the same thickness on the front and back surfaces of the substrate layer;
2.8, performing front silicon oxide photoetching corrosion to form a contact hole of the metal electrode;
2.9 growing a second metal layer (11) as a bonding medium layer and carrying out photoetching corrosion to form a bonding medium layer pattern;
2.10 growing a getter layer (15) and patterning it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910730860.3A CN110467148B (en) | 2019-08-08 | 2019-08-08 | Wafer-level packaging MEMS chip structure and processing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910730860.3A CN110467148B (en) | 2019-08-08 | 2019-08-08 | Wafer-level packaging MEMS chip structure and processing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110467148A CN110467148A (en) | 2019-11-19 |
| CN110467148B true CN110467148B (en) | 2022-12-27 |
Family
ID=68511703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910730860.3A Active CN110467148B (en) | 2019-08-08 | 2019-08-08 | Wafer-level packaging MEMS chip structure and processing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110467148B (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111174951A (en) * | 2020-01-06 | 2020-05-19 | 武汉大学 | Piezoelectric sensor and preparation method thereof |
| CN111377396A (en) * | 2020-02-26 | 2020-07-07 | 北京大学（天津滨海）新一代信息技术研究院 | Packaging device and method based on anodic bonding |
| CN111392688A (en) * | 2020-02-26 | 2020-07-10 | 北京大学（天津滨海）新一代信息技术研究院 | Packaging device and method based on anodic bonding |
| CN112345795A (en) * | 2020-11-09 | 2021-02-09 | 哈尔滨工业大学 | Accelerometer |
| CN112194097B (en) * | 2020-12-07 | 2021-05-07 | 中芯集成电路制造(绍兴)有限公司 | Inertial sensor and forming method thereof |
| CN112624031B (en) * | 2020-12-18 | 2022-10-21 | 北京航天控制仪器研究所 | MEMS structure with over-etching barrier layer and preparation method thereof |
| CN112802820B (en) * | 2021-01-15 | 2022-03-11 | 上海航天电子通讯设备研究所 | Three-dimensional packaging structure based on silicon-aluminum alloy vertical interconnection packaging substrate and LCP rewiring and preparation method |
| CN112875641B (en) * | 2021-01-29 | 2024-01-26 | 矽力杰半导体技术(杭州)有限公司 | Integrated structure of MEMS device and circuit device and manufacturing method thereof |
| CN113023660B (en) * | 2021-03-26 | 2023-06-23 | 华南农业大学 | Single-board double-side wiring type micro-mechanical structure and preparation method thereof |
| CN113336182B (en) * | 2021-05-19 | 2023-05-26 | 中山大学南昌研究院 | Micro-electromechanical system packaging structure and preparation method thereof |
| CN113562685A (en) * | 2021-07-26 | 2021-10-29 | 美满芯盛(杭州)微电子有限公司 | Blind hole structure of MEMS device |
| CN114455536A (en) * | 2022-02-08 | 2022-05-10 | 季优科技（上海）有限公司 | Wafer-level three-dimensional packaging method and structure of MEMS gas sensor |
| CN114388366B (en) * | 2022-03-22 | 2022-05-31 | 湖北江城芯片中试服务有限公司 | Preparation method of packaging shell and preparation method of packaging chip |
| CN114877917B (en) * | 2022-04-29 | 2023-07-14 | 清华大学 | Wafer-level packaging-based thin film sensor and manufacturing method thereof |
| CN114894856B (en) * | 2022-04-29 | 2024-04-23 | 清华大学 | MEMS gas sensor based on wafer level packaging and manufacturing method thereof |
| WO2023208208A1 (en) * | 2022-04-29 | 2023-11-02 | 清华大学 | Multi-mode sensor based on wafer-level package, and manufacturing method therefor |
| CN115849298B (en) * | 2023-01-18 | 2023-05-09 | 胜科纳米(苏州)股份有限公司 | Comb tooth layer removing method for chip with comb tooth structure |
| CN116484547B (en) * | 2023-05-09 | 2023-10-03 | 广东工业大学 | Vacuum packaging MEMS gyroscope air leakage analysis method, system, medium and computer |
| CN117509534B (en) * | 2024-01-04 | 2024-03-15 | 苏州敏芯微电子技术股份有限公司 | MEMS chip packaging structure and manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103213936A (en) * | 2012-01-18 | 2013-07-24 | 水木智芯科技（北京）有限公司 | Wafer-level MEMS (Micro Electronics Mechanical Systems) inert device TSV (Through Silicon Via) stack packaging structure |
| CN103523745A (en) * | 2013-10-21 | 2014-01-22 | 安徽北方芯动联科微系统技术有限公司 | Si conductive post based wafer-level packaging method and monolithic integrated MEMS (Micro Electro Mechanical System) chip for same |
| CN107176585A (en) * | 2017-05-24 | 2017-09-19 | 广东合微集成电路技术有限公司 | The piezoresistive pressure sensor and its manufacture method of a kind of suitable surface mount process |
| CN108529550A (en) * | 2018-04-28 | 2018-09-14 | 北京航天控制仪器研究所 | Wafer-level package of MEMS chip structure and its processing method based on wafer bonding technique |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2761028A1 (en) * | 2009-06-02 | 2010-12-09 | Micralyne Inc. | Semi-conductor sensor fabrication |
| US20140225206A1 (en) * | 2013-02-11 | 2014-08-14 | Yizhen Lin | Pressure level adjustment in a cavity of a semiconductor die |
| US9656857B2 (en) * | 2014-11-07 | 2017-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Microelectromechanical systems (MEMS) devices at different pressures |
-
2019
- 2019-08-08 CN CN201910730860.3A patent/CN110467148B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103213936A (en) * | 2012-01-18 | 2013-07-24 | 水木智芯科技（北京）有限公司 | Wafer-level MEMS (Micro Electronics Mechanical Systems) inert device TSV (Through Silicon Via) stack packaging structure |
| CN103523745A (en) * | 2013-10-21 | 2014-01-22 | 安徽北方芯动联科微系统技术有限公司 | Si conductive post based wafer-level packaging method and monolithic integrated MEMS (Micro Electro Mechanical System) chip for same |
| CN107176585A (en) * | 2017-05-24 | 2017-09-19 | 广东合微集成电路技术有限公司 | The piezoresistive pressure sensor and its manufacture method of a kind of suitable surface mount process |
| CN108529550A (en) * | 2018-04-28 | 2018-09-14 | 北京航天控制仪器研究所 | Wafer-level package of MEMS chip structure and its processing method based on wafer bonding technique |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110467148A (en) | 2019-11-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110467148B (en) | Wafer-level packaging MEMS chip structure and processing method thereof | |
| US8748998B2 (en) | Sensor module | |
| TWI594943B (en) | Process to produce a hybrid integrated component , and such a hybrid integrated component | |
| US10486964B2 (en) | Method for forming a micro-electro mechanical system (MEMS) including bonding a MEMS substrate to a CMOS substrate via a blocking layer | |
| EP2727136B1 (en) | Process for a sealed mems device with a portion exposed to the environment | |
| TWI533438B (en) | Semiconductor apparatus, semiconductor structure, and method of forming semiconductor structure | |
| US9581512B2 (en) | Pressure sensor with deformable membrane and method of manufacture | |
| KR101840925B1 (en) | Semiconductor device and method for fabricating the same | |
| JP2008046078A (en) | Micro electromechanical system element and manufacturing method thereof | |
| US9422152B2 (en) | Hybridly integrated module having a sealing structure | |
| JP2015515609A (en) | Catheter die and manufacturing method thereof | |
| US9840410B2 (en) | Micromechanical component | |
| US9790084B2 (en) | Micromechanical sensor device | |
| CN107963609B (en) | A kind of total silicon MEMS wafer-grade vacuum encapsulation method based on anode linkage | |
| TW201542442A (en) | IC and method for manufacturing IC of sensor device | |
| CN107265397B (en) | Piezoresistive acceleration sensor suitable for surface mounting process and manufacturing method thereof | |
| CN108692836B (en) | MEMS device including capacitive pressure sensor and method of manufacturing the same | |
| US11097942B2 (en) | Through silicon via (TSV) formation in integrated circuits | |
| US20180141803A1 (en) | Mems component having low-resistance wiring and method for manufacturing it | |
| US8461656B2 (en) | Device structures for in-plane and out-of-plane sensing micro-electro-mechanical systems (MEMS) | |
| CN107697882B (en) | Process for manufacturing a semiconductor device and corresponding semiconductor device | |
| TWI652728B (en) | Epi-poly etch stop for out of plane spacer defined electrode | |
| EP2725334B1 (en) | A pressure sensor having a membrane and a method for fabricating the same | |
| CN103229290A (en) | Eutectic bonding of thin chips on a carrier substrate | |
| EP2266920A2 (en) | Interface lid for hermetic MEMS package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |