CN110467148A - A kind of wafer-level package of MEMS chip structure and its processing method - Google Patents
A kind of wafer-level package of MEMS chip structure and its processing method Download PDFInfo
- Publication number
- CN110467148A CN110467148A CN201910730860.3A CN201910730860A CN110467148A CN 110467148 A CN110467148 A CN 110467148A CN 201910730860 A CN201910730860 A CN 201910730860A CN 110467148 A CN110467148 A CN 110467148A
- Authority
- CN
- China
- Prior art keywords
- layer
- wafer
- silicon
- metal
- level package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0006—Interconnects
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Micromachines (AREA)
Abstract
The present invention relates to a kind of wafer-level package of MEMS chip structure and its processing methods, are successively bonded by cap, device layer and substrate layer, form the mobile cavity structure of a comb teeth micro-structure for device layer.The first layer wire spans substrate bonding sealing ring that electrical signal passes through the double-level-metal lead arranged on substrate layer first in package cavity body is drawn from texture edge, after completing metal eutectic bonding wafers grade Vacuum Package, through-hole is formed by carrying out deep silicon etching in substrate wafer back side metal electrode corresponding position, through-hole is filled using conductive material or forms conductive silicon column, overleaf carries out electrode extraction.The mode that flip chip bonding can be used in the structure is realized integrated with signal processing circuit, compared with making TSV through hole out of package cavity and carrying out electricity lead-out mode, the packaging air tightness problem as caused by dielectric filling cavity is avoided, temperature stability and integrity problem as caused by packing material and silicon materials coefficient of thermal expansion mismatch are also avoided.
Description
Technical field
The invention belongs to MEMS (MEMS) manufacturing technology fields, and in particular to a kind of wafer-level package of MEMS chip
Structure and its processing method.
Background technique
Wafer-Level Packaging Technology, by way of wafer bonding, disposable realize carries out gas to the device on full wafer wafer
Close or Vacuum Package, and complete room machine and the electrical connection of MEMS chip different structure level.Potting process is simplified,
Packaging cost is reduced, while also greatly reducing the overall dimension of device.Wafer-level vacuum package can be to greatest extent
The pollution for protecting movable structure water flow and the particle during cutting-up in MEMS device, advantageously reduces batch cost, improves
Consistency, yield rate and the reliability of product.
Using longitudinally perpendicular electrode lead-out process, realizes that wafer-level packaging longitudinal direction electricity interlinkage is drawn, flip chip bonding can be used
The mode of (Flip chip) realizes that MEMS device and IC processing chip are three-dimensional stacked, greatly reduction overall dimension, makes MEMS
Product have mass, small size, low cost advantage, convenient for be applied to various mini systems in.
The devices such as MEMS resonator, MEMS gyroscope, MEMS infrared sensor need work ability under high vacuum state
Ensure its optimum performance, micro- movable structure of MEMS resonator and inertia device etc. needs work at a resonant condition, vacuum seal
Dress can reduce air damping as far as possible, the Q value of resonance be improved, to obtain higher measuring accuracy；MEMS infrared sensing
Device needs to carry out high vacuum encapsulation to it, to reduce cross-ventilation heat dissipation, to improve sensitivity.
In the MEMS wafer grade Vacuum Package using longitudinal direction TSV electrode lead-out mode, the electrode lead-out structures such as through silicon via
It is the greateset risk factor for causing vacuum sealing to leak.Micro-structure in vacuum chamber needs to realize by through silicon via mode and the external world
Interconnection.In order to meet the requirement of electrical insulation and leakproofness, need to fill dielectric and conductive material in through silicon via.In height
A process difficulties existing for packing material are how to guarantee that there is no holes for inside in the deep hole of depth-to-width ratio.How through-hole is guaranteed
Sealing, and it is permanently effective, meet condition of high vacuum degree wafer level packaging and requires to be current restrict based on TSV lead-out mode wafer scale vacuum
The crucial problem of packaging technology.High-performance MEMS device, which needs to meet in different temperatures variation range, to be worked normally, and TSV through hole
Difference of thermal expansion coefficients is larger between dielectric, conductive material and silicon materials in filling, between temperature changing process median surface
It is easy to generate gap under the action of stress, Vacuum Package is caused to fail.Storeroom thermal expansion coefficient in another aspect TSV technique
Difference is big, and caused thermal stress issues also will affect the characterisitic parameter of MEMS chip, causes chip core under condition of different temperatures
Piece characterisitic parameter drift, such as the full temperature zero drift of MEMS gyro and accelerometer.
Summary of the invention
The present invention is in order to overcome Vacuum Package leakproofness existing for the existing wafer-level package of MEMS chip based on TSV technology
Characterisitic parameter drifts about big problem under difference and condition of different temperatures, proposes a kind of wafer-level package of MEMS chip structure and its adds
Transverse electrode is drawn and TSV vertical electrode extraction in longitudinal direction combines by work method.Both there is the structure traditional longitudinal TSV to hang down
Straight electrode lead-out mode wafer level packaging can flip chip bonding, easily three-dimensional stacked integrated advantage, and have that potting is good, temperature
The good advantage of stability.
The technical scheme is that
A kind of wafer-level package of MEMS chip structure is provided, by substrate layer, device layer by way of wafer bonding twice
It is successively bonded with cap three-decker, forms cavity structure, sealed by bonded seal ring；First is formed along substrate layer surface
Metal layer, vertical interconnecting structure draw the first metal layer from the substrate layer back side, form electricity and draw access；Vertical interconnecting structure
It is located on the outside of the cavity structure of bonded seal ring sealing with the junction of the first metal layer.
Preferably, device layer forms a comb structure；The anchoring area structure of device layer is bonded by metal eutectic and substrate
Layer anchoring area structure bonds together to form the cavity of covering comb structure lower surface；
The anchoring area structural support cap of device layer, so that device layer is formed after being bonded with cap on covering comb structure
The cavity on surface；On the bonding face of cap and device layer, there is silicon oxide layer, realize the insulation of cap and device layer.
Preferably, it is formed by etching cavity on the substrate layer, and leaves in substrate layer cavity inside in supporting device
The anchoring area structure of layer；Different depth is arranged in the different location of substrate layer cavity, and contact conductor is arranged in the deeper position of depth,
Detecting electrode is arranged in the latenter position of depth.
Preferably, the substrate layer surface the first metal layer is furnished with the second silicon oxide layer and the first silica respectively up and down
Layer；The substrate layer anchoring area structure is the table top with certain slope, and the first metal layer extends on table top under table top；It is described
Second metal layer is furnished with as bonding medium layer on the second silicon oxide layer at substrate layer anchoring area structure；The substrate layer anchoring area
The second silicon oxide layer at structure has through-hole, so that the first metal layer is connected with second metal layer.
Preferably, described on substrate layer, the surrounding of chip structure forms the ring-like table top of city wall shape, cloth the on ring-like table top
Two metal layers form the bonded seal ring for surrounding comb structure as there is bonding medium layer；The first metal layer, from substrate layer
It is extended in cavity outside substrate layer cavity, the first metal layer and sealing interannular have the second silicon oxide layer at this, so that the first metal
Layer and bonding medium layer electric isolation at bonded seal ring.
Preferably, the second metal layer and the first metal layer use unlike material, and second metal layer material resistivity is small
In the first metal layer material；Second metal layer thickness is greater than the first metal layer；Second metal layer is as primary wiring level, the first metal
Layer is used as wire jumper layer, reduces lead resistance.
Preferably, the second metal layer prepares capacitor plate, what realization moved device layer structure in a longitudinal direction
Detection.
Preferably, which forms multiple encapsulation cavitys, in the second oxygen of substrate layer portion encapsulation cavity
It arranges that getter layer realizes high vacuum encapsulation on SiClx dielectric layer, manufactures leakage hole at the part cavity substrate layer back side, realize big
Air pressure packaging.
Preferably, the getter in getter layer uses the one or more of Ti, Zr, V, with a thickness of 200nm-2000nm；
Preferably, there are support construction, support knots with vertical interconnecting structure corresponding position outside device layer bonded seal ring
Longitudinal air insulated slot, the stress between isolation and vertical interconnecting structure is arranged in structure periphery.
Preferably, air insulated slot is set around substrate layer vertical interconnecting structure, answering for vertical interconnecting structure is isolated
Power.
Preferably, vertical interconnecting structure fills insulating medium layer by TSV through hole inner wall, fills metal in insulating medium layer
Conductive material is realized；Metal solder joints are prepared outside TSV through hole.
Preferably, it is one or more of tungsten, aluminium, titanium, copper, gold, nickel, chromium, tantalum, cobalt that the first metal layer, which uses,；Second
Metal layer includes sticking barrier layer and metal eutectic solder layer, sticks the one or more that barrier layer uses Cr, Ti, Ni, W, gold
Belong to one kind that eutectic solder layer uses AuSi, AuSn, AlGe, CuSn.
Preferably, substrate cavity depth be 2 μm -20 μm, the first silicon oxide layer with a thickness of 1 μm -3 μm；The first metal layer
With a thickness of 100nm-300nm；Second silicon oxide layer with a thickness of sticking barrier layer in 300nm-600nm, second metal layer
With a thickness of 10nm-50nm, metal eutectic solder layer with a thickness of 0.5 μm -2 μm.
Preferably, conductive material is realized using one of Cu, Au, W, heavily doped polysilicon in TSV through hole, dielectric
Layer is realized using one of silica, doped silicon oxide, silicon nitride, silicon oxynitride.
Preferably, the insulating medium layer growth is realized by the way of LPCVD, conductive material filling use plating,
One of CVD, PVD mode are realized.
Preferably, the substrate layer uses resistivity wafers；The vertical interconnecting structure is drawn by conductive silicon column,
It is separation layer around conductive silicon column, lower end is metal solder joints.
Preferably, medium or filled media are not filled in separation layer；Filled media material selection silica, doping oxidation
Silicon, silicon nitride, silicon oxynitride, glass paste, organic material；The dielectric layer that filled media is formed only covers silicon materials surface, or
Full of separation layer.
The processing method of wafer-level package of MEMS chip structure described in one kind is provided, is included the following steps:
1) device layer and cap structure are processed；
2) substrate layer uses resistivity wafers, the processing of upper surface graphic structure；
3) device layer carries out Wafer level bonding with cap and substrate layer respectively；
4) TSV through hole etches；
5) TSV through hole fills insulating medium layer；
6) insulating medium layer anti-carves erosion, removes via bottoms insulating medium layer；
7) conductive material is filled in TSV through hole；
8) substrate layer back side Excess conductive material layer is removed；
9) metal solder joints are prepared；
10) processing etches air insulated slot and at the part cavity substrate layer back side around substrate layer vertical interconnecting structure
Etch leakage hole；
11) cutting-up is carried out to chip, realizes MEMS chip cellular construction.
A kind of processing method of wafer-level package of MEMS chip structure stated is provided, is included the following steps:
1) device layer and cap structure are processed；
2) substrate layer upper surface graphic structure is processed；
3) device layer carries out Wafer level bonding with cap and substrate layer respectively；
4) metal solder joints are prepared；
5) separation layer is longitudinally etched around substrate layer metal solder joints form conductive silicon column；At the part cavity substrate layer back side
Etch leakage hole；
6) cutting-up is carried out to chip, realizes MEMS chip cellular construction.
Preferably, step 1) device layer includes the following steps: with the processing of cap structure
The silicon chip of 1.1 device layers；
1.2 photoetching corrosion device layer silica are formed and the consistent oxidation silicon graphics of anchoring area figure on bonding face；
The silicon wafer of 1.3 device layers carries out photoetching and dry etching, forms anchoring area figure；
1.4 device layer silicon wafers and cap silicon wafer carry out silicon-oxidation Si direct bonding；
1.5 pairs of device layer silicon wafers carry out thinned；
1.6 device layers carry out photoetching, dry etching, formed the air of device layer upper comb dent structure and device layer periphery every
From slot.
Preferably, step 2) substrate layer upper surface graphic structure processing includes the following steps:
2.1 substrate layer silicon wafers are aoxidized；
2.2, which carry out machine glazing on substrate layer silicon wafer, carves corrosion, and silica graphic structure is formed on bonding face；
2.3 pairs of substrate layer silicon wafers carry out the wet etching of silicon, form the boss structure of silicon；
2.4 erode remaining silica, and carry out second and aoxidize；
2.5 photoetching corrosion silica, the silica on boss structure form contact hole；
2.6 grow the first metal layer in bonding face, and carry out photoetching corrosion, form electrode pattern；
2.7 grow the silica of same thickness in substrate layer tow sides；
2.8 carry out front silica photoetching corrosion, form the contact hole of metal electrode；
2.9 growth second metal layers as bonding medium layer and carry out photoetching corrosion, form bonding medium layer pattern；
2.10 growth getter layers are simultaneously patterned.
Compared with the prior art, the invention has the advantages that:
(1) for having compared the wafer-level package structure based on TSV technique, the present invention in provide based on transverse electrode with
The lead-out mode that longitudinal TSV electrode combines is arranged by transverse electrode by the tie point of transverse electrode and longitudinal direction TSV electrode first
It leads to outside sealing ring, avoids cavity structure gas leakage, it is made to have more preferable potting.It avoids based on TSV technique wafer level
In encapsulating structure, since storeroom thermal expansion coefficient mismatch causes, silicon-insulation in TSV through hole is caused by temperature change to be situated between
Matter interface and dielectric and conductive material interface generate thermal stress, make interface material that creep occur, finally generate gap, lead
Cause package failure.
(2) present invention makes the cavity of different depth in underlayer electrode on piece, and the step structure for leaving certain slope is made
For anchoring area and bonded seal ring.Different depth can be set in different location, respectively meet reduce contact conductor parasitic capacitance and
Increase the needs of longitudinal detection capacitor.
(3) intracavitary lead is being bonded due to using two metal wired layers, will greatly reduce wiring difficulty, be suitable for tool
There is complicated circuit construction MEMS sensor structure.Large area capacitor plate can be prepared in second metal layer, realization exists to mass block
The detection moved on longitudinal direction meets the processing of the sensors such as Z axis accelerometer and outer surface movement gyro.
(4) getter can be arranged simultaneously and realize high vacuum, realize low vacuum and atmospheric packaged without getter by the present invention, can
Meet the device disc grade encapsulation of the different vacuum level requirements such as MEMS gyro, MEMS acceleration simultaneously, it can be achieved that multiaxis is integrated
MEMS inertial sensor.
(5) isolation channel is interconnected and is prepared using longitudinal direction TSV outside bonded seal ring, flip chip bonding stress pair can be significantly reduced
The influence of MEMS sensor improves device temperature stability.
Detailed description of the invention
Fig. 1 a is the wafer-level package of MEMS chip structure signal longitudinally interconnected in the present invention using TSV through hole filling mode
Figure；
Fig. 1 b is the wafer-level package of MEMS chip structure schematic diagram longitudinally interconnected in the present invention using silicon column TSV；
Fig. 2 a~Fig. 2 f is the flow process chart of device layer micro-structure and cap；
Fig. 3 a~Fig. 3 j is the flow process chart of substrate layer；
Fig. 4 a~Fig. 4 h is the processing stream after the combination of cap and device layer is bonded with substrate layer in first embodiment
Cheng Tu；
Fig. 5 a~Fig. 5 d is the processing stream after the combination of cap and device layer is bonded with substrate layer in second embodiment
Cheng Tu.
Specific embodiment
The present invention will be further described with reference to the accompanying drawing.The present invention is based on drawn and longitudinal direction TSV by transverse electrode
Electrode draws the mode combined and realizes that electricity draws wafer-level package of MEMS chip structure.Chip include substrate layer 1, device layer 2,
3 three-decker of cap, three-decker are bonded together, and form the cavity structure 5 comprising movable comb micro-structure 4.Device
The anchoring area structure 7 of 2 movable comb of part layer is bonded by metal eutectic bonding with the realization of 1 anchoring area structure 10 of substrate layer, and passes through the
6 outside vertical interconnection structure 16 of one contact conductor layer 12 and bonded seal ring is drawn from 1 back side of substrate layer, is formed electricity and is drawn
Access is realized and the integrated wafer-level package of MEMS device structure of flip chip bonding can be used.
Formed on device layer 2 and be used to support the anchoring area structure 7 of cap 3 so that device layer 2 be bonded with cap 3 after shape
At the cavity of covering comb structure upper surface；On the bonding face of cap 3 and device layer 2, there is silicon oxide layer, realize cap
3 with the insulation of device layer 2.The anchoring area structure 10 for being used to support device layer 2 is formed on substrate layer 1, so that device layer 2 and substrate layer
The cavity of covering comb structure lower surface is formed after 1 bonding.Different depth, the second gold medal can be arranged in the cavity in different location
Belong to the formation contact conductor of layer 11 to be arranged in deep chamber, detecting electrode is arranged in shallow cavity, meets reduce contact conductor respectively
Parasitic capacitance and the needs for increasing longitudinal detection capacitor.
1 about 12 surface the first metal layer of substrate layer is furnished with the first silicon oxide layer 14 and the second silicon oxide layer 13.Substrate layer 1
Anchoring area structure 10 is the table top with certain slope, and the first metal layer 12 extends on table top under table top.At anchoring area structure 10
Second metal layer 11 is furnished on second silicon oxide layer 13 as bonding medium layer.Anchoring area position is bonded the second oxidation under dielectric layer
Silicon layer 13 has through-hole, is connected so that the first metal layer 12 is bonded dielectric layer with anchoring area position.On substrate layer 1, chip knot
The surrounding of structure forms the ring-like table top of city wall shape, and cloth second metal layer 11 forms as there is bonding medium layer and surrounds comb teeth knot thereon
The bonded seal ring 6 of structure 4.The first metal layer 12 extends to outside bonded seal ring 6 from substrate layer cavity, the first metal at this
Layer 12 has the second silicon oxide layer 13 with bonding medium interlayer, so that 6 bonding medium layers at the first metal layer 12 and bonded seal ring
Electric isolation.
13 upper surface of the second silicon oxide layer is furnished with second metal layer 11, second metal layer 11 and the first gold medal in bonding cavity
Belong to layer 12 by the through-hole connection in the second silicon oxide layer 13, realizes double layer of metal wiring.Second metal layer 11 and the first metal
Unlike material can be used in layer 11, and second metal layer material resistivity is less than the first metal layer material, realizes low interconnection resistivity, and
By shortening single-layer metal pin interconnection length, metallic film stress is reduced.Second metal layer 11 can prepare large area capacitance pole
Plate is realized the detection moved in a longitudinal direction to the mass block that device layer 2 is formed, can be met outside Z axis accelerometer and face
Move the needs of the processing of sensors such as gyro.
Wafer-level package structure can form multiple encapsulation cavitys, in the second silicon oxide dielectric layer of 1 portion cavity of substrate layer
Getter layer 15 can be arranged on 13, can manufacture leakage hole 20 at the part cavity substrate layer back side, realize high vacuum and atmosphere respectively
Press seal dress can meet the needs that the device multiaxis that the different Vacuum Packages such as MEMS gyro, accelerometer require integrates.In device layer
Bonded seal ring 6 it is outer with 16 corresponding position of vertical interconnecting structure there are support construction, with air insulated slot around support construction
9, for the stress isolation between MEMS structure chip and vertical interconnecting structure 16.
Air insulated slot 19 is set around 1 vertical interconnecting structure 16 of substrate layer, for vertical interconnecting structure 16 to be isolated
Stress.
Embodiment 1
Substrate slice cavity depth of the present invention be 2 μm -20 μm, the first silicon oxide layer 14 with a thickness of 1 μm -3 μm；First metal
Electrode layer 15 is the composition of one or more of tungsten, aluminium, titanium, copper, gold, nickel, chromium, tantalum, cobalt, with a thickness of 100nm-300nm；
Second silicon oxide layer 16 also includes sticking barrier layer as bonding medium layer with a thickness of 300nm-600nm, second metal layer 11
With metal eutectic solder layer, stick the one or more combination object that barrier layer uses Cr, Ti, Ni, W, metal eutectic solder layer is adopted
With one kind of AuSi, AuSn, AlGe, CuSn；Stick barrier layer with a thickness of 10nm-50nm；The thickness of metal eutectic solder layer
It is 0.5 μm -2 μm；In substrate layer upper plenum, it is also furnished with getter layer 18；Getter is using one kind of Ti, Zr, V and several
Composition.Getter with a thickness of 200nm-2000nm.
Vertical interconnecting structure 16 in the present invention, as shown in fig. 1A, longitudinal electricity is drawn through TSV for a kind of way of realization
Conductive material is realized in through-hole, is insulating medium layer 17 around conductive metal material.In TSV through hole conductive material using Cu, Au,
W, a kind of realization of heavily doped polysilicon, insulating medium layer using silica, doped silicon oxide, silicon nitride, silicon oxynitride one
Kind is realized.Insulating medium layer growth realizes that conductive material filling is using plating, a kind of side of CVD, PVD by the way of LPCVD
Formula is realized.
Vertical interconnecting structure 16 in the present invention, another way of realization is as shown in Figure 1 b, and longitudinal electrical leads pass through
Conductive silicon column 21 is drawn, and is separation layer 22 around conductive silicon column.It can be not filled with medium in separation layer, medium also can be filled.Medium
Silica, doped silicon oxide, silicon nitride, silicon oxynitride, glass paste, organic material can be selected in material.Dielectric layer can be covered only
Silicon materials surface can also fill isolation channel tight.
Being drawn in the present invention based on transverse electrode draws the wafer-level package of MEMS chip knot combined with longitudinal direction TSV electrode
The processing method of structure comprising three big processes, first be device layer micro-structure and cap processing, second be lining
The processing of bottom；Third be device layer with the combination of cap and substrate layer be bonded and longitudinal electrode.
Embodiment 2
First pass is the processing of device layer and cap, and processing flow is as shown in Fig. 2, in conjunction with Fig. 2 to processed in detail
Journey is described as follows:
1) silicon chip of device layer, such as Fig. 2 a；
2) photoetching corrosion silica, formation and the consistent oxidation silicon graphics of anchoring area figure on bonding face, such as Fig. 2 b；
3) silicon wafer of device layer carries out photoetching and dry etching, forms anchoring area figure, as shown in Figure 2 c；
4) device layer silicon wafer and cap silicon wafer carry out silicon-oxidation Si direct bonding, as shown in Figure 2 d；
5) device layer silicon wafer is carried out it is thinned, as shown in Figure 2 e；
6) device layer carries out photoetching, dry etching, realizes the etching of micro-structure on device layer, as shown in figure 2f；
Second procedure is the processing of substrate layer, and processing flow is as shown in figure 3, illustrate such as detailed process in conjunction with Fig. 3
Under:
1) substrate layer silicon wafer is aoxidized, as shown in Figure 3a；
2) machine glazing is carried out on substrate layer silicon wafer and carve corrosion, silica graphic structure is formed on bonding face, such as Fig. 3 b
It is shown；
3) wet etching that silicon is carried out to substrate layer silicon wafer, forms the boss structure of silicon, as shown in Figure 3c；
4) remaining silica is eroded, and carries out second and aoxidizes, as shown in Figure 3d；
5) photoetching corrosion silica forms contact hole, as shown in Figure 3 e；
6) metal electrode layer is grown in bonding face, and carries out photoetching corrosion, form electrode pattern, as illustrated in figure 3f；
7) in the silica of substrate layer tow sides growth same thickness, as shown in figure 3g；
8) single side photoetching corrosion is carried out, forms the contact hole of metal electrode, as illustrated in figure 3h；
9) it grows bonding medium layer and carries out photoetching corrosion, form bonding medium layer pattern, as shown in figure 3i；
10) it grows getter layer and is patterned, as shown in Fig. 3 j.
Third process be device layer with the combination of cap and substrate layer be bonded and subsequent longitudinal electrode is drawn and is processed,
Detailed process is described as follows:
The processing method of the wafer-level package of MEMS chip structure of vertical interconnecting structure as shown in fig. 1A, third stream
Journey includes the following steps:
1) device layer and cover layer and substrate layer carry out Wafer level bonding, as shown in fig. 4 a；
2) TSV through hole etches, as shown in Figure 4 b；
3) TSV through hole fills insulating medium layer, as illustrated in fig. 4 c；
4) insulating medium layer anti-carves erosion, removes via bottoms insulating medium layer, as shown in figure 4d；
5) conductive material is filled in TSV through hole, as shown in fig 4e；
6) substrate layer back side Excess conductive material layer is removed, as shown in fig. 4f；
7) metal solder joints are prepared, as shown in figure 4g；
8) isolation channel and leakage hole etching, as shown in figure 4h；
9) cutting-up is carried out to chip, realizes single MEMS chip cellular construction.
The processing method of the wafer-level package of MEMS chip structure of vertical interconnecting structure as shown in Figure 1 b, third stream
Journey includes the following steps:
1) device layer and cover layer and substrate layer carry out Wafer level bonding, as shown in Figure 5 a；
2) contact hole chemical wet etching, as shown in Figure 5 b；
2) splash-proofing sputtering metal layer, photoetching, etching form metal solder joints, as shown in Figure 5 c；
3) TSV isolation channel and gas leakage are groove etched, as fig 5d；
4) cutting-up is carried out to chip, realizes single MEMS chip cellular construction.
Unspecified item in this explanation is general knowledge known in this field.
The above, optimal specific embodiment only of the invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.
Claims (22)
1. a kind of wafer-level package of MEMS chip structure, which is characterized in that by substrate layer by way of wafer bonding twice
(1), device layer (2) and cap (3) three-decker are successively bonded, and are formed cavity structure (5), close by bonded seal ring (6)
Envelope；The first metal layer (12) are formed along substrate layer (1) surface, vertical interconnecting structure (16) is by the first metal layer (12) from substrate layer
(1) back side is drawn, and is formed electricity and is drawn access；Vertical interconnecting structure (16) is located at the junction of the first metal layer (12) to be bonded
On the outside of the cavity structure of sealing ring (6) sealing.
2. wafer-level package of MEMS chip structure as described in claim 1, which is characterized in that device layer (2) forms a comb
Toothing (4)；The anchoring area structure (7) of device layer (2) is bonded by metal eutectic and is bonded together to form with substrate layer anchoring area structure (10)
Cover the cavity of comb structure (4) lower surface；
The anchoring area structure (7) of device layer (2) supports cap (3), covers so that device layer (2) is formed after being bonded with cap (3)
The cavity of lid comb structure upper surface；On the bonding face of cap and device layer, have silicon oxide layer (8), realize cap with
The insulation of device layer.
3. wafer-level package of MEMS chip structure as claimed in claim 2, which is characterized in that pass through corruption on the substrate layer (1)
Erosion forms cavity, and leaves the anchoring area structure (10) in supporting device layer (2) in substrate layer (1) cavity inside；Substrate layer (1) is empty
The different location of chamber is arranged different depth, and contact conductor is arranged in the deeper position of depth, detecting electrode be arranged in depth compared with
Latent position.
4. wafer-level package of MEMS chip structure as claimed in claim 2, which is characterized in that substrate layer (1) surface
One metal layer (12) is furnished with the second silicon oxide layer (13) and the first silicon oxide layer (14) respectively up and down；Substrate layer (1) anchoring area
Structure (10) is the table top with certain slope, and the first metal layer (12) extends on table top under table top；The substrate layer (1)
Second metal layer (11) is furnished at anchoring area structure (10) on second silicon oxide layer (13) as bonding medium layer；The substrate
The second silicon oxide layer (13) at layer (1) anchoring area structure (10) has through-hole, so that the first metal layer (12) and second metal layer
(11) it is connected.
5. wafer-level package of MEMS chip structure as claimed in claim 4, which is characterized in that described on substrate layer (1), core
The surrounding of chip architecture forms the ring-like table top of city wall shape, and cloth second metal layer (11), which is used as, on ring-like table top bonding medium layer, shape
At the bonded seal ring (6) for surrounding comb structure (4)；The first metal layer (12), extends to substrate from substrate layer cavity
Outside layer (1) cavity, there are the second silicon oxide layer (13) between the first metal layer (12) and sealing ring (6) at this, so that the first metal layer
(12) with bonded seal ring at (6) bonding medium layer electric isolation.
6. wafer-level package of MEMS structure as claimed in claim 5, which is characterized in that the second metal layer (11) and first
Metal layer (11) uses unlike material, and second metal layer material resistivity is less than the first metal layer material；Second metal layer thickness
Greater than the first metal layer；Second metal layer reduces lead resistance as wire jumper layer as primary wiring level, the first metal layer.
7. wafer-level package of MEMS structure as claimed in claim 6, which is characterized in that the second metal layer prepares capacitance pole
Plate realizes the detection moved in a longitudinal direction to device layer (2) structure.
8. wafer-level package of MEMS chip structure as claimed in claim 1 or 2, which is characterized in that the wafer-level package structure shape
At multiple encapsulation cavitys, getter layer is arranged on second silicon oxide dielectric layer (13) of substrate layer (1) partial encapsulation cavity
(15) it realizes high vacuum encapsulation, manufactures leakage hole (20) at the part cavity substrate layer back side, realize atmospheric pressure encapsulation.
9. wafer-level package of MEMS chip structure as claimed in claim 8, which is characterized in that the air-breathing in getter layer (15)
Agent uses the one or more of Ti, Zr, V, with a thickness of 200nm-2000nm.
10. wafer-level package of MEMS chip structure as claimed in claim 1 or 2, which is characterized in that in device layer bonded seal
For ring (6) outside with vertical interconnecting structure (16) corresponding position there are support construction, longitudinal air insulated slot is arranged in support construction periphery
(9), the stress between isolation and vertical interconnecting structure (16).
11. wafer-level package of MEMS chip structure as claimed in claim 1 or 2, which is characterized in that vertical in substrate layer (1)
The stress that vertical interconnecting structure (16) are isolated in air insulated slot (19) is set around interconnection structure (16).
12. wafer-level package of MEMS chip structure as claimed in claim 1 or 2, which is characterized in that vertical interconnecting structure (16)
Insulating medium layer (17) are filled by TSV through hole inner wall, filling conductive metal material is realized in insulating medium layer (17)；TSV is logical
Metal solder joints (18) are prepared outside hole.
13. wafer-level package of MEMS chip structure as described in claim 4 or 5, which is characterized in that the first metal layer (15) is adopted
With being one or more of tungsten, aluminium, titanium, copper, gold, nickel, chromium, tantalum, cobalt；Second metal layer (11) includes sticking barrier layer and gold
Belong to eutectic solder layer, stick barrier layer use Cr, Ti, Ni, W one or more, metal eutectic solder layer using AuSi,
One kind of AuSn, AlGe, CuSn.
14. wafer-level package of MEMS chip structure as claimed in claim 13, which is characterized in that substrate cavity depth be 2 μm-
20 μm, the first silicon oxide layer (14) with a thickness of 1 μm -3 μm；The first metal layer (12) with a thickness of 100nm-300nm；Second oxygen
SiClx layer (13) with a thickness of stick in 300nm-600nm, second metal layer (11) barrier layer with a thickness of 10nm-50nm, gold
Belong to eutectic solder layer with a thickness of 0.5 μm -2 μm.
15. wafer-level package of MEMS chip structure as claimed in claim 12, which is characterized in that conductive material in TSV through hole
It is realized using one of Cu, Au, W, heavily doped polysilicon, insulating medium layer (17) uses silica, doped silicon oxide, nitridation
One of silicon, silicon oxynitride are realized.
16. wafer-level package of MEMS chip structure as claimed in claim 12, which is characterized in that the insulating medium layer growth
It is realized by the way of LPCVD, conductive material filling is realized using one of plating, CVD, PVD mode.
17. wafer-level package of MEMS chip structure as claimed in claim 1 or 2, which is characterized in that the substrate layer (1) is adopted
Use resistivity wafers；The vertical interconnecting structure (16) is drawn by conductive silicon column (21), is separation layer around conductive silicon column
(22), lower end is metal solder joints (18).
18. wafer-level package of MEMS chip structure as claimed in claim 17, which is characterized in that be not filled with medium in separation layer
Or filled media；Filled media material selection silica, doped silicon oxide, silicon nitride, silicon oxynitride, glass paste, You Jicai
Material；The dielectric layer that filled media is formed only covers silicon materials surface, or is full of separation layer (22).
19. a kind of processing method of wafer-level package of MEMS chip structure as claimed in claim 12, which is characterized in that including
Following steps:
1) device layer (2) and cap (3) structure are processed；
2) substrate layer (1) uses resistivity wafers, the processing of upper surface graphic structure；
3) device layer (2) carries out Wafer level bonding with cap (3) and substrate layer (1) respectively；
4) TSV through hole etches；
5) TSV through hole fills insulating medium layer；
6) insulating medium layer anti-carves erosion, removes via bottoms insulating medium layer；
7) conductive material is filled in TSV through hole；
8) substrate layer (1) back side Excess conductive material layer is removed；
9) metal solder joints (18) are prepared；
10) processing etches air insulated slot (19) and serves as a contrast in part cavity around substrate layer (1) vertical interconnecting structure (16)
Back-side etches leakage hole (20)；
11) cutting-up is carried out to chip, realizes MEMS chip cellular construction.
20. a kind of processing method of wafer-level package of MEMS chip structure as claimed in claim 17, which is characterized in that including
Following steps:
1) device layer (2) and cap (3) structure are processed；
2) substrate layer (1) upper surface graphic structure is processed；
3) device layer (2) carries out Wafer level bonding with cap (3) and substrate layer (1) respectively；
4) metal solder joints are prepared；
5) separation layer (22) are longitudinally etched around substrate layer (1) metal solder joints forms conductive silicon column (21)；It is served as a contrast in part cavity
Back-side etches leakage hole (20)；
6) cutting-up is carried out to chip, realizes MEMS chip cellular construction.
21. a kind of processing method of the wafer-level package of MEMS chip structure as described in claim 19 or 20, feature exist
In device layer (2) and cap (3) structure are processed in step 1), are included the following steps:
The silicon chip of 1.1 device layers (2)；
1.2 photoetching corrosion device layer (2) silica are formed and the consistent oxidation silicon graphics of anchoring area figure on bonding face；
The silicon wafer of 1.3 device layers carries out photoetching and dry etching, forms anchoring area figure；
1.4 device layer silicon wafers and cap silicon wafer carry out silicon-oxidation Si direct bonding；
1.5 pairs of device layer silicon wafers carry out thinned；
1.6 device layers carry out photoetching, dry etching, formed the air of device layer upper comb dent structure (4) and device layer periphery every
From slot (9).
22. a kind of processing method of the wafer-level package of MEMS chip structure as described in claim 19 or 20, feature exist
In the processing of substrate layer (1) upper surface graphic structure includes the following steps: in step 2)
2.1 substrate layer silicon wafers are aoxidized；
2.2, which carry out machine glazing on substrate layer silicon wafer, carves corrosion, and silica graphic structure is formed on bonding face；
2.3 pairs of substrate layer silicon wafers carry out the wet etching of silicon, form the boss structure of silicon；
2.4 erode remaining silica, and carry out second and aoxidize；
2.5 photoetching corrosion silica, the silica on boss structure form contact hole；
2.6 grow the first metal layer (12) in bonding face, and carry out photoetching corrosion, form electrode pattern；
2.7 grow the silica of same thickness in substrate layer tow sides；
2.8 carry out front silica photoetching corrosion, form the contact hole of metal electrode；
2.9 growths second metal layer (11) are as bonding medium layer and carry out photoetching corrosion, form bonding medium layer pattern；
2.10 growths getter layer (15) are simultaneously patterned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910730860.3A CN110467148B (en) | 2019-08-08 | 2019-08-08 | Wafer-level packaging MEMS chip structure and processing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910730860.3A CN110467148B (en) | 2019-08-08 | 2019-08-08 | Wafer-level packaging MEMS chip structure and processing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110467148A true CN110467148A (en) | 2019-11-19 |
| CN110467148B CN110467148B (en) | 2022-12-27 |
Family
ID=68511703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910730860.3A Active CN110467148B (en) | 2019-08-08 | 2019-08-08 | Wafer-level packaging MEMS chip structure and processing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110467148B (en) |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111174951A (en) * | 2020-01-06 | 2020-05-19 | 武汉大学 | Piezoelectric sensor and preparation method thereof |
| CN111377396A (en) * | 2020-02-26 | 2020-07-07 | 北京大学（天津滨海）新一代信息技术研究院 | Packaging device and method based on anodic bonding |
| CN111392688A (en) * | 2020-02-26 | 2020-07-10 | 北京大学（天津滨海）新一代信息技术研究院 | Packaging device and method based on anodic bonding |
| CN112345795A (en) * | 2020-11-09 | 2021-02-09 | 哈尔滨工业大学 | Accelerometer |
| CN112624031A (en) * | 2020-12-18 | 2021-04-09 | 北京航天控制仪器研究所 | MEMS structure with over-etching barrier layer and preparation method thereof |
| CN112802820A (en) * | 2021-01-15 | 2021-05-14 | 上海航天电子通讯设备研究所 | Three-dimensional packaging structure based on silicon-aluminum alloy vertical interconnection packaging substrate and LCP rewiring and preparation method |
| CN112875641A (en) * | 2021-01-29 | 2021-06-01 | 矽力杰半导体技术(杭州)有限公司 | Integrated structure of MEMS device and circuit device and manufacturing method thereof |
| CN113023660A (en) * | 2021-03-26 | 2021-06-25 | 华南农业大学 | Single-board double-side wiring type micro mechanical structure and preparation method thereof |
| CN113336182A (en) * | 2021-05-19 | 2021-09-03 | 中山大学南昌研究院 | Micro electro mechanical system packaging structure and preparation method thereof |
| CN113562685A (en) * | 2021-07-26 | 2021-10-29 | 美满芯盛(杭州)微电子有限公司 | Blind hole structure of MEMS device |
| CN114388366A (en) * | 2022-03-22 | 2022-04-22 | 湖北江城芯片中试服务有限公司 | Preparation method of packaging shell and preparation method of packaging chip |
| CN114455536A (en) * | 2022-02-08 | 2022-05-10 | 季优科技（上海）有限公司 | Wafer-level three-dimensional packaging method and structure of MEMS gas sensor |
| WO2022121529A1 (en) * | 2020-12-07 | 2022-06-16 | 绍兴中芯集成电路制造股份有限公司 | Inertial sensor and formation method therefor |
| CN114877917A (en) * | 2022-04-29 | 2022-08-09 | 清华大学 | Thin film type sensor based on wafer level packaging and manufacturing method thereof |
| CN114894856A (en) * | 2022-04-29 | 2022-08-12 | 清华大学 | MEMS gas sensor based on wafer level packaging and manufacturing method thereof |
| CN115849298A (en) * | 2023-01-18 | 2023-03-28 | 胜科纳米(苏州)股份有限公司 | Comb tooth layer removing method with comb tooth structure chip |
| CN116484547A (en) * | 2023-05-09 | 2023-07-25 | 广东工业大学 | Vacuum packaging MEMS gyroscope air leakage analysis method, system, medium and computer |
| WO2023208208A1 (en) * | 2022-04-29 | 2023-11-02 | 清华大学 | Multi-mode sensor based on wafer-level package, and manufacturing method therefor |
| CN117509534A (en) * | 2024-01-04 | 2024-02-06 | 苏州敏芯微电子技术股份有限公司 | MEMS chip packaging structure and manufacturing method |
| CN118032877A (en) * | 2024-04-10 | 2024-05-14 | 广东迈能欣科技有限公司 | Electronic hydrogen sensor chip and preparation method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120119311A1 (en) * | 2009-06-02 | 2012-05-17 | Micralyne Inc. | Semi-conductor sensor fabrication |
| CN103213936A (en) * | 2012-01-18 | 2013-07-24 | 水木智芯科技（北京）有限公司 | Wafer-level MEMS (Micro Electronics Mechanical Systems) inert device TSV (Through Silicon Via) stack packaging structure |
| CN103523745A (en) * | 2013-10-21 | 2014-01-22 | 安徽北方芯动联科微系统技术有限公司 | Si conductive post based wafer-level packaging method and monolithic integrated MEMS (Micro Electro Mechanical System) chip for same |
| US20140225206A1 (en) * | 2013-02-11 | 2014-08-14 | Yizhen Lin | Pressure level adjustment in a cavity of a semiconductor die |
| US20160130137A1 (en) * | 2014-11-07 | 2016-05-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Microelectromechanical systems (mems) devices at different pressures |
| CN107176585A (en) * | 2017-05-24 | 2017-09-19 | 广东合微集成电路技术有限公司 | The piezoresistive pressure sensor and its manufacture method of a kind of suitable surface mount process |
| CN108529550A (en) * | 2018-04-28 | 2018-09-14 | 北京航天控制仪器研究所 | Wafer-level package of MEMS chip structure and its processing method based on wafer bonding technique |
-
2019
- 2019-08-08 CN CN201910730860.3A patent/CN110467148B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120119311A1 (en) * | 2009-06-02 | 2012-05-17 | Micralyne Inc. | Semi-conductor sensor fabrication |
| CN103213936A (en) * | 2012-01-18 | 2013-07-24 | 水木智芯科技（北京）有限公司 | Wafer-level MEMS (Micro Electronics Mechanical Systems) inert device TSV (Through Silicon Via) stack packaging structure |
| US20140225206A1 (en) * | 2013-02-11 | 2014-08-14 | Yizhen Lin | Pressure level adjustment in a cavity of a semiconductor die |
| CN103523745A (en) * | 2013-10-21 | 2014-01-22 | 安徽北方芯动联科微系统技术有限公司 | Si conductive post based wafer-level packaging method and monolithic integrated MEMS (Micro Electro Mechanical System) chip for same |
| US20160130137A1 (en) * | 2014-11-07 | 2016-05-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Microelectromechanical systems (mems) devices at different pressures |
| CN107176585A (en) * | 2017-05-24 | 2017-09-19 | 广东合微集成电路技术有限公司 | The piezoresistive pressure sensor and its manufacture method of a kind of suitable surface mount process |
| CN108529550A (en) * | 2018-04-28 | 2018-09-14 | 北京航天控制仪器研究所 | Wafer-level package of MEMS chip structure and its processing method based on wafer bonding technique |
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111174951A (en) * | 2020-01-06 | 2020-05-19 | 武汉大学 | Piezoelectric sensor and preparation method thereof |
| CN111377396A (en) * | 2020-02-26 | 2020-07-07 | 北京大学（天津滨海）新一代信息技术研究院 | Packaging device and method based on anodic bonding |
| CN111392688A (en) * | 2020-02-26 | 2020-07-10 | 北京大学（天津滨海）新一代信息技术研究院 | Packaging device and method based on anodic bonding |
| CN112345795A (en) * | 2020-11-09 | 2021-02-09 | 哈尔滨工业大学 | Accelerometer |
| WO2022121529A1 (en) * | 2020-12-07 | 2022-06-16 | 绍兴中芯集成电路制造股份有限公司 | Inertial sensor and formation method therefor |
| CN112624031A (en) * | 2020-12-18 | 2021-04-09 | 北京航天控制仪器研究所 | MEMS structure with over-etching barrier layer and preparation method thereof |
| CN112802820B (en) * | 2021-01-15 | 2022-03-11 | 上海航天电子通讯设备研究所 | Three-dimensional packaging structure based on silicon-aluminum alloy vertical interconnection packaging substrate and LCP rewiring and preparation method |
| CN112802820A (en) * | 2021-01-15 | 2021-05-14 | 上海航天电子通讯设备研究所 | Three-dimensional packaging structure based on silicon-aluminum alloy vertical interconnection packaging substrate and LCP rewiring and preparation method |
| CN112875641A (en) * | 2021-01-29 | 2021-06-01 | 矽力杰半导体技术(杭州)有限公司 | Integrated structure of MEMS device and circuit device and manufacturing method thereof |
| CN112875641B (en) * | 2021-01-29 | 2024-01-26 | 矽力杰半导体技术(杭州)有限公司 | Integrated structure of MEMS device and circuit device and manufacturing method thereof |
| CN113023660B (en) * | 2021-03-26 | 2023-06-23 | 华南农业大学 | Single-board double-side wiring type micro-mechanical structure and preparation method thereof |
| CN113023660A (en) * | 2021-03-26 | 2021-06-25 | 华南农业大学 | Single-board double-side wiring type micro mechanical structure and preparation method thereof |
| CN113336182A (en) * | 2021-05-19 | 2021-09-03 | 中山大学南昌研究院 | Micro electro mechanical system packaging structure and preparation method thereof |
| CN113562685A (en) * | 2021-07-26 | 2021-10-29 | 美满芯盛(杭州)微电子有限公司 | Blind hole structure of MEMS device |
| CN114455536A (en) * | 2022-02-08 | 2022-05-10 | 季优科技（上海）有限公司 | Wafer-level three-dimensional packaging method and structure of MEMS gas sensor |
| CN114388366B (en) * | 2022-03-22 | 2022-05-31 | 湖北江城芯片中试服务有限公司 | Preparation method of packaging shell and preparation method of packaging chip |
| CN114388366A (en) * | 2022-03-22 | 2022-04-22 | 湖北江城芯片中试服务有限公司 | Preparation method of packaging shell and preparation method of packaging chip |
| CN114877917A (en) * | 2022-04-29 | 2022-08-09 | 清华大学 | Thin film type sensor based on wafer level packaging and manufacturing method thereof |
| CN114894856A (en) * | 2022-04-29 | 2022-08-12 | 清华大学 | MEMS gas sensor based on wafer level packaging and manufacturing method thereof |
| CN114894856B (en) * | 2022-04-29 | 2024-04-23 | 清华大学 | MEMS gas sensor based on wafer level packaging and manufacturing method thereof |
| WO2023208208A1 (en) * | 2022-04-29 | 2023-11-02 | 清华大学 | Multi-mode sensor based on wafer-level package, and manufacturing method therefor |
| CN115849298A (en) * | 2023-01-18 | 2023-03-28 | 胜科纳米(苏州)股份有限公司 | Comb tooth layer removing method with comb tooth structure chip |
| CN116484547A (en) * | 2023-05-09 | 2023-07-25 | 广东工业大学 | Vacuum packaging MEMS gyroscope air leakage analysis method, system, medium and computer |
| CN116484547B (en) * | 2023-05-09 | 2023-10-03 | 广东工业大学 | Vacuum packaging MEMS gyroscope air leakage analysis method, system, medium and computer |
| CN117509534A (en) * | 2024-01-04 | 2024-02-06 | 苏州敏芯微电子技术股份有限公司 | MEMS chip packaging structure and manufacturing method |
| CN117509534B (en) * | 2024-01-04 | 2024-03-15 | 苏州敏芯微电子技术股份有限公司 | MEMS chip packaging structure and manufacturing method |
| CN118032877A (en) * | 2024-04-10 | 2024-05-14 | 广东迈能欣科技有限公司 | Electronic hydrogen sensor chip and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110467148B (en) | 2022-12-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110467148A (en) | A kind of wafer-level package of MEMS chip structure and its processing method | |
| CN107265388B (en) | A kind of the pressure resistance type compound sensor and its manufacturing method of suitable surface mount process | |
| US20190120710A1 (en) | Pressure sensor generating a transduced signal with reduced ambient temperature dependence, and manufacturing method thereof | |
| CN103818874B (en) | The method for packing of MEMS structure and treatment circuit integrated system | |
| US8748998B2 (en) | Sensor module | |
| CN105293428B (en) | Full silicification wafer level vacuum encapsulation method and device for MEMS (Micro-Electro-Mechanical System) device | |
| CN102556956B (en) | Vacuum packaging structure of MEMS (Micro Electro Mechanical System) device and manufacture method thereof | |
| CN105293420A (en) | MEMS wafer level vacuum package structure and manufacturing method thereof | |
| US7259436B2 (en) | Micromechanical component and corresponding production method | |
| CN102367165B (en) | Method for interconnecting electrodes of MEMS (micro electro mechanical system) device based on SOI (silicon-on-insulator) | |
| CN102759636B (en) | Capacitive micro-electromechanical system (MEMS) accelerometer and manufacturing method thereof | |
| CN103879952B (en) | The preparation method of MEMS component vacuum encapsulating structure | |
| CN107416760A (en) | Be inverted assembling can stress release MEMS chip encapsulating structure preparation method | |
| CN107512698B (en) | A kind of production method of the quasi- floated MEMS chip encapsulating structure of central supported | |
| CN103552980A (en) | Wafer level packaging method for micro electromechanical system (MEMS) chip and single-chip micro-miniature type MEMS chip | |
| CN108083226A (en) | A kind of MEMS device wafer-grade vacuum encapsulation method | |
| TW201322366A (en) | Sensor manufacturing method | |
| US9334159B2 (en) | Integrated chip with micro-electro-mechanical system and integrated circuit mounted therein and method for manufacturing the same | |
| CN106744656A (en) | A kind of mems device method for packing and structure | |
| CN107963609A (en) | A kind of total silicon MEMS wafer-grade vacuum encapsulation methods based on anode linkage | |
| CN107512700A (en) | A kind of preparation method of central supported formula MEMS chip encapsulating structure | |
| CN107445137A (en) | A kind of MEMS chip encapsulating structure preparation method for being inverted assembling | |
| CN109928359A (en) | Micro-structure packaging method and packaging | |
| CN115709970A (en) | Wafer-level vacuum packaged MEMS device and manufacturing method thereof | |
| CN106315504B (en) | Wafer-level package of MEMS chip with vertical press welding block and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |