CN112875641A

CN112875641A - Integrated structure of MEMS device and circuit device and manufacturing method thereof

Info

Publication number: CN112875641A
Application number: CN202110128547.XA
Authority: CN
Inventors: 李小刚
Original assignee: Hangzhou Silergy Semiconductor Technology Ltd
Current assignee: Hangzhou Silergy Semiconductor Technology Ltd
Priority date: 2021-01-29
Filing date: 2021-01-29
Publication date: 2021-06-01
Anticipated expiration: 2041-01-29
Also published as: CN112875641B

Abstract

The invention provides an integrated structure of an MEMS device and a circuit device and a manufacturing method thereof, wherein the method comprises the following steps: providing a substrate, wherein the substrate comprises a lower supporting layer, an upper device layer and an insulating layer positioned between the supporting layer and the device layer; forming a micromechanical structure in the device layer, the micromechanical structure comprising a fixed portion and a movable portion; providing an upper substrate, forming the upper substrate on the device layer by a bonding technology to form a sealed cavity, wherein the cavity is used for accommodating a movable part of the micromechanical structure; and forming a circuit device in the upper substrate. The MEMS device and the circuit device are integrated in a single chip, so that the integration level is improved, and the process complexity and the manufacturing cost are reduced.

Description

Integrated structure of MEMS device and circuit device and manufacturing method thereof

Technical Field

The invention relates to the field of micro electro mechanical systems, in particular to an integrated structure of an MEMS device and a circuit device and a manufacturing method thereof.

Background

The field of Micro Electro Mechanical Systems (MEMS) relates to the technology of manufacturing Micro electromechanical devices and nano electromechanical devices. In particular, the technique can be applied to the fabrication of high performance processing circuits and microelectromechanical systems devices or nanoelectromechanical systems devices on the same substrate. For example, MEMS velocimeters, gyroscopes, microphones, resonators, etc. all employ fabrication techniques in the MEMS field. MEMS fabrication techniques, similar to ic (integrated circuit) fabrication techniques, are applied to high-precision processes such as photolithography, implantation, etching, etc., and also require the use of MEMS-specific processing techniques such as bulk silicon etching, mask layer release, etc., which are used to form three-dimensional mechanical structures, such as beams, bridges, films, etc., on a substrate, such as a typical single-crystal silicon substrate, and the dimensions of these structures are typically on the order of microns, even on the order of nanometers.

These small mechanical structures often require a contained cavity TO provide mechanical protection, such as by using a TO-8 package TO seal the micromechanical structure inside the cavity through a metal soldering process, or by bonding it TO a substrate having a cavity for containing the mechanical structure. These methods are difficult to be compatible with the processing and manufacturing process of high-performance circuits at low cost, so as to realize the monolithic integrated MEMS microsystem product. These approaches do not provide a manufacturing method for monolithic integration with the circuitry, especially where the MEMS structure needs to operate in a vacuum environment.

Disclosure of Invention

In view of this, the present invention provides an integrated structure of an MEMS device and a circuit device and a method for manufacturing the same, so as to realize monolithic integration of the MEMS device and the circuit device, improve the integration of the device, and reduce the process complexity.

According to a first aspect of the present invention, a method for fabricating an integrated structure of a MEMS device and a circuit device is provided, wherein the method comprises: providing a substrate, wherein the substrate comprises a lower supporting layer, an upper device layer and an insulating layer positioned between the supporting layer and the device layer; forming a micromechanical structure in the device layer, the micromechanical structure comprising a fixed portion and a movable portion; providing an upper substrate, forming the upper substrate on the device layer by a bonding technology to form a sealed cavity, wherein the cavity is used for accommodating a movable part of the micromechanical structure; and forming a circuit device in the upper substrate.

Preferably, the method further comprises forming a conductive via in the upper substrate connected to the micromechanical structure to electrically connect the micromechanical structure outside the cavity.

Preferably, the method of forming the micromechanical structure comprises: forming a first dielectric layer on the substrate; forming patterned photoresist, and etching the first dielectric layer and the device layer to the top of the insulating layer by taking the patterned photoresist as a mask so as to form a plurality of grooves in the device layer; and removing part of the first dielectric layer and the insulating layer to form the micromechanical structure.

Preferably, before forming the patterned photoresist, the method further includes forming a patterned mask layer on the first dielectric layer, where the patterned mask layer has at least a first window forming a movable portion of the micromechanical structure, and the patterned photoresist is at least located on the first dielectric layer exposed by the first window.

Preferably, the method for removing part of the first dielectric layer and the insulating layer comprises: and removing the first dielectric layer and the insulating layer by using the patterned mask layer as a protective layer and adopting an etching method at least until the first dielectric layer on the upper surface of the movable part of the micromechanical structure and the insulating layer on the lower surface of the movable part of the micromechanical structure are completely removed.

Preferably, the method further comprises removing the patterned mask layer.

Preferably, the method of forming the conductive channel includes: forming a first contact hole exposing the first dielectric layer in the upper substrate; forming a second dielectric layer on the inner surface of the first contact hole and the upper surface of the upper substrate; removing the first dielectric layer at the bottom of the first contact hole; and depositing a first conductive material in the first contact hole with the side wall covered with the second dielectric layer and on part of the upper surface of the upper substrate to form the conductive channel.

Preferably, the method of forming the circuit device includes forming a well region of a first doping type in the upper substrate; forming a gate conductor on the second dielectric layer; and forming a drain region of the second doping type and a source region of the second doping type in the well region by a self-aligned ion implantation process.

Preferably, the well region is formed before the second dielectric layer is formed.

Preferably, the second dielectric layer is used as a gate dielectric layer of the circuit device.

Preferably, the first conductive material and the gate conductor are formed in a simultaneous process.

Preferably, the method of forming the first conductive material and forming the gate conductor comprises: depositing a conductive layer in the first contact hole and on the upper surface of the upper substrate; and selectively etching part of the conductive layer on the upper surface of the upper substrate to form the first conductive material and a gate conductor above the well region.

Preferably, the method further comprises: forming a third dielectric layer on the conductive channel, the second dielectric layer and the gate conductor; forming second contact holes respectively exposing parts of the conductive channel, the gate conductor, the drain region and the source region in the third dielectric layer; depositing a second conductive material in the second contact hole.

Preferably, the upper substrate is a silicon substrate, and the first dielectric layer is silicon oxide.

Preferably, the upper substrate is bonded to the upper surface of the first dielectric layer by a silicon melt bonding technique.

Preferably, before forming the conductive channel, the method further includes thinning the upper substrate by a chemical mechanical polishing process.

Preferably, the upper substrate is thinned to 10-15 um.

Preferably, the patterned mask layer is a silicon nitride layer.

Preferably, the device layer is etched using a deep silicon etch process.

Preferably, the first dielectric layer and the insulating layer are etched with hydrofluoric acid or a buffered oxide etchant in a gaseous state.

Preferably, the first conductive material is highly doped polysilicon or a conductive metal.

Preferably, the device layer has a thickness in the range of 5-15 um.

Preferably, the substrate is an SOI substrate.

According to a second aspect of the present invention, an integrated structure of a MEMS device and a circuit device is provided, which includes: a substrate including a lower support layer, an upper device layer, and an insulating layer between the support layer and the device layer, a micromechanical structure included in the device layer, the micromechanical structure including a fixed portion and a movable portion; a first dielectric layer at least on the upper surface of the fixed part of the micromechanical structure; the upper substrate is bonded on the first dielectric layer through a bonding technology; and a circuit device located in the upper substrate, wherein the upper substrate and the substrate form a sealed cavity for accommodating the movable part of the micromechanical structure.

Preferably, the micro-mechanical structure further comprises a conductive channel in the upper substrate for electrically connecting the micro-mechanical structure to the outside of the cavity.

Preferably, the movable part of the micromechanical structure includes at least two separated suspended structures, the first dielectric layer is not included between the upper surface of the movable part of the micromechanical structure and the upper substrate, and the insulating layer is not included between the lower surface of the movable part of the micromechanical structure and the supporting layer.

Preferably, the fixed part of the micromechanical structure is connected to at least one suspension structure of the movable part of the micromechanical structure.

Preferably, the movable part of the micromechanical structure is located between the fixed parts of the micromechanical structure.

Preferably, the conductive via includes a first contact hole in the upper substrate and a first conductive material filling the first contact hole and on at least an upper surface of the upper substrate.

Preferably, the semiconductor device further comprises a second dielectric layer located on the side wall of the first contact hole and the upper surface of the upper substrate.

Preferably, the circuit device includes; a well region of a first doping type located in the upper substrate; a gate conductor on the second dielectric layer; and a source region of the second doping type and a drain region of the second doping type in the well region.

Preferably, the device further comprises a third dielectric layer located on the conductive channel, the second dielectric layer and the gate conductor.

Preferably, the first dielectric layer is silicon oxide.

Preferably, the upper substrate is a silicon substrate.

Preferably, the upper substrate has a thickness ranging from 10 to 15 um.

Preferably, the device layer has a thickness in the range of 5-15 um.

Preferably, the substrate is an SOI substrate.

According to the manufacturing method of the integrated structure of the MEMS device and the circuit device, a substrate comprising a device layer, an insulating layer and a supporting layer is provided, and the device layer is etched to form a micro-mechanical structure; then bonding an upper substrate to the substrate by bonding to form a sealed cavity for accommodating the movable part of the micromechanical structure; finally, a circuit device is formed in the upper substrate and a conductive channel is formed to electrically connect the micromechanical structure to the outside of the cavity. The cavity formed by bonding has low tensile stress, the environmental pressure in the cavity can be adjusted, the sealing performance of the cavity cannot be degraded in the subsequent process, and the performance of a micro-mechanical structure in the cavity cannot be influenced. In addition, the MEMS device and the circuit device are integrated in a single chip, so that the circuit device and the MEMS device with high performance are manufactured on the same substrate, the integration level is improved, and the process complexity and the manufacturing cost are reduced.

Drawings

FIG. 1 is a cross-sectional view of an integrated structure of a MEMS device and a circuit device according to an embodiment of the invention;

fig. 2A-2J are partial, fragmentary, cross-sectional views of a method of fabricating an integrated structure of a MEMS device and a circuit device, in accordance with an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like components are denoted by like reference numerals throughout the various figures. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques for each component, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

Fig. 1 is a cross-sectional view of an integrated structure of a MEMS device and a circuit device according to an embodiment of the present invention.

The integrated structure includes a substrate, a micromechanical structure, a first dielectric layer 11, an upper substrate 12, a circuit device, and a conductive via 30 a. Wherein the substrate comprises a lower supporting layer 10a, an upper device layer 10b and an insulating layer 10c between the supporting layer 10a and the device layer 10b, the micromechanical structure being comprised in the device layer 10b and comprising a

fixed part

21, 22 and a movable part. The first dielectric layer 11 is at least located on the upper surface of the fixed portion of the micromechanical structure, and in this embodiment, the first dielectric layer 11 is also located on the other portion 23 of the device layer 10 b. The upper substrate 12 is bonded to the first dielectric layer 11 by a bonding technique, and the upper substrate 12 and the substrate form a sealed cavity for accommodating a movable portion of the micromechanical structure. The conductive vias 30a are located in the upper substrate for electrically connecting the micromechanical structure to the outside of the cavity. The circuit devices are located in the upper substrate 12. In this embodiment, the substrate is an SOI (silicon-on-insulator) substrate, the supporting layer 10a and the device layer 10b are made of a semiconductor silicon material, and the insulating layer 10c is made of silicon dioxide. The first dielectric layer 11 is silicon oxide, the upper substrate 12 is a silicon substrate, and the upper substrate 12 and the first dielectric layer 11 are bonded in a silicon-silicon bonding manner. Wherein, the thickness range of the upper substrate 12 is 10-15 um. The thickness of the device layer 10b ranges from 5um to 15um, and the doping resistivity of the device layer 10b ranges from 1 ohm-cm to 0.01 ohm-cm.

The movable part of the micro-mechanical structure comprises at least two separated suspension structures, a first dielectric layer is not arranged between the upper surface of the movable part of the micro-mechanical structure and the upper substrate, and an insulating layer is not arranged between the lower surface of the movable part of the micro-mechanical structure and the supporting layer. In this embodiment, the movable part of the micromechanical structure comprises three separate suspended structures, 20a, 20b, 20c respectively. The fixed part of the micromechanical structure is also partially suspended, in particular an edge portion of the fixed part of the micromechanical structure is suspended.

The

fixed part

21, 22 of the micromechanical structure is connected to at least one suspended structure of the movable part of the micromechanical structure. In the present embodiment, the fixed part 21 of the micromechanical structure is connected to the

movable parts

20a and 20c, and the fixed part 22 of the micromechanical structure is connected to the movable part 20 b. The

movable parts

20a, 20b, 20c of the micromechanical structure are located between the fixed

parts

21 and 22 of the micromechanical structure. The fixed part 21 of the micromechanical structure is spaced apart from the other part 23 of the device layer 10 b. It should be noted that the connection between the fixed part and the movable part of the micromechanical structure is not limited to the manner disclosed in the present invention, and those skilled in the art can connect the micromechanical structure according to the actual process and device requirements, and the connection is not limited herein.

The conductive via 30a includes a first contact hole in the upper substrate 12 and a first conductive material filling the first contact hole and on a portion of the upper surface of the upper substrate. In this embodiment, the conductive path 30a extends to an upper surface of the fixed portion of the micromechanical structure to electrically connect the micromechanical structure to outside the cavity. The side wall of the first contact hole and the upper surface of the upper substrate further include a second dielectric layer 13, and the second dielectric layer in the first contact hole is used for isolating the conductive channel from other device structures or conductive structures in the upper substrate 12. The first conductive material is highly doped polysilicon or conductive metal.

Wherein the circuit device comprises a well region 31 of a first doping type in the upper substrate; a gate conductor 30b on the second dielectric layer 13; and a source region 32 of the second doping type and a drain region 32 of the second doping type located in the well region 31. The integrated structure further comprises a third dielectric layer 15 on the conductive via 30a, the second dielectric layer 13 and the gate conductor 30 b; the second contact holes are positioned in the third dielectric layer 15 and respectively partially expose the conductive channel 30a, the gate conductor 30b and the source drain region 32; and a second conductive material (not shown) in the second contact hole.

The first doping type is one of an N type or a P type, and the second doping type is the other of the N type or the P type.

Fig. 2A-2H are partial, fragmentary, cross-sectional views of a method of fabricating an integrated structure of a MEMS device and a circuit device, in accordance with an embodiment of the present invention.

As shown in fig. 2A, a substrate is provided, and in this embodiment, the substrate sheet is an SOI substrate. The SOI substrate includes a lower support layer 10a, an upper device layer 10b, and an insulating layer 10c between the support layer 10a and the device layer 10 b. The supporting layer 10a and the device layer 10b are made of semiconductor silicon material, the insulating layer 10c is made of silicon dioxide, the doping resistivity of the device layer 10b is preferably 1 ohm-0.01 ohm-cm, and the thickness of the device layer 10b is preferably 5-15 um.

As shown in fig. 2B, a first dielectric layer 11 is grown on the SOI substrate, and then a mask layer is formed on the first dielectric layer 11. The thickness of the first dielectric layer is preferably 1um, and the thickness of the mask layer 12 is preferably 0.25 um. Then, the mask layer is patterned, and a conventional photolithography and etching process is used to obtain a patterned mask layer 12, where the patterned mask layer 12 at least has a window 1201 forming a movable portion of a subsequent micro-mechanical structure. In this embodiment, the mask layer 12 further comprises a window 1202 for subsequently forming a trench separating the fixed portion of the micromechanical structure from other portions of the device layer. The etching process of this step is preferably a wet etching process. The first dielectric layer 11 is preferably an oxide layer, preferably silicon oxide.

As shown in fig. 2C, a patterned photoresist (not shown in the figure) is formed at least in the window 1201, and the first dielectric layer 11 and the device layer 10b are etched to the upper surface of the insulating layer 10C using the patterned photoresist as a mask layer, so as to form a plurality of trenches in the device layer 10 b. The etching process for etching the device layer 10b in this step is a deep silicon etching process, which is a dry etching process, and can form a nearly vertical sidewall. The process for etching the first dielectric layer 11 in this step is a wet etching process.

As shown in fig. 2D, the first dielectric layer 11 and the insulating layer 10c are etched with the patterned mask layer 12 as a protective layer to form a micromechanical structure including

movable portions

20a, 20b, and 20c and fixed

portions

21 and 22. Wherein, the first dielectric layer 11 and the insulating layer 10c are etched at least until the first dielectric layer 11 on the upper surface of the movable part of the micromechanical structure and the insulating layer 10c on the lower surface thereof are completely removed. In this embodiment, the etching is performed using a Buffered Oxide Etchant (BOE) or VHF (vapor HF acid), wherein the gaseous hydrofluoric acid, VHF, does not cause the structure to stick to the support layer after etching. Finally, patterned masking layer 12 is removed.

As shown in fig. 2E, an upper substrate 12 is provided, and the upper substrate 12 is bonded to the first dielectric layer 11 to form a closed cavity with the substrate, so as to accommodate the movable portion of the micromechanical structure. In this embodiment, the upper substrate 12 is preferably a silicon material, and the upper substrate 12 can be bonded to the first dielectric layer 11 by a silicon-silicon fusion bonding technique, wherein the bonding temperature is about 1100-. Because of silicon-silicon bonding, the thermal mismatch ratio of the material is small, so that the stress ratio of a bonding interface is small, and the bonding is very firm. In addition, by adjusting the environment of the bonding process, the type and pressure of the ambient gas in the chamber can be adjusted accordingly, so that the chamber contains fluid with a certain pressure to provide damping required by the operation of the device. During operation, a part or parts of the micromechanical structure may perform a relative movement within the cavity.

As shown in fig. 2F, the upper substrate 12 is thinned to a desired thickness for subsequent processing. The desired thickness is preferably 10-15 um. This thinning is typically accomplished by a CMP (Chemical Mechanical Polishing) process, which results in a very smooth surface after thinning, and thus allows the fabrication of circuit devices on this surface.

As shown in fig. 2G, a well region 31 is formed in the upper substrate 12, the well region 31 is formed by an ion implantation process, and then impurities are diffused into the upper substrate by high temperature diffusion. The well region 31 is a well region of a first doping type. And then, forming a first contact hole 14 in the upper substrate 12 by adopting an etching process, wherein the first contact hole 14 exposes the upper surface of the first dielectric layer 11. Since the etching rate of the first dielectric layer 11 is very low, the etching process can be self-stopped. The etching process of this step may be a dry etching process. In the present embodiment, the first contact hole is formed after the step of forming the well region 31. Of course, in other embodiments, the first contact hole may also be formed before the step of forming the well region 31, and is not limited herein.

As shown in fig. 2H, a second dielectric layer 13 is formed on the inner surface of the first contact hole 14 and the upper surface of the upper substrate 12. The second dielectric layer 13 also covers the upper surface of the well region 31. In this embodiment, the second dielectric layer 13 is formed by a thermal oxidation growth or deposition process.

As shown in fig. 2I, the first dielectric layer 11 at the bottom of the first contact hole is removed, and a first conductive material is deposited in the first contact hole and on the upper surface of the second dielectric layer 13 on the upper substrate 12. And the first conductive material on the upper surface of the second dielectric layer on the upper substrate is etched to form a conductive via 30a and a gate conductor 30 b. The conductive channel is used to electrically connect the micro-mechanical structure to the outside of the cavity, the gate conductor is located above the well region 31, the second dielectric layer 13 below the gate conductor is a gate dielectric layer of the circuit device, and the second dielectric layer in the first contact hole is also used to isolate the conductive channel from other device structures or conductive structures in the upper substrate 12. In this embodiment, the first conductive material may be selected to be highly doped polysilicon or a conductive metal material.

As shown in fig. 2J, a source/drain region 32 of the second doping type is formed in the well region 31, and the source/drain region 32 is formed by a self-aligned ion implantation process. In this embodiment, the first doping type is one of an N type or a P type, and the second doping type is the other of the N type or the P type.

As shown in fig. 1, a third dielectric layer 15 is formed on the conductive channel 30a, the gate conductor 30b and the second dielectric layer 13, and second contact holes are formed in the third dielectric layer 15, wherein parts of the second contact holes respectively expose the conductive channel 30a, the gate conductor 30b and the source/drain region 32; finally, a second conductive material (not shown) is deposited in the second contact hole to lead out the microstructure and the electrode of the circuit device.

According to the method for manufacturing the MEMS device, a substrate comprising a device layer, an insulating layer and a supporting layer is provided, and the device layer is etched to form a micro-mechanical structure; then bonding an upper substrate to the substrate by bonding to form a sealed cavity for accommodating the movable part of the micromechanical structure; finally, a circuit device is formed in the upper substrate and a conductive channel is formed to electrically connect the micromechanical structure to the outside of the cavity. The cavity formed by bonding has low tensile stress, the environmental pressure in the cavity can be adjusted, the sealing performance of the cavity cannot be degraded in the subsequent process, and the performance of a micro-mechanical structure in the cavity cannot be influenced. In addition, the MEMS device and the circuit device are integrated in a single chip, so that the circuit device and the MEMS device with high performance are manufactured on the same substrate, the integration level is improved, and the process complexity and the manufacturing cost are reduced.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing an integrated structure of a MEMS device and a circuit device comprises the following steps:

providing a substrate, wherein the substrate comprises a lower supporting layer, an upper device layer and an insulating layer positioned between the supporting layer and the device layer;

forming a micromechanical structure in the device layer, the micromechanical structure comprising a fixed portion and a movable portion;

providing an upper substrate, forming the upper substrate on the device layer by a bonding technology to form a sealed cavity, wherein the cavity is used for accommodating a movable part of the micromechanical structure; and

a circuit device is formed in the upper substrate.

2. The method of claim 1, further comprising forming conductive vias in the upper substrate connected to the micromechanical structure to electrically connect the micromechanical structure outside of the cavity.

3. The method of claim 2, wherein forming the micromechanical structure comprises:

forming a first dielectric layer on the substrate;

forming patterned photoresist, and etching the first dielectric layer and the device layer to the top of the insulating layer by taking the patterned photoresist as a mask so as to form a plurality of grooves in the device layer; and

and removing part of the first dielectric layer and the insulating layer to form the micromechanical structure.

4. The method of claim 3, wherein prior to forming the patterned photoresist, the method further comprises forming a patterned masking layer on the first dielectric layer, the patterned masking layer having at least a first window forming a movable portion of the micromechanical structure, the patterned photoresist being located on at least the first dielectric layer exposed by the first window.

5. The method of claim 4, wherein removing portions of the first dielectric layer and the insulating layer comprises: and removing the first dielectric layer and the insulating layer by using the patterned mask layer as a protective layer and adopting an etching method at least until the first dielectric layer on the upper surface of the movable part of the micromechanical structure and the insulating layer on the lower surface of the movable part of the micromechanical structure are completely removed.

6. The method of claim 5, further comprising removing the patterned masking layer.

7. The method of claim 3, wherein forming the conductive via comprises:

forming a first contact hole exposing the first dielectric layer in the upper substrate;

forming a second dielectric layer on the inner surface of the first contact hole and the upper surface of the upper substrate;

removing the first dielectric layer at the bottom of the first contact hole; and

and depositing a first conductive material in the first contact hole with the side wall covered with the second dielectric layer and part of the upper surface of the upper substrate to form the conductive channel.

8. The method of claim 7, wherein forming the circuit device comprises:

forming a well region of a first doping type in the upper substrate;

forming a gate conductor on the second dielectric layer; and

and forming a drain region of the second doping type and a source region of the second doping type in the well region by a self-aligned ion implantation process.

9. The method of claim 8 wherein the well region is formed prior to forming the second dielectric layer.

10. The method of claim 8, wherein the second dielectric layer serves as a gate dielectric layer of the circuit device.

11. The method of claim 8, wherein the first conductive material and the gate conductor are formed in a simultaneous process.

12. The method of claim 8, wherein forming the first conductive material and forming the gate conductor comprises:

depositing a conductive layer in the first contact hole and on the upper surface of the upper substrate; and

and selectively etching part of the conductive layer on the upper surface of the upper substrate to form the first conductive material and a gate conductor above the well region.

13. The method of claim 8, wherein the method further comprises:

forming a third dielectric layer on the conductive channel, the second dielectric layer and the gate conductor;

forming second contact holes respectively exposing parts of the conductive channel, the gate conductor, the drain region and the source region in the third dielectric layer; and

depositing a second conductive material in the second contact hole.

14. The method of claim 3, wherein the upper substrate is a silicon substrate and the first dielectric layer is silicon oxide.

15. The method of claim 14, wherein the upper substrate is bonded to the first dielectric layer upper surface by a silicon melt bonding technique.

16. The method of claim 2, further comprising thinning the upper substrate using a chemical mechanical polishing process prior to forming the conductive via.

17. The method of claim 16, wherein the upper substrate is thinned to 10-15 um.

18. The method of claim 4, wherein the patterned mask layer is a silicon nitride layer.

19. The method of claim 3, wherein the device layer is etched using a deep silicon etch process.

20. The method of claim 5, wherein the first dielectric layer and the insulating layer are etched with a hydrofluoric acid or buffered oxide etchant in a gaseous state.

21. The method of claim 7, wherein the first conductive material is highly doped polysilicon or a conductive metal.

22. The method of claim 1, wherein the device layer has a thickness in the range of 5-15 um.

23. The method of claim 1, wherein the substrate is an SOI substrate.

24. An integrated structure of a MEMS device and a circuit device, comprising:

a substrate including a lower support layer, an upper device layer, and an insulating layer between the support layer and the device layer, a micromechanical structure included in the device layer, the micromechanical structure including a fixed portion and a movable portion;

a first dielectric layer at least on the upper surface of the fixed part of the micromechanical structure;

the upper substrate is bonded on the first dielectric layer through a bonding technology; and

a circuit device located in the upper substrate,

wherein the upper substrate and the substrate form a sealed cavity for accommodating the movable part of the micromechanical structure.

25. The integrated structure of claim 24, further comprising conductive vias in the upper substrate to electrically connect the micromechanical structure outside the cavity.

26. The integrated structure of claim 24, wherein the movable portion of the micromechanical structure comprises at least two separate suspended structures, wherein a first dielectric layer is not included between an upper surface of the movable portion of the micromechanical structure and the upper substrate, and wherein an insulating layer is not included between a lower surface of the movable portion of the micromechanical structure and the support layer.

27. The integrated structure of claim 24, wherein the fixed portion of the micromechanical structure is coupled to at least one suspended structure of the movable portion of the micromechanical structure.

28. The integrated structure of claim 24, wherein the movable portion of the micromechanical structure is located between the fixed portions of the micromechanical structure.

29. The integrated structure of claim 24, wherein the conductive via comprises a first contact hole in the upper substrate and a first conductive material filling the first contact hole and on at least an upper surface of the upper substrate.

30. The integrated structure of claim 29, further comprising a second dielectric layer on sidewalls of the first contact hole and an upper surface of the upper substrate.

31. The integrated structure of claim 30, wherein the circuit device comprises;

a well region of a first doping type located in the upper substrate;

a gate conductor on the second dielectric layer; and

and the source region of the second doping type and the drain region of the second doping type are positioned in the well region.

32. The integrated structure of claim 31, further comprising a third dielectric layer on the conductive via, the second dielectric layer, and the gate conductor.

33. The integrated structure of claim 24 wherein the first dielectric layer is silicon oxide.

34. The integrated structure of claim 24, wherein the upper substrate is a silicon substrate.

35. The integrated structure of claim 29, wherein the first conductive material is highly doped polysilicon or a conductive metal.

36. The integrated structure of claim 24, wherein the upper substrate has a thickness in the range of 10-15 um.

37. The integrated structure of claim 24, wherein the device layer has a thickness in the range of 5-15 um.

38. The integrated structure of claim 24, wherein the substrate is an SOI substrate.