CN106115608A - Laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device - Google Patents
Laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device Download PDFInfo
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- CN106115608A CN106115608A CN201610373326.8A CN201610373326A CN106115608A CN 106115608 A CN106115608 A CN 106115608A CN 201610373326 A CN201610373326 A CN 201610373326A CN 106115608 A CN106115608 A CN 106115608A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0006—Interconnects
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00269—Bonding of solid lids or wafers to the substrate
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Abstract
The present invention relates to a kind of laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device, it is characterized in that the technique using Au, In isothermal solidification low-temperature bonding to be combined with organic material Bonded Phase carries out the low temperature envelope packaging technology of radio-frequency devices, the problem solving lead-in wire laterally interconnection, encapsulates simultaneously and also has good mechanical strength and air-tightness.Meanwhile, the metal deposit mode of Au, In isothermal solidification bonding, including the barrier material using Cu to react as Au, In isothermal solidification, and it is used as the protective layer material preventing In top layer oxidized at one layer of thin Au of superficial deposit of In layer.The making of sealing ring is concentrated mainly on encapsulation cover plate, substantially reduces the encapsulation performance impact to substrate chip.It is integrated that the making of sealing ring simultaneously and the making of encapsulation cavity achieve technique.
Description
Technical field
The present invention relates to a kind of low-temperature packaging method, particularly relate to a kind of horizontal interconnection for the application of RF MEMS device
Low-temperature round slice level packaging methods.
Background technology
By miniaturization and highly integrated developing, there is components and parts or the micro-system of New function, thus formed a kind of new
Technical industry field be the main target of MEMS development, and MEMS package plays conclusive work to the realization of this target
With.Encapsulation is to determine commercial MEMS volume, cost and the most key technology of reliability.RF MEMS device is exactly a kind of right
Encapsulation performance requires high MEMS, is one of the key area of MEMS package.RF MEMS device is used to I haven't seen you for ages
To a kind of metal (gold or aluminum), as structural material, therefore the encapsulation to radio-frequency devices must be low temperature bonding；Due to radio frequency
MEMS includes movable cantilever beam or two-end fixed beam structure, is easily subject to steam and some impurity in external environment
Impact and the inefficacy that sticks together, so the encapsulation for RF MEMS chip must be bubble-tight；Owing to MEMS is wanted
Realization is mutual with outer signals, therefore encapsulates and also must be able to realize and extraneous electrical connection.
At present, it is adaptable to MEMS package there is kinds of processes, such as anode linkage technique, the gold-silicon of the materials such as si-glass
The low-temperature bonding technique after bonding technology, plasma or chemical reagent process, glass is melted Deng the eutectic bonding technique of material, silicon silicon
Glass slurry bonding technology, adhering with epoxy resin technique etc..Anode linkage is typically only limited to silicon on glass bonding, and bonding temperature is usual
Being 300～400 DEG C, bias is usually 800～2000V, and the surface smoothness of disk is required the highest, typically by anode linkage simultaneously
Reach nanometer scale.Although anode linkage has the best mechanical strength and air-tightness, but the height added by bonding is electric
Pressure and high temperature, can cause serious impact to even result in the inefficacy of chip on radio-frequency devices.The technological temperature of solder welding is relatively low,
Conventional brazing metal can effectively relax thermal stress owing to having relatively low hardness.But the plasticity that welding procedure is bigger is easily led
Causing weld interface and produce fatigue failure, the pore that reflow soldering process produces also cannot ensure the air-tightness of Vacuum Package.Weld simultaneously
The organic substance that material adds can be discharged in package cavity body during welding, and air-tightness cannot ensure.
Surface active low-temperature bonding is to utilize chemical method to make silicon face activation processing to be bonded, and then realizes the low of silicon silicon
Temperature bonding.But surface active low-temperature bonding process time length (the most several hours to tens hours), inefficient, annealing temperature
High and be easily formed cavity, process owing to relating to surface, it is difficult to meet containing graphics circuitry and the requirement of wafer bonding.Bonding bonding
Dielectric layer thin film is mainly organic material (epoxy resin), glass paste etc., but organic easy aging and poor heat
Stability can cause the drift of device performance, and the method for printing screen that glass paste is used limits the feature chi of structure
Very little, cause the raising of packaging cost.
The interconnection of MEMS wire generally has two kinds of methods, i.e. longitudinal hole type (TSV technology) and two kinds of type of laterally sunkening cord.
Although the wire interconnection technique of the vertical mode that TSV technology realizes can be greatly improved the density of lead-in wire, but the cost of TSV technology is relatively
Height, does not has the biggest advantage for device less demanding for terminal density, also result in bigger the answering of backing material simultaneously
Power.Laterally the simple in construction of pin interconnection, advantage of lower cost, be highly suitable for the encapsulation of RF MEMS device, but laterally draw
The encapsulating material of line interconnection must be the material of insulating properties.Because above-mentioned defect, the design people, actively studied wound
Newly, to founding a kind of laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device so that it is have more product
Value in industry.
From the point of view of the defect of prior art,
1., in prior art, low temperature bonding is easily by treating that backing material is limited, and such as anode linkage packaging technology, it was bonded
In journey, sodium ion to be had migrates, and can typically be only used to the bonding between si-glass substrate；As surface active low-temperature bonding encapsulates work
Skill, is typically only capable to the Direct Bonding encapsulation realizing between silicon-silicon.
2. in prior art, low temperature bonding technique is easily limited by the flatness of substrate surface, such as anode linkage, Au/Si
Eutectic bonding, the packaging technology such as Si-Si bonding, the flatness of bonding surface usually requires that less than 1um, this considerably increases technique
Difficulty and process costs.
3. in prior art, low temperature bonding is not easy to graphically, such as surface active low temperature bonding technique.In the present invention, key
Zygonema can utilize thin film deposition processes to form Au, In metallic film and organic binder bond material by being lithographically formed pattern mask
Material, bonding line lines are uniform, and bonded interface is not limited by figure.
4., in prior art, organic binder bond bonding packaging technique can realize the horizontal interconnection of low temperature bonding and lead-in wire,
But the intensity of organic material encapsulation and air-tightness all cannot ensure；Although use Metal Packaging time can ensure that encapsulation intensity and
Air-tightness, but the horizontal interconnection of lead-in wire cannot be realized, it is necessary to combine with via process, this thereby necessarily increases encapsulation difficulty and
Packaging cost.
Summary of the invention
For solving above-mentioned technical problem, it is an object of the invention to provide a kind of for the application of RF MEMS device laterally mutually
Even low-temperature round slice level packaging methods.
The laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device of the present invention, it includes cap
Plate makes, package substrate makes, encapsulation cover plate is bonded, wherein with package substrate alignment:
Described encapsulation cover plate makes, and comprises the following steps,
Step a1, selects suitable material as cap material；
Step a2, makes bonding line pattern mask by lithography after cleaning；
Step a3, generates adhesion layer, barrier layer, metal level, In layer respectively；
Step a4, makes encapsulation cavity body structure；
Step a5, generates sealing ring, and deposits organic binder material thereon, complete the making of encapsulation cover plate；
Described package substrate makes, and comprises the following steps,
Step b1, carries out necessary cleaning to underlay substrate；
Step b2, carries out being bonded alignment mark and scribing labelling to the bottom of underlay substrate；
Step b3, the upper surface at underlay substrate generates seal ring structure figure, adhesion layer, barrier layer, metal level；
Step b4, separates bonding line metal layer image；
Step b5, picks out position deposition organic binders knot material at sealing ring lead-in wire, completes the making of package substrate substrate；
Described encapsulation cover plate is bonded with package substrate alignment, comprises the following steps,
Step c1, is directed at encapsulation cover plate with package substrate and grips；
Step c2, sends in bonder and is bonded；
Step c3, is cooled to room temperature, it is achieved low-temperature bonding.
Further, the above-mentioned laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device, wherein,
Suitable material described in step a1 is silicon chip, or glass or GaN.
Further, the above-mentioned laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device, its
In, described in step a3
Generation adhesion layer is, thermal evaporation or the Ti of sputtering 20 to 50nm, as adhesion layer；
Generation barrier layer is, the Cu of sputtering 50 to 100nm, as the barrier layer of reaction；
Generation metal level is, sputters or electroplate Au layer material, constitutes metal level；
Generating In layer is, sputtering or thermal evaporation or plating In layer material, constitutes In layer.
Further, the above-mentioned laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device, its
In, the In layer surface described in step a3, deposition has Au layer.
Further, the above-mentioned laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device, its
In, in step a4, by wet etching, or dry etching, or the laser sintered cavity body structure making encapsulation.
Further, the above-mentioned laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device, its
In, in described step b2, by photoetching the degree of depth that etches 2 to 5um, as bonding alignment mark and scribing labelling.
Further, the above-mentioned laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device, its
In, in described step b3, the upper surface at underlay substrate carries out photoetching, makes seal ring structure figure, by thermal evaporation or
The Ti of sputtering 20 to 50nm is as adhesion layer, by sputtering the Cu of 50 to 100nm, as the barrier layer of reaction, by sputtering or
It is plating Au, constitutes metal level.
Further, the above-mentioned laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device, its
In, in described step c2, it is warming up to 100 DEG C to 50 DEG C, pressurize 1 to 3min, extracts fixture out, is rapidly heated 160 DEG C to 210
DEG C, apply pressure 1000mbar to 2500mbar, be bonded dwell time 20min to 30min, remove pressure or add little pressure,
Realizing pressure is 100mbr to 500mbr.
Further, the above-mentioned laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device, its
In, the described dwell time is 2min.
Yet further, the above-mentioned laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device, its
In, described organic binder material includes one or more combinations in polyimides, epoxy resin, BCB.
By such scheme, the present invention at least has the advantage that
1, the performance of gold In material is high, In fusing point low (156.6 DEG C), and hardness is low, and plasticity is strong, and atomic radius is big, very
It is applicable to low-temperature bonding.The speed of gold In isothermal solidification reaction is fast, and bonded interface is difficult to the defect such as bubble and cavity occur, can make
Bonding rate is up to more than 95%.
2, more existing low-temperature bonding technology, the present invention is bonded by Au/In isothermal solidification and organic adhesive bonding
The packaging technology combined, is applicable not only between silicon and silicon, silicon and glass substrate, it is also possible to be suitable between multiple different materials
Being packaged, its application is not limited by baseplate material to be packaged.
3, in the present invention, Au/In isothermal solidification and organic material are fused into liquid during bonding, make bonding have
Liquid flow dynamic characteristic, para-linkage surface smoothness requires relatively low, and in cleaning process, bonding face is made without special surface key
Conjunction increase processes, and is bonded and is easily achieved, low cost, and bonding efficiency is high.
4, bonding line can deposit metal foil by being lithographically formed pattern mask by thermal evaporation or sputtering or electroplating technology
Film, and by being coated with rotation, spraying or silk screen printing depositing organic material, sealing ring lines are uniform, and bonded interface is not limited by figure
System, time saving and energy saving and cost-effective.
5, the making of sealing ring is concentrated mainly on encapsulation cover plate, makes packaging technology that the impact of chip to be minimized.
Metal lead-outs and encapsulant can be all Au material simultaneously, enormously simplify technological process, improve packaging efficiency, reduce into
This.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of description, below with presently preferred embodiments of the present invention and coordinate accompanying drawing describe in detail as after.
Accompanying drawing explanation
Fig. 1 is that the structural representation of encapsulation cover plate (from bottom to up, is followed successively by Si, SiN2、Ti、Cu、Au、In、Au)。
Fig. 2 is the structural representation (from bottom to up, being followed successively by Si, Ti, Cu, Au) of package substrate.
Fig. 3 is the finished product structure schematic diagram of MEMS.
Fig. 4 is seal ring structure schematic diagram.
In figure, the implication of each reference is as follows.
1 encapsulation cover plate 2 package substrate
3 encapsulation cavity 4 metal electrodes
5 organic insulations
Detailed description of the invention
Below in conjunction with the accompanying drawings and embodiment, the detailed description of the invention of the present invention is described in further detail.Hereinafter implement
Example is used for illustrating the present invention, but is not limited to the scope of the present invention.
Such as the laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device of Fig. 1 to 4, it includes encapsulation
Cover plate 1 makes, package substrate 2 makes, encapsulation cover plate 1 is bonded with package substrate 2 alignment, and its unusual part is:
Encapsulation cover plate 1 makes, and comprises the following steps:
First, silicon chip, or the non-silicon material such as glass or GaN are selected, as cap material.After to be cleaned, photoetching
Go out bonding line pattern mask.
Then, by thermal evaporation or the Ti of sputtering 20 to 50nm, as adhesion layer.Immediately, sputter 50 to 100nm's
Cu, as the barrier layer of reaction.Meanwhile, sputter or electroplate Au layer material, constitute metal level.Further, sputtering or thermal evaporation
Or plating In layer material, constitute In layer.On In layer surface, deposition has Au layer.So, the oxidized impact in top layer bonding can be prevented
Effect.
The technique such as afterwards, by wet etching, or dry etching or laser sintered makes the cavity body structure of encapsulation.
Finally, generate sealing ring, and deposit organic binder material thereon, complete the making of encapsulation cover plate 1.
Package substrate 2 makes, and comprises the following steps:
First, the upper and lower surface of underlay substrate to be bonded is carried out necessary cleaning.The bottom of underlay substrate is carried out key
Close alignment mark and scribing labelling.Specifically, can be by photoetching the degree of depth etching 2 to 5um, as bonding alignment mark
With last scribing labelling.During this period, if transparent material, then the making of alignment mark can be omitted.
Afterwards, the upper surface at underlay substrate generates seal ring structure figure, adhesion layer, barrier layer, metal level.Concrete next
Saying, for the ease of preparation, the upper surface at underlay substrate carries out photoetching, makes seal ring structure figure.By thermal evaporation or
The Ti of sputtering 20 to 50nm is as adhesion layer.By sputtering the Cu of 50 to 100nm, as the barrier layer of reaction.By sputtering or
It is plating Au, constitutes metal level.
Subsequently, bonding line metal layer image is separated.Afterwards, position deposition organic binders knot material is picked out at sealing ring lead-in wire
Material, completes the making of package substrate 2 substrate.
Encapsulation cover plate 1 is bonded with package substrate 2 alignment, comprises the following steps:
First, encapsulation cover plate 1 is directed at package substrate 2 and grips.Afterwards, feeding bonder is bonded.
Specifically, bonder is first warming up to 100 DEG C to 50 DEG C, pressurize 1 to 3min (2min is preferred).Then, fixture is extracted out, soon
Speed is warmed up to 160 DEG C to 210 DEG C.During this period, applying pressure 1000mbar to 2500mbar, bonding dwell time 20min is extremely
30min.Finally, remove pressure or add little pressure, it is achieved pressure is 100mbr to 500mbr.After completing above-mentioned steps,
It is cooled to room temperature, it is achieved low-temperature bonding.
From the point of view of the present invention one preferably embodiment, it is contemplated that the facility of preparation, it is suitable for different final technique
Demand, organic binder material of the present invention includes one or more in polyimides, epoxy resin, BCB
In conjunction with.
In order to further illustrate technical scheme, below in conjunction with the accompanying drawings, and using Si sheet as the base up and down of encapsulation
Panel material, and select BCB4000 as this organic binder material, the present invention is embodied as technique, makees the most in detail
Explanation.
This embodiment selects Si sheet as the cover plate encapsulated and backing material.First cover plate and backing material are carried out
Clean, remove surface organic contamination and metal ion.
First, making the encapsulation cavity 3 of encapsulation cover plate 1, this example selects KOH solution warming therapy etching process system
Make.First on encapsulation cover plate 1 the SiO2 material of PECVD or hot oxygen deposition 50-100nm as buffer layer material (Si3N4 and Si
Stress match poor), then utilize the Si3N4 mask graph as corrosion of LPCVD deposition 100-300nm, sputtering is heavy
The Ti of long-pending 50nm is as adhesive layer material, and deposition 50-100nmCu material is as the barrier material of isothermal solidification, sputtering sedimentation
The Au of 100-200nm is as the seed layer materials of plating.
Then, utilize the mask graph that photoetching making is electroplated, electroplate Au layer and the In layer of 10um of 1um, and at In layer
The Au layer of surface deposition 50nm is to prevent In surface oxidized.Removing the seed layer materials beyond sealing ring, photoetching also uses RIE work
Skill etches corrosion window, is gone out encapsulation cavity 3 structure of encapsulation cover plate 1 by KOH solution wet etching, draws at sealing ring electrode
Line position one layer of 12umBCB4000 material of deposition, completes the making of the sealing ring of encapsulation cover plate 1.
Afterwards, underlay substrate is carried out back side photoetching, alignment mark when etching bonding and scribing labelling.Sputtering sedimentation
The Ti of 50nm is as adhesive layer material, and the Cu material of deposition 50-100nm is as the barrier material of isothermal solidification, sputtering sedimentation
The Au of 100-200nm is as the seed layer materials of plating, the Au layer material of electroplating deposition 2um.Further, in metal electrode 4 region
The BCB4000 material of deposition 2um, completes the making of the sealing ring of package substrate 2 substrate.
As shown in Figure 1, being produced as follows of encapsulation cover plate 1:
First, select suitable silicon chip, and use dense H2SO4With H2O2Cleaning silicon chip.Use PECVD or hot oxygen deposition 50-
The SiO of 100nm2Material is as buffer layer material.Utilize LPCVD technique, deposit Si3N4Thin film, as etching mask.Sputtering is heavy
The Ti of long-pending 50nm, as adhesive layer material.Meanwhile, the Cu of deposition 100nm is as the barrier material reacted and seed layer materials.
The Au layer material of electroplating deposition 1um and the In layer material of 10um.Meanwhile, the Au layer material of magnetron sputtering deposition 50nm, to prevent
In layer surface is oxidized.Afterwards, the seed layer materials beyond sealing ring is removed.Then, photoetching etch wet method by RIE technique
Corrosion window.Finally, at the metal electrode 4 organic bonding material of area deposition BCB.
As in figure 2 it is shown, being produced as follows of underlay substrate used:
First, select suitable backing material, and depollution is removed in cleaning.Afterwards, back side photoetching, and etch key with RIE
The alignment mark (if non-transparent substrate material then can omit this step) closed.Meanwhile, the Ti of sputtering sedimentation 50nm is as adhesion layer material
Material, the Cu of deposition 100nm is as the barrier material reacted and seed layer materials, and the Au layer material of electroplating deposition 2um is as electricity
Pole and bonded layer material.Afterwards, the seed layer materials beyond sealing ring is removed, at the metal electrode 4 organic bonding of area deposition BCB
Material.
As it is shown on figure 3, for substrate bonding technology, upper and lower base plate is carried out bonding alignment and fixes.Then, send into
Vacuum bonding is carried out in bonder.Further, bonding temperature uses staged, is warming up to 100 DEG C, pressurize 2min, extracts out fixing
Fixture, is rapidly heated to 250 DEG C, and applies pressure 2000mbar, is bonded dwell time 30min, then reduces pressure extremely
500mbar.Finally, naturally cool to room temperature and take sheet, it is achieved cover plate and the low temperature bonding of backing material.
Finally, the seal ring structure of this encapsulation scheme is distributed as shown in Figure 4, respectively constitutes encapsulation cover plate 1, package substrate
2, encapsulation cavity 3.Using organic insulation 5 to seal around metal electrode 4, other region uses gold In isothermal solidification
Bonding seals.This encapsulation scheme can realize the low temperature bonding technique of RF MEMS device, can realize again the horizontal stroke of lead-in wire
To interconnection, owing to this minor metal is main encapsulating material, encapsulation also has good thermal conduction characteristic and excellent mechanical strength.
It is to say, in the present invention, the packaging technology that Au/In isothermal solidification bonding and organic material Bonded Phase combine, no
It is only applicable between silicon with silicon, silicon and glass be bonded, it is also possible to be suitable to carry out between multiple different materials bonding packaging, its application
Do not limited by backing material.Meanwhile, Au/In isothermal solidification and organic material become liquid at the process melt of bonding, make bonding
Having liquid flow dynamic characteristic, require relatively low to surface smoothness and be easily achieved, low cost, bonding efficiency is high.Bonding line is permissible
By being lithographically formed pattern mask, thin film deposition processes is utilized to form Au, In metallic film and organic binder material, bonding line
Lines are uniform, and bonded interface is not limited by figure.
By above-mentioned character express and combine accompanying drawing it can be seen that use after the present invention, gather around and have the following advantages:
1, the performance of gold In material is high, In fusing point low (156.6 DEG C), and hardness is low, and plasticity is strong, and atomic radius is big, very
It is applicable to low-temperature bonding.The speed of gold In isothermal solidification reaction is fast, and bonded interface is difficult to the defect such as bubble and cavity occur, can make
Bonding rate is up to more than 95%.
2, more existing low-temperature bonding technology, the present invention is bonded by Au/In isothermal solidification and organic adhesive bonding
The packaging technology combined, is applicable not only between silicon and silicon, silicon and glass substrate, it is also possible to be suitable between multiple different materials
Being packaged, its application is not limited by baseplate material to be packaged.
3, in the present invention, Au/In isothermal solidification and organic material are fused into liquid during bonding, make bonding have
Liquid flow dynamic characteristic, para-linkage surface smoothness requires relatively low, and in cleaning process, bonding face is made without special surface key
Conjunction increase processes, and is bonded and is easily achieved, low cost, and bonding efficiency is high.
4, bonding line can deposit metal foil by being lithographically formed pattern mask by thermal evaporation or sputtering or electroplating technology
Film, and by being coated with rotation, spraying or silk screen printing depositing organic material, sealing ring lines are uniform, and bonded interface is not limited by figure
System, time saving and energy saving and cost-effective.
5, the making of sealing ring is concentrated mainly on encapsulation cover plate, makes packaging technology that the impact of chip to be minimized.
Metal lead-outs and encapsulant can be all Au material simultaneously, enormously simplify technological process, improve packaging efficiency, reduce into
This.
The above is only the preferred embodiment of the present invention, is not limited to the present invention, it is noted that for this skill
For the those of ordinary skill in art field, on the premise of without departing from the technology of the present invention principle, it is also possible to make some improvement and
Modification, these improve and modification also should be regarded as protection scope of the present invention.
Claims (10)
1., for the laterally interconnection low-temperature round slice level packaging methods of RF MEMS device application, it includes that encapsulation cover plate makes, seals
Make at the bottom of fitted lining, encapsulation cover plate is bonded with package substrate alignment, it is characterised in that:
Described encapsulation cover plate makes, and comprises the following steps,
Step a1, selects suitable material as cap material；
Step a2, makes bonding line pattern mask by lithography after cleaning；
Step a3, generates adhesion layer, barrier layer, metal level, In layer respectively；
Step a4, makes encapsulation cavity body structure；
Step a5, generates sealing ring, and deposits organic binder material thereon, complete the making of encapsulation cover plate；
Described package substrate makes, and comprises the following steps,
Step b1, carries out necessary cleaning to underlay substrate；
Step b2, carries out being bonded alignment mark and scribing labelling to the bottom of underlay substrate；
Step b3, the upper surface at underlay substrate generates seal ring structure figure, adhesion layer, barrier layer, metal level；
Step b4, separates bonding line metal layer image；
Step b5, picks out position deposition organic binders knot material at sealing ring lead-in wire, completes the making of package substrate substrate；
Described encapsulation cover plate is bonded with package substrate alignment, comprises the following steps,
Step c1, is directed at encapsulation cover plate with package substrate and grips；
Step c2, sends in bonder and is bonded；
Step c3, is cooled to room temperature, it is achieved low-temperature bonding.
Laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device the most according to claim 1, its
It is characterised by: the suitable material described in step a1 is silicon chip, or glass or GaN.
Laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device the most according to claim 1, its
It is characterised by: described in step a3
Generation adhesion layer is, thermal evaporation or the Ti of sputtering 20 to 50nm, as adhesion layer；
Generation barrier layer is, the Cu of sputtering 50 to 100nm, as the barrier layer of reaction；
Generation metal level is, sputters or electroplate Au layer material, constitutes metal level；
Generating In layer is, sputtering or thermal evaporation or plating In layer material, constitutes In layer.
Laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device the most according to claim 1, its
Being characterised by: the In layer surface described in step a3, deposition has Au layer.
Laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device the most according to claim 1, its
It is characterised by: in step a4, by wet etching, or dry etching, or the laser sintered cavity body structure making encapsulation.
Laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device the most according to claim 1, its
It is characterised by: in described step b2, by photoetching the degree of depth that etches 2 to 5um, as bonding alignment mark and scribing mark
Note.
Laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device the most according to claim 1, its
Being characterised by: in described step b3, the upper surface at underlay substrate carries out photoetching, makes seal ring structure figure, is steamed by heat
Send out or the Ti of sputtering 20 to 50nm is as adhesion layer, by sputtering the Cu of 50 to 100nm, as the barrier layer of reaction, pass through
Sputtering or plating Au, constitute metal level.
Laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device the most according to claim 1, its
It is characterised by: in described step c2, is warming up to 100 DEG C to 50 DEG C that pressurize 1 to 3min extracts fixture out, is rapidly heated 160 DEG C
To 210 DEG C, apply pressure 1000mbar to 2500mbar, be bonded dwell time 20min to 30min, remove pressure or add little
Pressure, it is achieved pressure is 100mbr to 500mbr.
Laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device the most according to claim 8, its
It is characterised by: the described dwell time is 2min.
Laterally interconnection low-temperature round slice level packaging methods for the application of RF MEMS device the most according to claim 1, its
It is characterised by: described organic binder material includes one or more combinations in polyimides, epoxy resin, BCB.
Priority Applications (1)
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106829849A (en) * | 2017-03-29 | 2017-06-13 | 苏州希美微纳系统有限公司 | RF mems switches encapsulating structure and its method for packing based on photosensitive BCB bondings |
| CN107814351A (en) * | 2017-11-03 | 2018-03-20 | 苏州希美微纳系统有限公司 | Suitable for the bonding packaging construction and its method of RF MEMS |
| CN109243974A (en) * | 2018-08-02 | 2019-01-18 | 中国电子科技集团公司第五十五研究所 | A method of reducing wafer bonding deviation of the alignment |
| CN109835870A (en) * | 2019-02-19 | 2019-06-04 | 厦门大学 | A kind of integrated encapsulation method and structure of MEMS device and ASIC processing circuit IC |
| CN111146094A (en) * | 2019-12-04 | 2020-05-12 | 中国电子科技集团公司第十三研究所 | Gallium nitride power module packaging method, pressurizing device and pre-curing molding rubber ring |
| CN113745326A (en) * | 2021-10-11 | 2021-12-03 | 清华大学 | Gallium nitride pressure sensor and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1821052A (en) * | 2006-01-13 | 2006-08-23 | 中国科学院上海微系统与信息技术研究所 | Low temperature airtightness packaging method for wafer level micro machinery device and photoelectric device |
| US20060208326A1 (en) * | 2005-03-18 | 2006-09-21 | Nasiri Steven S | Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom |
| CN101295753A (en) * | 2007-04-24 | 2008-10-29 | 中国科学院上海微系统与信息技术研究所 | Low temperature Au-In-Au bonding method for III-V family compounds |
| CN101746706A (en) * | 2009-10-16 | 2010-06-23 | 华中科技大学 | Micro-electromechanical system (MEMS) wafer-level vacuum packaging transverse interconnection structure and manufacture method thereof |
| CN102569031A (en) * | 2011-07-07 | 2012-07-11 | 杨继远 | Method for carrying out bonding epitaxial wafer and silicon wafer by indium (In) |
-
2016
- 2016-05-31 CN CN201610373326.8A patent/CN106115608B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060208326A1 (en) * | 2005-03-18 | 2006-09-21 | Nasiri Steven S | Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom |
| CN1821052A (en) * | 2006-01-13 | 2006-08-23 | 中国科学院上海微系统与信息技术研究所 | Low temperature airtightness packaging method for wafer level micro machinery device and photoelectric device |
| CN101295753A (en) * | 2007-04-24 | 2008-10-29 | 中国科学院上海微系统与信息技术研究所 | Low temperature Au-In-Au bonding method for III-V family compounds |
| CN101746706A (en) * | 2009-10-16 | 2010-06-23 | 华中科技大学 | Micro-electromechanical system (MEMS) wafer-level vacuum packaging transverse interconnection structure and manufacture method thereof |
| CN102569031A (en) * | 2011-07-07 | 2012-07-11 | 杨继远 | Method for carrying out bonding epitaxial wafer and silicon wafer by indium (In) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106829849A (en) * | 2017-03-29 | 2017-06-13 | 苏州希美微纳系统有限公司 | RF mems switches encapsulating structure and its method for packing based on photosensitive BCB bondings |
| CN107814351A (en) * | 2017-11-03 | 2018-03-20 | 苏州希美微纳系统有限公司 | Suitable for the bonding packaging construction and its method of RF MEMS |
| CN109243974A (en) * | 2018-08-02 | 2019-01-18 | 中国电子科技集团公司第五十五研究所 | A method of reducing wafer bonding deviation of the alignment |
| CN109835870A (en) * | 2019-02-19 | 2019-06-04 | 厦门大学 | A kind of integrated encapsulation method and structure of MEMS device and ASIC processing circuit IC |
| CN109835870B (en) * | 2019-02-19 | 2020-12-11 | 厦门大学 | Integrated packaging method and structure of MEMS device and ASIC processing circuit IC |
| CN111146094A (en) * | 2019-12-04 | 2020-05-12 | 中国电子科技集团公司第十三研究所 | Gallium nitride power module packaging method, pressurizing device and pre-curing molding rubber ring |
| CN111146094B (en) * | 2019-12-04 | 2021-08-31 | 中国电子科技集团公司第十三研究所 | Gallium nitride power module packaging method and pressurizing device |
| CN113745326A (en) * | 2021-10-11 | 2021-12-03 | 清华大学 | Gallium nitride pressure sensor and preparation method thereof |
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