CN101630692A - Channel layers and semiconductor devices including the same - Google Patents
Channel layers and semiconductor devices including the same Download PDFInfo
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- CN101630692A CN101630692A CN200910140008A CN200910140008A CN101630692A CN 101630692 A CN101630692 A CN 101630692A CN 200910140008 A CN200910140008 A CN 200910140008A CN 200910140008 A CN200910140008 A CN 200910140008A CN 101630692 A CN101630692 A CN 101630692A
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- 239000004065 semiconductor Substances 0.000 title abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 21
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 8
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 6
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 6
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 5
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 5
- 229910052725 zinc Inorganic materials 0.000 claims description 5
- 239000011701 zinc Substances 0.000 claims description 5
- 230000005684 electric field Effects 0.000 claims description 4
- 230000037230 mobility Effects 0.000 abstract 1
- 230000000052 comparative effect Effects 0.000 description 33
- 239000000758 substrate Substances 0.000 description 21
- 239000012212 insulator Substances 0.000 description 19
- 239000011248 coating agent Substances 0.000 description 13
- 238000000576 coating method Methods 0.000 description 13
- 229910004438 SUB2 Inorganic materials 0.000 description 9
- 101100311330 Schizosaccharomyces pombe (strain 972 / ATCC 24843) uap56 gene Proteins 0.000 description 9
- 101150018444 sub2 gene Proteins 0.000 description 9
- 102100036464 Activated RNA polymerase II transcriptional coactivator p15 Human genes 0.000 description 8
- 101000713904 Homo sapiens Activated RNA polymerase II transcriptional coactivator p15 Proteins 0.000 description 8
- 229910004444 SUB1 Inorganic materials 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000002161 passivation Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Channel layers and semiconductor devices including the channel layers are disclosed. A channel layer may include a multi-layered structure. Layers forming the channel layer may have different carrier mobilities and/or carrier densities. The channel layer may have a double layered structure including a first layer and a second layer which may be formed of different oxides. Characteristics of the transistor may vary according to materials used to form the channel layers and/or thicknesses thereof.
Description
Technical field
One or more embodiment of the present invention relates to a kind of semiconductor device, more particularly, relates to a kind of channel layer and a kind of transistor that comprises this channel layer.
Background technology
Usually, with transistor as switching device or drive unit in the electronic installation.Specifically, thin-film transistor (TFT) can be formed on substrate of glass or the plastic-substrates.As a result, TFT usually is used for the flat panel display equipment such as liquid crystal display and oganic light-emitting display device.
In order to improve transistorized operating characteristic, made the trial of oxide semiconductor layer as transistorized channel layer.Such conventional method is mainly used in the TFT that makes flat panel display equipment.Yet, in the transistor (for example, the conventional oxide transistor) that has as the oxide semiconductor layer of channel layer, be difficult to control threshold voltage.
The conventional oxide transistor is used as channel layer with n type oxide skin(coating).(subthreshold slope, SS), n type oxide skin(coating) need have high carrier concentration and high degree of crystallinity in order to obtain high ON/OFF current ratio and little sub-threshold slope.In order to control threshold voltage, if the carrier concentration of n type oxide skin(coating) reduces, then mobility reduces.Therefore, the ON/OFF current ratio reduces and SS increases, thereby makes transistorized operating characteristic deterioration.In addition, if the carrier concentration of n type oxide skin(coating) increases, then threshold voltage is reduced to negative (-) side, causes making enhancement transistor.
Summary of the invention
One or more embodiment of the present invention comprises a kind of the have mobility of having regulated and the oxide transistor of threshold voltage.
To partly set forth other aspect and/or advantage in the following description, and other aspect and/or advantage will partly become clear by description, maybe can know by implementing the present invention.
In order to realize above-mentioned and/or others and advantage, one or more embodiment of the present invention can comprise a kind of transistor, described transistor comprises: channel layer, comprise lower floor and upper strata, and the mobility on lower floor and upper strata is different and formed by different oxide materials; Source electrode and drain electrode contact the opposite end of channel layer respectively; Grid is used for electric field is applied to channel layer.
The mobility of one deck of more close grid can be higher than another layer further from grid in lower floor and the upper strata.
One deck of more close grid can be determined transistorized mobility in lower floor and the upper strata.
One deck at least in lower floor and the upper strata can be determined transistorized threshold voltage.
If the thickness of one deck of more close grid (ground floor) is in first scope in lower floor and the upper strata, then transistorized threshold voltage can be determined by another layer (second layer) further from grid.If the thickness of ground floor is in second scope greater than first scope, then threshold voltage can be determined by the ground floor and the second layer.If the thickness of ground floor is in the 3rd scope greater than second scope, then threshold voltage can be determined by ground floor.
One deck of more close grid can comprise at least a oxide of selecting in lower floor and the upper strata from the group of being made up of indium zinc oxide (IZO), tin indium oxide (ITO), aluminum zinc oxide (AZO), gallium oxide zinc (GZO).
One deck further from grid in lower floor and the upper strata can comprise the ZnO type oxide.
The thickness of one deck of more close grid can be for approximately in lower floor and the upper strata
To about
The thickness of one deck of more close grid can be for approximately in lower floor and the upper strata
To about
Can be for approximately in lower floor and the upper strata further from the thickness of one deck of grid
To about
Can be identical or greater than the thickness of another layer in lower floor and the upper strata with the thickness of another layer further from the thickness of one deck of grid.
Described transistor can be the thin-film transistor (TFT) of top gate structure or the thin-film transistor (TFT) of bottom grating structure.
In order to realize top and/or others and advantage, one or more embodiment of the present invention can comprise a kind of transistor, described transistor comprises: channel layer, comprise lower floor and upper strata, and the carrier density on lower floor and upper strata is different and formed by different oxide materials; Source electrode and drain electrode contact the opposite end of channel layer respectively; Grid is used for electric field is applied to channel layer.
The carrier density of one deck of more close grid can be higher than another layer further from grid in lower floor and the upper strata.
The mobility on lower floor and upper strata can be different.
The mobility of one deck of more close grid can be higher than another layer further from grid in lower floor and the upper strata.
One deck of more close grid can be determined transistorized mobility in lower floor and the upper strata.
One deck at least in lower floor and the upper strata can be determined transistorized threshold voltage.
If the thickness of one deck of more close grid (ground floor) is in first scope in lower floor and the upper strata, then transistorized threshold voltage can be determined by another layer (second layer) further from grid.If the thickness of ground floor is in second scope greater than first scope, then threshold voltage can be determined by the ground floor and the second layer.If the thickness of ground floor is in the 3rd scope greater than second scope, then threshold voltage can be determined by ground floor.
One deck of more close grid can comprise at least a oxide of selecting in lower floor and the upper strata from the group of being made up of indium zinc oxide (IZO), tin indium oxide (ITO), aluminum zinc oxide (AZO), gallium oxide zinc (GZO).
One deck further from grid in lower floor and the upper strata can comprise the ZnO type oxide.
The thickness of one deck of more close grid can be for approximately in lower floor and the upper strata
To about
The thickness of one deck of more close grid can be for approximately in lower floor and the upper strata
To about
Can be for approximately in lower floor and the upper strata further from the thickness of one deck of grid
To about
Can be identical or greater than the thickness of another layer in lower floor and the upper strata with the thickness of another layer further from the thickness of one deck of grid.
Described transistor can be the TFT of top gate structure or the TFT of bottom grating structure.
Description of drawings
By below in conjunction with the description of accompanying drawing to embodiment, these and/or others and advantage will become obviously and be more readily understood, in the accompanying drawing:
Fig. 1 is the transistorized cutaway view according to illustrated embodiments of the invention;
Fig. 2 is the transistorized cutaway view of another example embodiment according to the present invention;
Fig. 3 is the transistorized grid voltage V that illustrates according to example embodiment and comparative example
g-drain current I
dThe curve chart of characteristic;
Fig. 4 is the linear scale curve chart of Fig. 3;
Fig. 5 is the transistorized grid voltage V that illustrates according to illustrated embodiments of the invention
g-drain current I
dCharacteristic is about the curve chart of the thickness of transistorized indium zinc oxide (IZO) layer;
Fig. 6 is transistorized threshold voltage (V) and the mobility (cm that illustrates according to illustrated embodiments of the invention
2/ Vs) about the curve chart of the thickness of transistorized IZO layer;
Fig. 7 is the transistorized grid voltage V that illustrates according to example embodiment and comparative example
g-drain current I
dThe curve chart of characteristic;
Fig. 8 is the transistorized grid voltage V that illustrates according to illustrated embodiments of the invention
g-drain current I
dCharacteristic is about the curve chart of the thickness of transistorized ITO layer;
Fig. 9 is transistorized threshold voltage (V) and the mobility (cm that illustrates according to illustrated embodiments of the invention
2/ Vs) about the curve chart of the thickness of transistorized ITO layer;
Figure 10 A to Figure 10 D is the cutaway view according to the transistorized method of manufacturing of illustrated embodiments of the invention;
Figure 11 A to Figure 11 D is the cutaway view of the transistorized method of manufacturing of another example embodiment according to the present invention.
Embodiment
Now, with reference to the accompanying drawing that shows some example embodiment various example embodiment are described more fully.
Disclosed herein is the example embodiment that is shown specifically.Yet concrete structure disclosed herein and function detail are only represented for the purpose of describing example embodiment.Yet the present invention can implement with many replacement forms, should not be interpreted as the example embodiment that only limits to set forth here.
Therefore, though example embodiment can have various modifications and interchangeable form, in the mode of the example in the accompanying drawing embodiment is shown, and will be described in detail here.It should be understood, however, that not to be intended to example embodiment is restricted to disclosed concrete form that but opposite, example embodiment is intended to cover all modifications that fall within the scope of the present invention, equivalent and alternative.In the whole description of accompanying drawing, identical label is represented components identical.
Though it should be understood that and to use term here first, second waits and describes various elements that these elements are not limited by these terms should.These terms only are used to distinguish an element and another element.For example, under the situation of the scope that does not break away from example embodiment, first element can be called as second element, and similarly, second element can be called as first element.As used herein, term " and/or " comprise one or more relevant listd arbitrarily and all combinations.
It should be understood that when element or the layer be called as " being formed on " another element or the layer " on " time, it can be formed on directly or indirectly another element or the layer on.That is, for example, can there be intermediary element or layer.On the contrary, when element or the layer be called as " being formed directly into " another element " on " time, do not exist intermediary element or the layer.Should explain in an identical manner other speech of being used to describe the relation between element or the layer (for example, " and ... between " with " and directly exist ... between ", " adjacent " and " direct neighbor " etc.).
Term used herein is only for the purpose of describing specific embodiment, and is not intended to the restriction example embodiment.As used herein, unless context points out clearly that in addition otherwise singulative also is intended to comprise plural form.It should also be understood that, when using term " to comprise " here and/or when " comprising ", show to have described feature, integral body, step, operation, element and/or assembly, do not exist or add one or more other feature, integral body, step, operation, element, assembly and/or their groups but do not get rid of.
In the accompanying drawings, for clarity, exaggerated the thickness in layer and zone.Identical label in the accompanying drawing is represented components identical.
Fig. 1 is the cutaway view according to the transistor T 1 of illustrated embodiments of the invention.Transistor T 1 can be the thin-film transistor (TFT) with bottom grating structure, and wherein, grid G 1 is formed on channel layer C1 below.
With reference to Fig. 1, grid G 1 is formed on the substrate SUB1.Substrate SUB1 can be silicon base, substrate of glass or plastic-substrates.Substrate SUB1 can be transparent or can be opaque.Gate insulator GI1 can be formed on the substrate SUB1, with cover gate G1.Gate insulator GI1 can be silicon oxide layer, silicon nitride layer or other material layer that is fit to.Channel layer C1 can be formed on the gate insulator GI1 and above grid G 1.Channel layer C1 can be greater than the width of grid G 1 along X-direction along the width of X-direction.Channel layer C1 can have the sandwich construction of at least two oxide skin(coating)s that comprise that mobility and/or carrier density are different.For example, channel layer C1 can have double-decker, and double-decker comprises first oxide skin(coating) (ground floor) 10 and second oxide skin(coating) (second layer) 20 that is formed on the ground floor 10.Compare with the second layer 20, ground floor 10 is set to relatively more be close to grid G 1.For this reason, the mobility of ground floor 10 can be greater than the mobility of the second layer 20.The carrier density of ground floor 10 can be greater than the carrier density of the second layer 20.To the mobility and the carrier density of material be described in more detail.The mobility of material and carrier density can be variablees independently.Yet in oxide, carrier density is common and mobility is proportional.That is, the oxide with high carrier density has high mobility.Yet in some cases, the oxide with high carrier density can have low mobility.Simultaneously, carrier density and/or mobility increase along with the oxide skin(coating) that is used as channel layer comprise that the transistorized mobility of described oxide skin(coating) increases.Yet, when the carrier density of the oxide skin(coating) with low mobility is high, comprise that the transistor as this oxide skin(coating) of channel layer can have high mobility.The carrier density of channel material and/or mobility not only influence transistorized mobility, also influence transistorized threshold voltage.For example, along with the carrier density of channel material reduces, transistorized threshold voltage can be to (+) side shifting just.According to example embodiment,, then can easily control transistorized mobility and the threshold voltage that comprises channel layer C1 if make channel layer C1 by piling up carrier density and/or the mobility different ground floor 10 and the second layer 20.To be described this in more detail.
Compare with the second layer 20, ground floor 10 can be set to more close relatively grid G 1, and can increase the mobility of transistor T 1.That is, the transistor of the channel layer that forms with the material that only comprises by the second layer 20 is compared, and comprises that the transistor T 1 of the channel layer C1 that is formed by the ground floor 10 and the second layer 20 can have higher mobility.Because the carrier density of ground floor 10 and/or mobility can be higher than the carrier density and/or the mobility of the second layer 20, the mobility of transistor T 1 can increase.Even ground floor 10 has lower mobility, if ground floor 10 has high carrier density, then the mobility of transistor T 1 also can increase because of ground floor 10.Simultaneously, if the thin thickness of ground floor 10, then the threshold voltage of transistor T 1 can be better than by the second layer 20 controls and be subjected to ground floor 10 controls.For example, if ground floor 10 is enough thin, then can be according to the threshold voltage of the material of the second layer 20, composition, carrier concentration oxide-semiconductor control transistors T1.Because compare with ground floor 10, the second layer 20 can have lower carrier density and/or mobility, so compare with only comprising the transistorized threshold voltage that material by ground floor 10 forms channel layer, comprise that the threshold voltage of the transistor T 1 of the channel layer C1 that is formed by the ground floor 10 and the second layer 20 can move to just (+) side.Therefore, transistor T 1 can be for having high mobility and the enhancement transistor of (+) threshold voltage just.Yet if ground floor 10 thickenings (surpassing predetermined or given critical thickness), ground floor 10 can increase in the influence aspect the threshold voltage of transistor T 1.In this case, the threshold voltage of transistor T 1 can be subjected to the influence of the ground floor 10 and the second layer 20.Along with the influence increase of ground floor 10, the threshold voltage of transistor T 1 can be to negative (-) side shifting.If ground floor 10 is too thick, then the threshold voltage of transistor T 1 can be better than by ground floor 10 controls and be subjected to the second layer 20 controls.
For example, ground floor 10 can be for comprising at least a layer in indium zinc oxide (IZO), tin indium oxide (ITO), aluminum zinc oxide (AZO), the gallium oxide zinc (GZO).The second layer 20 can comprise the ZnO type oxide.For this reason, the second layer 20 can also comprise the III family element such as Ga and In.For example, the second layer 20 can be gallium oxide indium zinc (GIZO) layer.The second layer 20 can be for being doped with such as the IV family element of Sn or other element that is fit to but not the ZnO type oxide layer of III family element.The thickness of ground floor 10 can be for approximately
To about
At length say, approximately
To about
If ground floor 10 is too thin, then ground floor 10 can reduce in the effect aspect the increase of the mobility of transistor T 1.On the other hand, if ground floor 10 is too thick, then the second layer 20 can reduce in the effect aspect the threshold voltage that increases transistor T 1, and this is because be not easy to form raceway groove in the second layer 20.That is, along with the thickness increase of ground floor 10, the threshold voltage of transistor T 1 can be subjected to the influence of the ground floor 10 and the second layer 20.If ground floor 10 is too thick, then the threshold voltage of transistor T 1 can be determined and be can't help the second layer 20 and determine by ground floor 10.Therefore, the threshold voltage of transistor T 1 can be for its purpose Be Controlled easily.If desired with the threshold voltage of transistor T 1 to (+) side shifting just, then can reduce the thickness of ground floor 10, thereby can increase the second layer 20 in the effect that increases aspect the threshold voltage.On the other hand, if desired with the threshold voltage of transistor T 1 to negative (-) side shifting, then ground floor 10 can have enough thickness, thereby can reduce the threshold voltage of transistor T 1 by ground floor 10.The thickness of ground floor 10 can be for approximately
To about
The thickness of ground floor 10 can be for approximately
To about
Thereby can increase the threshold voltage of transistor T 1 by the second layer 20.Yet, be suitable for obtaining the second layer and can change according to the material of the ground floor 10 and the second layer 20 at the thickness of the ground floor 10 of the effect aspect the increase threshold voltage.In addition, described thickness can change according to transistorized size and type.Simultaneously, the thickness of the second layer 20 can be for approximately
To about
Promptly can be more than or equal to the thickness of ground floor 10.
Source electrode S1 and drain electrode D1 can be formed on the gate insulator GI1, thereby contact the opposite side of channel layer C1 respectively.Source electrode S1 and drain electrode D1 all can be single metal layer or many metal levels.Source electrode S1 can be formed by the metal identical with the metal that is used to form grid G 1 with drain electrode D1.Selectively, source electrode S1 can be formed by the material different with the material that is used to form grid G 1 with drain electrode D1.Passivation layer P1 can be formed on the gate insulator GI1, to cover channel layer C1, source electrode S1, drain electrode D1.Passivation layer P1 can be silicon oxide layer or silicon nitride layer.Simultaneously, grid G 1 can have the thickness of about 50nm to about 300nm.Gate insulator GI1 can have the thickness of about 50nm to about 300nm.Gate insulator GI1 can have the thickness of about 50nm to about 300nm.Source electrode S1 can have the thickness of about 10nm to about 200nm.Drain electrode D1 can have the thickness of about 10nm to about 200nm.
Fig. 2 is the cutaway view of the transistor T 2 of another example embodiment according to the present invention.Transistor T 2 can be for having the TFT of top gate structure, and wherein, grid G 2 is formed on channel layer C2 top.
With reference to Fig. 2, channel layer C2 is formed on the substrate SUB2.Channel layer C2 can have such structure, wherein, and the channel layer C1 of the Fig. 1 that overturn.That is, the channel layer C2 of Fig. 2 can have such structure, wherein, and the second layer 20 corresponding with the second layer 20 of Fig. 1 ' and be formed on the substrate SUB2 with the corresponding ground floor 10 ' order of the ground floor 10 of Fig. 1.Source electrode S2 and drain electrode D2 can be formed on the substrate SUB2, to contact the opposite side of channel layer C2 respectively.Gate insulator GI2 can be formed on the substrate SUB2, to cover channel layer C2, source electrode S2, drain electrode D2.Grid G 2 can be formed on the gate insulator GI2.Grid G 2 can be formed on channel layer C2 top.Therefore, with the second layer 20 ' compare, the more close grid G 2 of ground floor 10 ' be set to.Passivation layer P2 can be formed on the gate insulator GI2, with cover gate G2.
Be used to form the substrate SUB2, ground floor 10 of Fig. 2 ', the second layer 20 ', the material with the substrate SUB1 that is used to form Fig. 1, ground floor 10, the second layer 20, source electrode S1, drain electrode D1, gate insulator GI1, grid G 1, passivation layer P1 is identical respectively for the material of source electrode S2, drain electrode D2, gate insulator GI2, grid G 2, passivation layer P2.Similarly, the thickness of the various elements of Fig. 2 can be identical with the thickness of the element of Fig. 1.In addition, the ground floor 10 of Fig. 2 ' with the second layer 20 ' function can be identical with the function of the ground floor 10 of Fig. 1 and the second layer 20.
Fig. 3 is the transistorized grid voltage V that illustrates according to first example embodiment, first comparative example, second comparative example
g-drain current I
dThe curve chart of characteristic.The first curve G1 of Fig. 3 illustrates the grid voltage V of the transistor (hereinafter, being called the first transistor) according to first example embodiment
g-drain current I
dCharacteristic, the first transistor are the transistor with structure of Fig. 1 for example, and wherein, ground floor 10 is the IZO layer, and the second layer 20 is the GIZO layer.For this reason, the IZO layer can have approximately
Thickness, the GIZO layer can have approximately
Thickness.The second curve G2 of Fig. 3 illustrates the transistorized grid voltage V according to first comparative example
g-drain current I
dCharacteristic, in first comparative example's transistor, channel layer is that thickness is about
The GIZO individual layer.The 3rd curve G3 of Fig. 3 illustrates the transistorized grid voltage V according to second comparative example
g-drain current I
dCharacteristic, in second comparative example's transistor, channel layer is that thickness is about
The IZO individual layer.Simultaneously, in Fig. 3, drain voltage can be 1V, can adopt identical drain voltage to obtain the curve of Fig. 5 and Fig. 7.
Based on to the first curve G1 of Fig. 3 and the contrast of the second curve G2, the ON electric current of the first curve G1 is about 10
-3A, this is the ON electric current (about 3 * 10 of the second curve G2
-4A) about three times big.The mobility of the first transistor is about three times big according to first comparative example's transistorized mobility.Shown in transistorized mobility and sub-threshold slope (SS) table 1 below.
Table 1
| Channel layer | Mobility (cm 2/V·s) | Sub-threshold slope (V/dec) |
| IZO/GIZO bilayer (example embodiment) | ??52 | ??0.19 |
| GIZO individual layer (comparative example) | ??19 | ??0.19 |
Fig. 4 is the linear scale curve chart of the first curve G1 to the, the three curve G3 of Fig. 3.The first curve G1 ' of Fig. 4 corresponds respectively to the first curve G1 to the, the three curve G3 of Fig. 3 to the 3rd curve G3 '.Grid voltage at the some place that the tangent line and the X-axis of every the curve of the first curve G1 ' to the 3rd curve G3 ' intersects is transistorized threshold voltage.Make described tangent line at the first curve G1 ' to maximum " Gm " the some place of the 3rd curve G3 ', wherein, " Gm " is [(variation of drain current)/(variation of grid voltage)], that is, and and [(Δ I
d/ Δ V
g)].
With reference to Fig. 4, the transistorized threshold voltage of the first curve G1 ' is about 0.31V, the transistorized threshold voltage of the second curve G2 ' is approximately-and 0.60V.That is, the threshold voltage of the first transistor shown in the first curve G1 ' is similar to the transistorized threshold voltage according to first comparative example shown in the second curve G2 '.Simultaneously, the transistor of the 3rd curve G3 ' (that is, according to second comparative example the transistor as the IZO individual layer of channel layer of comprising) has approximately-low threshold voltage of 8V.As a result, not enhancement transistor but depletion mode transistor according to second comparative example's transistor.As mentioned above, the threshold voltage of the first transistor is to similar according to first comparative example's transistor threshold voltage and have just (+) value, and low relatively and have negative (-) value according to second comparative example's transistorized threshold voltage.Because the first transistor comprises the IZO/GIZO channel layer, transistor according to first comparative example comprises the GIZO channel layer, transistor according to second comparative example comprises the IZO channel layer, so the threshold voltage of the first transistor is not by the IZO layer but is determined by the GIZO layer.
That is, if as in first comparative example, the GIZO individual layer is used as channel layer, and then transistor can not have high mobility.If as in second comparative example, the IZO individual layer is used as channel layer, then threshold voltage is low, causes being difficult to produce enhancement transistor.Yet,, can produce enhancement transistor with high mobility according to example embodiment.For this reason, the IZO layer according to the channel layer (IZO/GIZO) of the first transistor of example embodiment has approximately
Thin thickness.Reduce threshold voltage if desired, the thickness of IZO layer that then increases channel layer (IZO/GIZO) is to increase the IZO layer in the effect aspect the threshold voltage.
Fig. 5 is the transistorized grid voltage V that illustrates according to illustrated embodiments of the invention
g-drain current I
dThe curve chart of characteristic, according to the transistor of illustrated embodiments of the invention comprise the IZO layer as ground floor 10 and GIZO layer as the second layer 20.Solid line among Fig. 5 represents to utilize the GIZO individual layer not have the characteristics of transistor of IZO layer as channel layer.
With reference to Fig. 5, has thickness for about
The transistorized grid voltage V of thin IZO layer
g-drain current I
dCharacteristic and transistorized grid voltage V with GIZO individual layer
g-drain current I
dCharacteristic is similar.If the thickness of IZO layer is about
Then transistorized threshold voltage to comprise that the GIZO individual layer is similar as the transistorized threshold voltage of channel layer, but the ON electric current significantly increases.The increase of transistorized mobility is represented in the increase of ON electric current.In addition, if the thickness of IZO layer is about
Then curve moves to negative (-) side.Here, with comprising thickness be
The transistorized mobility of IZO layer compare, comprise that thickness is
The transistorized mobility of IZO further increase.The transistorized grid voltage V that comprises too thin IZO layer
g-drain current I
dCharacteristic with comprise the grid voltage V of GIZO individual layer as channel layer
g-drain current I
dCharacteristic is similar.The transistorized grid voltage V that comprises too thick IZO layer
g-drain current I
dCharacteristic with according to second comparative example's transistorized grid voltage V
g-drain current I
dCharacteristic is similar, is according to second comparative example's transistor to comprise the transistor of IZO individual layer as channel layer.The thickness of IZO layer can be controlled for its purpose.
Fig. 6 illustrates according to the transistorized threshold voltage of illustrated embodiments of the invention and the mobility curve chart about the thickness of transistorized IZO layer.
With reference to Fig. 6, along with the thickness increase of IZO layer, mobility increases, and threshold voltage reduces.Specifically, the thickness when the IZO layer is about
To about
The time, the variation maximization of mobility.Along with the thickness increase of IZO layer, variations in threshold voltage increases.
Fig. 7 is the transistorized grid voltage V according to second example embodiment, the 3rd comparative example, the 4th comparative example
g-drain current I
dThe curve chart of characteristic.The first curve GG1 of Fig. 7 illustrates the grid voltage V of the transistor (hereinafter, being called transistor seconds) according to second example embodiment
g-drain current I
dCharacteristic, transistor seconds are the transistor with structure of Fig. 1 for example, and wherein, ground floor 10 is the ITO layer, and the second layer 20 is the GIZO layer.For this reason, the ITO layer can have approximately
Thickness.The GIZO layer can have approximately
Thickness.The second curve GG2 of Fig. 7 illustrates the transistorized grid voltage V according to the 3rd comparative example
g-drain current I
dCharacteristic, in the transistor according to the 3rd comparative example, channel layer is that thickness is about
The GIZO individual layer.The 3rd curve GG3 of Fig. 7 illustrates the transistorized grid voltage V according to the 4th comparative example
g-drain current I
dCharacteristic, in the transistor according to the 4th comparative example, channel layer is that thickness is about
The ITO individual layer.According to the 3rd comparative example's transistorized structure and first comparative example's who describes according to reference Fig. 3 transistorized structural similarity.Yet it is different slightly to form two transistorized conditions.
Based on to the first curve GG1 of Fig. 7 and the contrast of the second curve GG2, the ON electric current of the first curve GG1 is about 5 * 10
-5A, this is the ON electric current (about 5 * 10 of the second curve GG2
-6A) about ten times are big.The mobility of the transistor seconds shown in the first curve GG1 be shown in the second curve GG2 according to transistorized about ten times big of the 3rd comparative example.The tangent slope of the first curve GG1 at the firing point place is slightly larger than the tangent slope that the second curve GG2 points out in conducting.That is, the sub-threshold slope of transistor seconds (SS) is less than the transistorized sub-threshold slope (SS) according to the 3rd comparative example.That is, comprise that the conducting speed of transistor seconds of double-deck channel layer is faster than the transistorized conducting speed that comprises the individual layer channel layer according to the 3rd comparative example.Shown in transistorized mobility, SS, the threshold voltage table 2 below.
Table 2
| Channel layer | Mobility (cm 2/V·s) | Sub-threshold slope (SS) (V/dec) | Threshold voltage (V) |
| ITO/GIZO bilayer (example embodiment) | ??104 | ??0.25 | ??0.50 |
| GIZO individual layer (comparative example) | ??13 | ??0.35 | ??0.75 |
When as in conventional transistor with single oxide skin(coating) when the channel layer, the carrier concentration of channel layer need be reduced with threshold voltage to (+) side shifting just, thereby reduce transistorized mobility.Yet,, can have the threshold voltage of expectation, good mobility and the transistor of SS characteristic as channel layer manufacturing by utilizing double-deck oxide skin(coating) according to embodiments of the invention.
Fig. 8 is the transistorized grid voltage V that illustrates according to illustrated embodiments of the invention
g-drain current I
dThe curve chart of characteristic comprises as the ITO layer of ground floor 10 with as the GIZO layer of the second layer 20 according to the transistor of illustrated embodiments of the invention.Solid line among Fig. 8 represents to utilize the GIZO individual layer not have the characteristics of transistor of ITO layer as channel layer.
The result of Fig. 8 is similar to the result of Fig. 5.That is, has thickness for about
The transistorized grid voltage V of thin ITO layer
g-drain current I
dCharacteristic and transistorized grid voltage V with GIZO individual layer
g-drain current I
dCharacteristic is similar, but the ON electric current increases.Has thickness for about
The transistorized threshold voltage of ITO layer to have a GIZO individual layer similar as the transistorized threshold voltage of channel layer, but the ON electric current has significantly increased.The increase of transistorized mobility is represented in the increase of On electric current.In addition, if the thickness of ITO layer is about
Then curve moves to negative (-) side.For this reason, with comprising thickness be
The transistor of ITO layer compare, comprise that thickness is
The transistorized mobility of ITO layer increase slightly.
Fig. 9 is transistorized threshold voltage (V) and the mobility (cm that illustrates according to illustrated embodiments of the invention
2/ Vs) about the curve chart of the thickness of transistorized ITO layer.
With reference to Fig. 9, along with the thickness increase of ITO layer, mobility increases, and threshold voltage reduces.Specifically, the thickness when the ITO layer is about
Extremely
The time, the variation maximization of mobility.Along with the thickness of ITO layer increase to greater than
Variations in threshold voltage increases.
Hereinafter, will describe according to the transistorized method of the manufacturing of illustrated embodiments of the invention.
Figure 10 A to Figure 10 D is the cutaway view according to the transistorized method of manufacturing of example embodiment.Transistor according to example embodiment can be for having the TFT of bottom grating structure.The transistor of making according to Figure 10 A to Figure 10 D can be corresponding with the transistor of Fig. 1.Identical label is used to represent components identical.
With reference to Figure 10 A, can on substrate SUB1, form grid G 1.Can on substrate SUB1, form gate insulator GI1 with cover gate G1.Gate insulator GI1 can be formed by silica, silicon nitride or other material that is fit to.
With reference to Figure 10 B, can on gate insulator GI1, form and comprise the ground floor 10 that order forms and the channel layer C1 of the second layer 20.Channel layer C1 can be positioned at grid G 1 top.Can utilize physical vapor deposition (PVD) method (such as sputter or evaporation) to deposit the ground floor 10 and the second layer 20, perhaps can utilize identical mask layer ground floor 10 and the second layer 20 patternings.
With reference to Figure 10 C, can on gate insulator GI1, form source electrode S1 and drain electrode D1, to contact the opposite end of channel layer C1 respectively, expose the part of the upper surface of channel layer C1 simultaneously.Source electrode S1 and drain electrode D1 all can form single metal layer or many metal levels.
With reference to Figure 10 D, can on substrate SUB1, form passivation layer P1 to cover expose portion, source electrode S1, the drain electrode D1 of channel layer C1.According to example embodiment, can anneal to resulting structures with predetermined temperature, thereby finish transistor.
Figure 11 A to Figure 11 D is the cutaway view according to the transistorized method of manufacturing of another example embodiment.This transistor can be for having the TFT of top gate structure.The transistor of making according to Figure 11 A to Figure 11 D can be corresponding with the transistor of Fig. 2.Identical label is used to represent components identical.
With reference to Figure 11 A, can on substrate SUB2, form channel layer C2.Channel layer C2 can have comprise order be formed on the second layer 20 on the substrate SUB2 ' and ground floor 10 ' double-decker.Form ground floor 10 ' and the second layer 20 ' method can be similar with the method for the second layer 20 to the ground floor 10 of formation Figure 10 B.
With reference to Figure 11 B, source electrode S2 and drain electrode D2 can be formed, on substrate SUB2 to contact the opposite end of channel layer C2 respectively.
With reference to Figure 11 C, can on substrate SUB2, form gate insulator GI2 to cover expose portion, source electrode S2, the drain electrode D2 of channel layer C2.Can on gate insulator GI2, form grid G 2.Grid G 2 can be positioned at channel layer C2 top.Grid G 2 can be formed by the metal identical with the metal that is used to form source electrode S2 and drain electrode D2.Selectively, grid G 2 can be formed by the material different with the material that is used to form source electrode S2 and drain electrode D2.
With reference to Figure 11 D, can on gate insulator GI2, form passivation layer P2 with cover gate G2.Passivation layer P2 can be formed by silicon oxide layer or silicon nitride layer.According to example embodiment, can anneal to resulting structures with predetermined temperature, thereby finish transistor.
Though illustrated and described example embodiment with reference to accompanying drawing, the application's scope should not be understood that to be limited to example embodiment.For example, it will be appreciated by one skilled in the art that other transistor that the instruction here can be applied to except that TFT.In addition, can be with transistorized composed component and the structure of modified in various forms Fig. 1 and Fig. 2.According to the transistor of example embodiment can not be enhancement transistor but depletion mode transistor.Transistor not only can be used for liquid crystal display (LCD) equipment and oganic light-emitting display device, and can be used for storage device and logic device.Therefore, the application's scope should not be interpreted as being limited to irrelevantly the literal of detailed description.
Though specifically illustrate and described each side of the present invention, it should be understood that these exemplary embodiments should be construed as merely descriptive, and be not purpose for restriction with reference to different embodiment of the present invention.It is available that the feature of each embodiment or the description of aspect should be considered to for other similar feature among other the embodiment or aspect usually.
Though disclose example embodiment here, it should be understood that and to carry out other variation.Such variation should not be considered to have broken away from the spirit and scope of the application's example embodiment, and be intended to all such should be that conspicuous modification comprises within the scope of the claims to those skilled in the art.
Claims (20)
1, a kind of transistor comprises:
Channel layer comprises lower floor and upper strata, and the mobility on lower floor and upper strata is different and formed by different oxide materials;
Source electrode and drain electrode contact the opposite end of channel layer respectively;
Grid is used for electric field is applied to channel layer.
2, transistor as claimed in claim 1, wherein, the mobility of one deck of more close grid is higher than another layer further from grid in lower floor and the upper strata.
3, transistor as claimed in claim 1, wherein, one deck of more close grid is determined transistorized mobility in lower floor and the upper strata.
4, transistor as claimed in claim 1, wherein, transistorized threshold voltage is determined by the one deck at least in lower floor and the upper strata.
5, transistor as claimed in claim 1, wherein, one deck of more close grid comprises at least a oxide of selecting in lower floor and the upper strata from the group of being made up of indium zinc oxide, tin indium oxide, aluminum zinc oxide, gallium oxide zinc.
6, transistor as claimed in claim 1, wherein, the one deck further from grid in lower floor and the upper strata comprises the ZnO type oxide.
7, transistor as claimed in claim 1, wherein, the thickness of one deck of more close grid is in lower floor and the upper strata
Extremely
8, transistor as claimed in claim 7, wherein, the thickness of one deck of more close grid is in lower floor and the upper strata
Extremely
9, transistor as claimed in claim 1, described transistor are the thin-film transistor of top gate structure or the thin-film transistor of bottom grating structure.
10, a kind of transistor comprises:
Channel layer comprises lower floor and upper strata, and the carrier density on lower floor and upper strata is different and formed by different oxide materials;
Source electrode and drain electrode contact the opposite end of channel layer respectively;
Grid is used for electric field is applied to channel layer.
11, transistor as claimed in claim 10, wherein, the carrier density of one deck of more close grid is higher than another layer further from grid in lower floor and the upper strata.
12, transistor as claimed in claim 10, wherein, the mobility on lower floor and upper strata is different.
13, transistor as claimed in claim 12, wherein, the mobility of one deck of more close grid is higher than another layer further from grid in lower floor and the upper strata.
14, want 10 described transistors as right, wherein, one deck of more close grid is determined transistorized mobility in lower floor and the upper strata.
15, transistor as claimed in claim 10, wherein, transistorized threshold voltage is determined by the one deck at least in lower floor and the upper strata.
16, transistor as claimed in claim 10, wherein, one deck of more close grid comprises at least a oxide of selecting in lower floor and the upper strata from the group of being made up of indium zinc oxide, tin indium oxide, aluminum zinc oxide, gallium oxide zinc.
17, transistor as claimed in claim 10, wherein, the one deck further from grid in lower floor and the upper strata comprises the ZnO type oxide.
18, transistor as claimed in claim 10, wherein, the thickness of one deck of more close grid is in lower floor and the upper strata
Extremely
19, transistor as claimed in claim 18, wherein, the thickness of one deck of more close grid is in lower floor and the upper strata
Extremely
20, transistor as claimed in claim 10, described transistor are the thin-film transistor of top gate structure or the thin-film transistor of bottom grating structure.
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| KR10-2009-0033846 | 2009-04-17 | ||
| KR1020090033846 | 2009-04-17 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1906770A (en) * | 2004-01-23 | 2007-01-31 | 惠普开发有限公司 | Transistor including a deposited channel region having a doped portion |
| US20070063211A1 (en) * | 2005-09-06 | 2007-03-22 | Canon Kabushiki Kaisha | Thin-film transistor and thin-film diode having amorphous-oxide semiconductor layer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003298062A (en) * | 2002-03-29 | 2003-10-17 | Sharp Corp | Thin film transistor and its manufacturing method |
| JP4907942B2 (en) * | 2005-09-29 | 2012-04-04 | シャープ株式会社 | Transistors and electronic devices |
-
2009
- 2009-04-17 KR KR1020090033846A patent/KR101603775B1/en active IP Right Grant
- 2009-07-14 CN CN200910140008.7A patent/CN101630692B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1906770A (en) * | 2004-01-23 | 2007-01-31 | 惠普开发有限公司 | Transistor including a deposited channel region having a doped portion |
| US20070063211A1 (en) * | 2005-09-06 | 2007-03-22 | Canon Kabushiki Kaisha | Thin-film transistor and thin-film diode having amorphous-oxide semiconductor layer |
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| CN113809182B (en) * | 2020-06-16 | 2023-09-08 | 京东方科技集团股份有限公司 | Metal oxide thin film transistor, preparation method thereof and array substrate |
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Also Published As
| Publication number | Publication date |
|---|---|
| KR20100007703A (en) | 2010-01-22 |
| KR101603775B1 (en) | 2016-03-18 |
| CN101630692B (en) | 2016-03-02 |
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