KR20100007703A - Channel layer and transistor comprising the same - Google Patents

Abstract

PURPOSE: A channel layer and a transistor including the same are provided to control a threshold voltage and the mobility of a transistor by comprising the channel layer with a first layer and a second layer with different carrier density and/or mobility. CONSTITUTION: A transistor includes a channel layer(C1), a source(S1), a drain(D1), and a gate(G1). The channel layer has different mobility and includes a lower layer(10) and an upper layer(20). The lower layer and the upper layer are made of the different oxide. The source and the drain are contacted with both sides of the channel layer. The gate applies the electric field to the channel layer. The closest layer to the gate among the lower layer and the upper layer determines the mobility of the transistor.

Description

Channel layer and transistor comprising the same

The present disclosure relates to a channel layer and a transistor comprising the same.

Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, the thin film transistor is usefully used in the field of flat panel display devices such as a liquid crystal display device or an organic light emitting display device.

In order to improve the operating characteristics of a transistor, a method of applying an oxide semiconductor layer as a channel layer has been attempted. This method is mainly applied to thin film transistors for flat panel display devices. However, in the case of a transistor having an oxide semiconductor layer as a channel layer (hereinafter, a conventional oxide transistor), it is difficult to control a threshold voltage.

In more detail, the conventional oxide transistor mainly uses an n-type oxide layer as a channel layer, which obtains a high on / off current ratio and a small subthreshold slope (SS). In order to increase the carrier concentration of the n-type oxide layer, the crystallinity must be excellent. Therefore, in order to control the threshold voltage, if the carrier concentration of the n-type oxide layer is lowered, mobility of the transistor is lowered, such that the on / off current ratio is decreased and the sub-threshold slope SS is deteriorated. A problem arises. In addition, when the carrier concentration of the n-type oxide layer is high, the threshold voltage becomes very small in the negative direction, making it difficult to implement an enhancement mode transistor.

One aspect of the invention relates to oxide transistors in which mobility and threshold voltages are controlled.

According to one aspect of the invention, the channel layer having a different mobility (mobility), including a lower layer and an upper layer formed of different oxides; Source and drain in contact with both ends of the channel layer, respectively; And a gate for applying an electric field to the channel layer.

Among the lower and upper layers, a layer close to the gate may have a higher mobility than a layer disposed far from the gate.

A layer close to the gate of the lower layer and the upper layer may be a layer that determines mobility of the transistor.

The threshold voltage of the transistor may be determined by at least one of the lower layer and the upper layer.

When the thickness of the lower layer and the upper layer among the upper layers (hereinafter, referred to as the first layer) is in the first range, the lower layer and the upper layer (hereinafter referred to as the second layer) are disposed away from the gate. The threshold voltage of the transistor may be determined, and when the thickness of the first layer is in a second range larger than the first range, the threshold voltage may be determined by the first and second layers, and the first When the thickness of the layer is in the third range larger than the second range, the threshold voltage may be determined by the first layer.

The lower layer and the upper layer may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO).

The layer disposed far from the gate among the lower layer and the upper layer may include a ZnO-based oxide.

The thickness of the lower layer and the upper layer close to the gate may be in the range of about 10 to about 500 microns.

The thickness of the lower layer and the upper layer close to the gate may be in the range of about 30 to about 200 kPa.

The thickness of the lower layer and the upper layer disposed far from the gate may be 10 to 2000 microns.

The thickness of the lower layer and the upper layer disposed far from the gate may be equal to or greater than the thickness of other layers.

The transistor may be a thin film transistor having a top-gate or bottom-gate structure.

According to another aspect of the invention, the channel layer having a different carrier density (carrier density), including a lower layer and an upper layer formed of different oxides; Source and drain in contact with both ends of the channel layer, respectively; And a gate for applying an electric field to the channel layer.

A layer closer to the gate of the lower layer and the upper layer may have a higher carrier density than the layer disposed farther from the gate.

The lower layer and the upper layer may have different mobility.

Among the lower and upper layers, a layer close to the gate may have a higher mobility than a layer disposed far from the gate.

A layer close to the gate of the lower layer and the upper layer may be a layer that determines mobility of the transistor.

The threshold voltage of the transistor may be determined by at least one of the lower layer and the upper layer.

When the thickness of the lower layer and the upper layer among the upper layers (hereinafter, referred to as the first layer) is in the first range, the lower layer and the upper layer (hereinafter referred to as the second layer) are disposed away from the gate. The threshold voltage of the transistor may be determined, and when the thickness of the first layer is in a second range larger than the first range, the threshold voltage may be determined by the first and second layers, and the first When the thickness of the layer is in the third range larger than the second range, the threshold voltage may be determined by the first layer.

The lower layer and the upper layer among the upper layers may include at least one of IZO, ITO, AZO, and GZO.

A layer disposed far from the gate among the lower layer and the upper layer may include an oxide of a ZnO series.

The thickness of the lower layer and the upper layer close to the gate may be in the range of about 10 to about 500 microns.

The thickness of the lower layer and the upper layer close to the gate may be in the range of about 30 to about 200 kPa.

The thickness of the lower layer and the upper layer disposed far from the gate may be 10 to 2000 microns.

The thickness of the lower layer and the upper layer disposed far from the gate may be equal to or greater than the thickness of other layers.

The transistor may be a thin film transistor having a top-gate or bottom-gate structure.

According to an embodiment of the present invention, a transistor having a desired threshold voltage and excellent characteristics such as mobility can be implemented.

Hereinafter, a channel layer and a transistor including the channel layer according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. The width and thickness of the layers or regions shown in the accompanying drawings are somewhat exaggerated for clarity. Like numbers refer to like elements throughout.

1 shows a transistor T1 according to an embodiment of the present invention. The transistor T1 of the present embodiment is a thin film transistor having a bottom gate structure in which the gate G1 is formed under the channel layer C1.

Referring to FIG. 1, a gate G1 is formed on a substrate SUB1. The substrate SUB1 may be one of a silicon substrate, a glass substrate, and a plastic substrate, and may be transparent or opaque. A gate insulating layer GI1 covering the gate G1 is formed on the substrate SUB1. The gate insulating layer GI1 may be a silicon oxide layer or a silicon nitride layer, but may be another material layer. The channel layer C1 is provided on the gate insulating layer GI1 above the gate G1. The width of the X-axis direction of the channel layer C1 may be slightly larger than the width of the X-axis direction of the gate G1. The channel layer C1 may have a multilayer structure including at least two oxide layers having different mobility and / or carrier density. For example, the channel layer C1 has a double layer structure including a first oxide layer (hereinafter referred to as a first layer) 10 and a second oxide layer (hereinafter referred to as a second layer) 20 on the first layer 10. Can have The first layer 10 is disposed closer to the gate G1 than the second layer 20. In this case, the mobility of the first layer 10 may be greater than the mobility of the second layer 20. Alternatively, the carrier density of the first layer 10 may be greater than the carrier density of the second layer 20. More detailed description of the mobility and carrier density of the material is as follows. Material mobility and carrier density are independent variables. However, in oxides, carrier density and mobility are generally proportional. That is, the oxide having a higher carrier density may have greater mobility. But in some cases it may not. That is, even an oxide having a high carrier density may have low mobility. On the other hand, in general, the higher the carrier density and / or mobility of the oxide layer used as the channel layer, the higher the mobility of the transistor including the same. However, even if the oxide layer having a low mobility has a high carrier density, the mobility of the transistor employing it as the channel layer may be high. The carrier density and / or mobility of the channel material affects not only the mobility of the transistor but also the threshold voltage. For example, as the carrier density of the channel material is lower, the threshold voltage of the transistor may move in a positive direction. As in this embodiment, when the channel layer C1 is formed by stacking the first and second layers 10 and 20 having different carrier densities and / or mobility, the mobility and threshold voltage of the transistor including the same Can be easily controlled. This will be described in more detail as follows.

The first layer 10 is a layer disposed closer to the gate G1 than the second layer 20, and may increase the mobility of the transistor T1. That is, when the first layer 10 is present, the mobility of the transistor T1 may be higher than when it is not (that is, when all of the channel layers C1 are made of the material of the second layer 20). Since the first layer 10 may have a higher carrier density and / or mobility than the second layer 20, the mobility of the transistor T1 may increase. Even if the first layer 10 has a low mobility, if its carrier density is high, the mobility of the transistor T1 may be increased by the first layer 10. Meanwhile, when the thickness of the first layer 10 is thin, the threshold voltage of the transistor T1 may depend on the second layer 20 rather than the first layer 10. For example, when the first layer 10 has an appropriately thin thickness, the threshold voltage of the transistor T1 may be adjusted according to the material, composition, carrier density, etc. of the second layer 20. The second layer 20 may have a lower carrier density and / or mobility than the first layer 10, so if there is a second layer 20, otherwise (ie, the channel layer C1 is all The threshold voltage of the transistor T1 may be moved in a positive direction than in the case of the material of the first layer 10). Accordingly, the transistor T1 according to the present embodiment may be an enhancement mode transistor having high mobility and having a positive threshold voltage. However, when the thickness of the first layer 10 becomes thicker to some extent, the influence of the first layer 10 on the threshold voltage of the transistor T1 may gradually increase. In this case, the threshold voltage of the transistor T1 may be simultaneously affected by the first layer 10 and the second layer 20. As the influence of the first layer 10 increases, the threshold voltage of the transistor T1 may move in the negative direction. When the thickness of the first layer 10 becomes thicker than a predetermined thickness, the threshold voltage of the transistor T1 may be influenced by the first layer 10 rather than the second layer 20.

As a specific example, the first layer 10 may be a layer including at least one of indium zinc oxide (IZO), indium tin oxide (ITO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO). In addition, the second layer 20 may be a layer including a ZnO-based oxide. In this case, the second layer 20 may further include a Group 3 element such as Ga and In. For example, the second layer 20 may be a gallium indium zinc oxide (GIZO) layer. The second layer 20 may be a ZnO-based oxide layer doped with Group 4 elements such as Sn or other elements instead of the Group 3 elements. The thickness of the first layer 10 may be about 10 to 500 mm wide and about 30 to 200 mm narrow. If the first layer 10 is too thin, the effect of increasing the mobility of the transistor T1 by the first layer 10 may be reduced. In addition, if the first layer 10 is too thick, it may be difficult to form a channel in the second layer 20, thereby reducing the effect of increasing the threshold voltage by the second layer 20. That is, when the first layer 10 is thickened, the threshold voltage of the transistor T1 may be simultaneously affected by the first and second layers 10 and 20, and when the first layer 10 is thicker, The threshold voltage of the transistor T1 may be determined by the first layer 10 rather than the second layer 20. Therefore, according to the purpose, it may be easy to appropriately adjust the threshold voltage of the transistor T1. If it is desired to move the threshold voltage of the transistor T1 in the positive direction, the first layer 10 may be formed thin to increase the effect of increasing the threshold voltage by the second layer 20. On the other hand, when it is desired to move the threshold voltage of the transistor T1 in the negative direction, the first layer 10 may be formed to be thick enough so that the threshold voltage is lowered by the first layer 10. The first layer 10 may be formed to a thickness of about 10 to 500 kV, and may be formed to a thickness of about 30 to 200 kV to obtain an effect of increasing the threshold voltage by the second layer 20. The thickness of the first layer 10 suitable for obtaining the threshold voltage increase effect of the second layer 20 may vary depending on the materials of the first and second layers 10 and 20. In addition, the thickness range may vary depending on the size and type of the transistor to be implemented. On the other hand, the second layer 20 may be formed to a thickness of about 10 ~ 2000Å, it may be formed the same or thicker than the first layer (10).

The source electrode S1 and the drain electrode D1 are formed on the gate insulating layer GI1 to be in contact with both ends of the channel layer C1, respectively. The source electrode S1 and the drain electrode D1 may be a single metal layer or multiple metal layers. The source electrode S1 and the drain electrode D1 may be the same metal layer as the gate G1, but may be another metal layer. A passivation layer P1 is formed on the gate insulating layer GI1 to cover the channel layer C1, the source electrode S1, and the drain electrode D1. The protective layer P1 may be a silicon oxide layer or a silicon nitride layer. The thickness of the gate G1, the gate insulating layer GI1, the source electrode S1, and the drain electrode D1 may be about 50 to 300 nm, 50 to 300 nm, 10 to 200 nm, and 10 to 200 nm, respectively.

2 shows a transistor T2 according to another embodiment of the present invention. The transistor T2 according to the present embodiment is a thin film transistor having a top gate structure in which the gate G2 is formed on the channel layer C2.

Referring to FIG. 2, a channel layer C2 is provided on the substrate SUB2. The channel layer C2 may have a structure in which the channel layer C1 of FIG. 1 is turned upside down. That is, the channel layer C2 of FIG. 2 is formed of the second layer 20 'equivalent to the second layer 20 of FIG. 1 and the first layer 10 of FIG. 1 on the substrate SUB2. The first layer 10 ′ may have a structure sequentially provided. The source electrode S2 and the drain electrode D2 are formed on the substrate SUB2 so as to be in contact with both ends of the channel layer C2, respectively. A gate insulating layer GI2 is formed on the substrate SUB2 to cover the channel layer C2, the source electrode S2, and the drain electrode D2. The gate G2 is formed on the gate insulating layer GI2. Gate G2 is located above channel layer C2. Therefore, the first layer 10 'is disposed closer to the gate G2 than the second layer 20'. A protective layer P2 is formed on the gate insulating layer GI2 to cover the gate G2.

The substrate SUB2, the first layer 10 ′, the second layer 20 ′, the source electrode S2, the drain electrode D2, the gate insulating layer GI2, the gate G2, and the protective layer of FIG. 2. Each of the materials and thicknesses of the substrate PB1 includes the substrate SUB1, the first layer 10, the second layer 20, the source electrode S1, the drain electrode D1, the gate insulating layer GI1, and the like. It may be the same as those of each of the gate G1 and the protective layer P1. In addition, in FIG. 2, the role of the first layer 10 ′ and the second layer 20 ′ may be the same as the role of the first layer 10 and the second layer 20 of FIG. 1.

3 shows the characteristics of the gate voltage (V _g ) -drain current (I _d ) of the transistor according to the first embodiment, the first comparative example and the second comparative example of the present invention. In FIG. 3, the first graph G1 is a transistor according to the first embodiment of the present invention (hereinafter, the first transistor of the present invention), more specifically, has the structure of FIG. 1, but includes the first layer 10 and the first transistor. The results correspond to the transistors using the IZO layer and the GIZO layer as the two layers 20, respectively. At this time, the thicknesses of the IZO layer and the GIZO layer were 50 kPa and 600 kPa, respectively. The second graph G2 is a result corresponding to the transistor according to the first comparative example using a GIZO single layer (thickness: 600 mW) as the channel layer, and the third graph G3 is a IZO single layer (thickness: The result corresponds to the transistor according to the second comparative example using 500 Hz). On the other hand, the drain voltage used to obtain the result of FIG. 3 was 1V. This drain voltage was also used to obtain the characteristic graphs of FIGS. 5 and 7.

Comparing the first and second graphs G1 and G2 of FIG. 3, the ON current of the first graph G1 is about 10 ⁻³ A, and the ON current of the second graph G2 (about 3 times higher than 3 × 10 ^-4 A). In fact, the mobility of the first transistor of the present invention was about three times higher than that of the transistor according to the first comparative example. Table 1 shows the mobility and subthreshold slope SS of the transistor according to the first transistor and the first comparison example of the present invention.

Channel type Mobility (㎠ / V · s) Subthreshold Slope (V / dec) IZO / GIZO Bilayer (This Example) 52 0.19 GIZO Single Layer (Comparative Example) 19 0.19

FIG. 4 is a graph in which the first to third graphs G1 to G3 of FIG. 3 are converted to a linear scale. In FIG. 4, the first to third graphs G1 ′ to G3 ′ correspond to the first to third graphs G1 to G3 of FIG. 3, respectively. The gate voltage at the point where the tangents of the first to third graphs G1 'to G3' meet the X-axis is the threshold voltage of the transistor corresponding to each graph.

Referring to FIG. 4, the threshold voltage of the transistor corresponding to the first graph G1 ′ is about 0.31V, and the threshold voltage of the transistor corresponding to the second graph G2 ′ is about −0.60V. That is, the threshold voltage of the first transistor of the present invention corresponding to the first graph G1 ′ is very similar to the threshold voltage of the transistor according to the first comparative example corresponding to the second graph G2 ′. On the other hand, in the case of the transistor corresponding to the third graph G3 ', that is, in the case of the transistor according to the second comparative example using the IZO single layer as the channel layer, the threshold voltage is very low as -8V. This indicates that the transistor according to the second comparative example is a depletion mode transistor, not an enhancement mode transistor. As described above, the threshold voltage of the first transistor of the present invention is similar to the threshold voltage of the transistor according to the first comparative example and has a positive value, whereas the threshold voltage of the transistor according to the second comparative example The threshold voltage has a relatively very small negative value. The first transistor of the present invention is an IZO / GIZO channel layer, the transistor according to the first comparative example is a GIZO channel layer, the transistor according to the second comparative example considering that the IZO channel layer, It can be seen that the threshold voltage of the first transistor of is dependent on the GIZO layer, not the IZO layer.

That is, when the GIZO single layer is applied as the channel layer as in the first comparative example, it is difficult to obtain high mobility, and when the IZO single layer is applied as the channel layer as in the second comparative example, the threshold voltage is increased small. It is difficult to implement an enhancement mode transistor. However, according to the first embodiment of the present invention, it is possible to implement an enhancement mode transistor with high mobility. However, at this time, the thickness of the IZO layer in the channel layer (IZO / GIZO) of the first transistor of the present invention was as thin as 50 Å. If a transistor having a low threshold voltage is to be implemented, the influence of the IZO layer on the threshold voltage may be increased by increasing the thickness of the IZO layer in the channel layer IZO / GIZO.

5 is a gate voltage (V _g ) -drain current (I) according to the thickness of the IZO layer of the transistor having the structure of FIG. _d ) show changes in properties. The solid line graph in FIG. 5 corresponds to a transistor having a zero thickness of the IZO layer, that is, a transistor using a GIZO single layer as a channel layer.

From Figure 5, the thickness of the IZO layer thin gate voltage (V _g) when about 30Å - drain current (I _d) characteristic is the gate voltage (V _g) of the case of applying the GIZO single layer as the channel layer, the drain current (I _d ) similar characteristics. When the thickness of the IZO layer is about 50 mA, the threshold voltage is similar to that when the GIZO single layer is applied as the channel layer, but the ON current is considerably increased. The increase in the ON current means that the mobility of the transistor is increased. In addition, it can be seen that when the thickness of the IZO layer is as thick as 100 kPa, the graph is moved in the negative direction as a whole. At this time, the mobility of the transistor increased more than the case where the thickness of the IZO layer was 50 kPa. The characteristics of the transistor having an excessively thin thickness of the IZO layer may be similar to those of a transistor in which a single layer of GIZO is applied as a channel layer. That is, it can be similar to a transistor in which an IZO single layer is applied as a channel layer. The thickness of the IZO layer can be appropriately determined depending on the intended use.

FIG. 6 shows the change in threshold voltage and mobility of the transistor according to the thickness of the IZO layer as a result obtained from FIG. 5.

Referring to FIG. 6, it can be seen that as the thickness of the IZO layer increases within the measurement range, the mobility increases and the threshold voltage decreases. In particular, in the case of mobility, the change amount is large in the IZO thickness range of 30 to 50 mA, and the change amount of the threshold voltage tends to increase gradually as the thickness of the IZO layer increases.

7 shows the gate voltage (V _g ) -drain current (I _d ) characteristics of the transistors according to the second, third and fourth comparative examples of the present invention. In FIG. 7, the first graph GG1 is a transistor according to the second embodiment of the present invention (hereinafter, the second transistor of the present invention), more specifically, has the structure of FIG. 1, but includes the first layer 10 and The result corresponds to a transistor using the ITO layer and the GIZO layer as the second layer 20, respectively. In this case, the thicknesses of the ITO layer and the GIZO layer were 50 kPa and 600 kPa, respectively. The second graph GG2 is a result corresponding to the transistor according to the third comparative example, that is, a transistor using a GIZO single layer (thickness: 600 mW) as the channel layer, and the third graph GG3 is the fourth comparative example. This results in a transistor corresponding to the transistor according to the present invention, that is, a transistor using an ITO single layer (thickness: 50 mW) as the channel layer. In addition, although the transistor according to the third comparative example is structurally almost identical to the transistor according to the first comparative example described with reference to FIG. 3, the two transistors are somewhat different in forming conditions.

When comparing the first and second graphs GG1 and GG2 of FIG. 7, the ON current of the first graph GG1 is about 5 × 10 ⁻⁵ A and the ON current of the second graph GG2 is about 5 × 10 ⁻⁵ A. It is about ten times higher than (about 5 × 10 ^-6 A). In fact, the mobility of the second transistor of the present invention corresponding to the first graph GG1 is about ten times higher than the mobility of the transistor according to the third comparative example corresponding to the second graph GG2. In addition, it can be seen that the slope of the first graph GG1 is slightly larger than the slope of the second graph GG2 at the turn-on point. That is, the subthreshold slope SS of the second transistor of the present invention is smaller than the subthreshold slope SS of the transistor according to the third comparative example. This is because, as in the second transistor of the present invention, when the channel layer of the double layer structure is used, the turn-on speed of the transistor is higher than when the channel layer of the single layer structure is used as in the third comparative example. Is faster. Table 2 summarizes the mobility, sub-threshold slope and threshold voltage of the transistor according to the second transistor and the third comparative example of the present invention.

Channel type Mobility (㎠ / V · s) Subthreshold Slope (V / dec) Threshold Voltage (V) ITO / GIZO Double Layer (This Example) 104 0.25 0.50 GIZO Single Layer (Comparative Example) 13 0.35 0.75

In the case of using a single oxide layer as a channel layer as in the related art, in order to move the threshold voltage in a positive direction, since the carrier concentration of the channel layer must be reduced, there is a problem that the mobility of the transistor is reduced. However, according to the exemplary embodiment of the present invention, by using an oxide layer having a double layer structure as a channel layer, a transistor having a desired threshold voltage and excellent characteristics such as mobility and sub-threshold slope may be implemented.

FIG. 8 is a gate voltage (V _g ) -drain current (I) according to the thickness of the ITO layer of the transistor having the structure of FIG. 1 but using the ITO layer and the GIZO layer as the first layer 10 and the second layer 20, respectively. _d ) show changes in properties. The solid line graph in FIG. 8 corresponds to a transistor having a zero thickness of the ITO layer, that is, a transistor using a GIZO single layer as a channel layer.

The result of FIG. 8 is similar to FIG. 5. That is, in FIG. 8, the gate voltage (V _g ) -drain current (I _d ) characteristics when the thickness of the ITO layer is as thin as about 30 μs are similar to those when the GIZO single layer is applied as the channel layer, but the ON current is somewhat Increased. When the thickness of the ITO layer is about 50 mA, the threshold voltage is similar to that when the GIZO single layer is applied as the channel layer, but the ON current is considerably increased. An increase in the ON current means an increase in the mobility of the transistor. In addition, it can be seen that when the thickness of the ITO layer is about 80 mm, the graph is moved in the negative direction as a whole. At this time, the mobility of the transistor slightly increased than the case where the thickness of the ITO layer was 50 kPa.

FIG. 9 shows the change in threshold voltage and mobility of the transistor according to the thickness of the ITO layer as a result obtained from FIG. 8.

Referring to FIG. 9, it can be seen that as the thickness of the ITO layer increases within the measurement range, the mobility increases and the threshold voltage decreases. In particular, in the case of mobility, the amount of change is large in the ITO thickness range of 30 to 50 mA, and the amount of change in the threshold voltage tends to increase as the thickness of the ITO layer increases to 50 mA or more.

Hereinafter, a method of manufacturing a transistor according to embodiments of the present invention will be described.

10A to 10D show a method of manufacturing a transistor according to an embodiment of the present invention. The present embodiment is a method of manufacturing a thin film transistor having a bottom gate structure. Like reference numerals in FIGS. 1 and 10A to 10D denote like elements.

Referring to FIG. 10A, a gate G1 is formed on the substrate SUB1, and a gate insulating layer GI1 covering the gate G1 is formed on the substrate SUB1. The gate insulating layer GI2 may be formed of silicon oxide, silicon nitride, or other materials.

Referring to FIG. 10B, a channel layer C1 having a first layer 10 and a second layer 20 sequentially stacked on the gate insulating layer GI1 is formed. In this case, the channel layer C1 is positioned on the gate G1. The first layer 10 and the second layer 20 may be deposited by physical vapor deposition (PVD), such as sputtering or evaporation, and the same mask layer may be formed. May be patterned layers.

Referring to FIG. 10C, a source electrode S1 and a drain electrode D1 are formed on the gate insulating layer GI1 to contact both ends of the channel layer C1 and expose a portion of the upper surface of the channel layer C1. do. The source electrode S1 and the drain electrode D1 may be formed of a single metal layer or multiple metal layers.

Referring to FIG. 10D, a protective layer P1 is formed on the substrate SUB1 to cover the exposed portion of the channel layer C1 and the source electrode S1 and the drain electrode D1. Transistors formed in this manner can be annealed at a predetermined temperature.

11A to 11D show a method of manufacturing a transistor according to another embodiment of the present invention. This embodiment is a method of manufacturing a thin film transistor having a top gate structure. Like reference numerals in FIGS. 2 and 11A to 11D denote like elements.

Referring to FIG. 11A, a channel layer C2 is formed on the substrate SUB2. The channel layer C2 may be formed in a double layer structure including a second layer 20 ′ and a first layer 10 ′ sequentially stacked on the substrate SUB2. The method of forming the first layer 10 ′ and the second layer 20 ′ of FIG. 11A may be similar to the method of forming the first layer 10 and the second layer 20 described with reference to FIG. 10B.

Referring to FIG. 11B, a source electrode S2 and a drain electrode D2 are formed on the substrate SUB2 to contact both ends of the channel layer C2, respectively.

Referring to FIG. 11C, a gate insulating layer GI2 is formed on the substrate SUB1 to cover the exposed portion of the channel layer C2, the source electrode S2, and the drain electrode D2. Subsequently, a gate G2 is formed on the gate insulating layer GI2. The gate G2 is formed to be positioned on the channel layer C2. The gate G2 may be formed of the same metal or different metal as the source electrode S2 and the drain electrode D2.

Referring to FIG. 11D, a protective layer P2 is formed on the gate insulating layer GI2 to cover the gate G2. The protective layer P2 may be formed of silicon oxide or silicon nitride. Transistors formed in this manner can be annealed at a predetermined temperature.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those skilled in the art will appreciate that the idea of the present invention may be applied to other transistors other than thin film transistors. In addition, it will be appreciated that the components and structures of the transistors of FIGS. 1 and 2 may be diversified and modified, respectively. The transistors according to the embodiments of the present invention may be depleted rather than increased. It will be appreciated that the present invention can be applied to not only an organic light emitting display device but also a memory device and a logic device. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

1 is a cross-sectional view showing a transistor according to an embodiment of the present invention.

2 is a cross-sectional view illustrating a transistor according to another embodiment of the present invention.

3 is a graph showing the gate voltage (Vg) -drain current (Id) characteristics of the transistor according to the embodiment and the comparative examples of the present invention.

FIG. 4 is a graph obtained by converting FIG. 3 to a linear scale.

5 is a graph showing a change in gate voltage (V _g ) -drain current (I _d ) characteristics according to the thickness of the IZO layer of the transistor according to an embodiment of the present invention.

6 is a graph showing changes in threshold voltage and mobility according to the thickness of an IZO layer of a transistor according to an embodiment of the present invention.

7 is a graph illustrating gate voltage (Vg) and drain current (Id) characteristics of a transistor according to another embodiment and comparative examples of the present invention.

8 is a graph showing a change in gate voltage (V _g ) -drain current (I _d ) characteristics according to the thickness of the ITO layer of a transistor according to another embodiment of the present invention.

9 is a graph showing changes in threshold voltage and mobility according to a thickness of an ITO layer of a transistor according to another embodiment of the present invention.

10A to 10D are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

11A to 11D are cross-sectional views illustrating a method of manufacturing a transistor according to another embodiment of the present invention.

* Explanation of Signs of Major Parts of Drawings *

10, 10 ': first layer 20, 20': second layer

C1, C2: channel layer D1, D2: drain electrode

G1, G2: Gate GI1, GI2: Gate Insulation Layer

P1, P2: protective layer S1, S2: source electrode

SUB1, SUB2: Board

Claims (20)

A channel layer having different mobility and including a lower layer and an upper layer formed of different oxides; Source and drain in contact with both ends of the channel layer, respectively; And And a gate for applying an electric field to the channel layer. The method of claim 1, And a layer closer to the gate of the lower layer and the upper layer has a higher mobility than the layer disposed farther from the gate. The method of claim 1, And a layer close to the gate of the lower layer and the upper layer is a layer that determines the mobility of the transistor. The method of claim 1, And the threshold voltage of the transistor is determined by at least one of the lower layer and the upper layer. The method of claim 1, And a layer close to the gate of the lower layer and the upper layer includes at least one of IZO, ITO, AZO, and GZO. The method of claim 1, And a layer disposed away from the gate among the lower layer and the upper layer includes a ZnO-based oxide. The method of claim 1, And a thickness of the lower layer and the upper layer close to the gate is 10 to 500 mW. The method of claim 7, wherein And a layer having a thickness close to the gate among the lower layer and the upper layer is 30 to 200 mW. The method of claim 1, The transistor is a thin film transistor having a top-gate or bottom-gate structure. A channel layer having different carrier densities and including lower and upper layers formed of different oxides; Source and drain in contact with both ends of the channel layer, respectively; And And a gate for applying an electric field to the channel layer. The method of claim 10, And a layer closer to the gate of the lower layer and the upper layer has a higher carrier density than the layer disposed away from the gate. The method of claim 10 or 11, The lower layer and the upper layer have different mobility. The method of claim 12, And a layer closer to the gate of the lower layer and the upper layer has a higher mobility than the layer disposed farther from the gate. The method of claim 10, And a layer close to the gate of the lower layer and the upper layer is a layer that determines the mobility of the transistor. The method of claim 10, And the threshold voltage of the transistor is determined by at least one of the lower layer and the upper layer. The method of claim 10, And a layer close to the gate of the lower layer and the upper layer includes at least one of IZO, ITO, AZO, and GZO. The method of claim 10, And a layer disposed away from the gate among the lower layer and the upper layer includes a ZnO-based oxide. The method of claim 10, And a thickness of the lower layer and the upper layer close to the gate is 10 to 500 mW. The method of claim 18, And a layer having a thickness close to the gate among the lower layer and the upper layer is 30 to 200 mW. The method of claim 10, The transistor is a thin film transistor having a top-gate or bottom-gate structure.

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