CN101626032B - 半导体结构 - Google Patents
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Abstract
本发明揭示一种半导体结构,其包括:一半导体基底,具有一第一导电型;一前高电压阱区,位于半导体基底内,其中前高电压阱区具有与第一导电型相反的一第二导电型;一高电压阱区,位于前高电压阱区上方,其中高电压阱区具有第二导电型;一场环型物,具有第一导电型且占据高电压阱区的顶部;以及一隧道,具有第一导电型且位于前高电压阱区与高电压阱区内且电性连接场环型物与半导体基底。根据本发明的半导体结构,超高电压MOSFET的导通电阻可降低,且装置的击穿电压得以增加。同样也可改善超高电压MOSFET的稳定性。再者,本发明的好处在于不需使用额外的掩模。
Description
技术领域
本发明涉及一种半导体结构,特别涉及一种超高电压(ultra-high voltage,UHV)金属-氧化物-半导体场效应晶体管(metal-oxide-semiconductor fieldeffect transistor,MOSFET)。
背景技术
超高电压金属-氧化物-半导体场效应晶体管(UHV MOSFET)通常被制造成具有共平面的漏极与源极区。图1A示出公知超高电压MOSFET装置100。超高电压MOSFET装置100形成于一P型基底101上,且另一P型层113以外延生长(epitaxially grown)方式形成于P型基底101上。高电压P型阱区115与高电压N型阱区103相邻且位于外延生长的P型层113内。N型(N+)源极117位于高电压P型阱区115内,而N型(N+)漏极105位于高电压N型阱区103内。栅极介电层111与栅极电极110自N型(N+)源极117上方延伸至一部分的场氧化(field oxide)层107上方。超高电压MOSFET装置100也包括位于高电压P型阱区115内的P型(P+)捡拾(pickup)区119。在栅极电极110施加一正电压而产生一自N型(N+)源极117经过通道而进入高电压N型阱区103的电流,该电流聚集于N型(N+)漏极105。
上述类型的超高电压MOSFET的问题在于当一高电压施加于超高电压MOSFET时,无法保有低导通电阻(on-resistance)。导通电阻对于电流传导于装置时的功率转换成热有影响。装置的导通电阻较大时,装置的效率较低。因此,为了提高装置的效率,最好能够尽可能地降低此电阻。
图1B示出另一公知超高电压MOSFET装置150,用以改善上述问题。超高电压MOSFET装置150类似于图1A的超高电压MOSFET装置100,其中相同的部件使用相同标号,除了新增的场环型物109以外。环型物109用于降低表面电场以及改善漂移(drift)区的耗尽能力(depletion capability)。如此一来,相较于超高电压MOSFET装置100,漂移区的掺杂(doping)浓度得以增加,且超高电压MOSFET装置150的导通电阻得以降低。
公知超高电压MOSFET装置100(如图1A所示)以及公知超高电压MOSFET装置150(如图1B所示)的击穿电压(breakdown voltage)依旧无法另人满意。对于装置只能在低于其击穿电压下操作来说是公知的。当大于击穿电压的电压施加于装置时,例如超高电压MOSFET装置100及150,装置将发生严重且无法挽救的损害,使其毫无商业价值而必须被取代。因此,对于增加击穿电压具有高度的期待。
除了上述问题以外,公知UHV MOSFET的击穿电压并不稳定。举例而言,即使使用相同制造工艺来制造,UHV MOSFET的击穿电压可能在650伏特(volt)至800伏特的范围。使得UHV MOSFET的使用上限低于650伏特。
因此,必须寻求一种改善的超高电压MOSFET,以降低导通电阻、提高击穿电压、及改善其稳定性。
发明内容
通过本发明的实施例,上述的及其他问题可获得解决或避免其发生,且可获得技术上的优势,其利用了位于超高电压MOSFET内的一延伸漂移区,当装置处于高压时,超高电压MOSFET具有低导通电阻及高的击穿电压。
根据本发明的一形态,一种半导体结构,包括:一半导体基底,具有一第一导电型;一前高电压阱区,位于半导体基底内,其中前高电压阱区具有与第一导电型相反的一第二导电型;一高电压阱区,位于前高电压阱区上方,其中高电压阱区具有第二导电型;一场环型物,具有第一导电型且占据高电压阱区的顶部;以及一隧道,具有第一导电型且位于前高电压阱区与高电压阱区内且电性连接场环型物与半导体基底。
根据本发明的另一形态,一种半导体结构,包括:一半导体基底,具有一第一导电型;一前高电压阱区,位于半导体基底内,其中前高电压阱区具有与第一导电型相反的一第二导电型;一高电压阱区,位于前高电压阱区上方并与其接触,其中高电压阱区具有第二导电型;多个隧道,具有第一导电型且自高电压阱区的上表面延伸至前高电压阱区的下表面,其中每一隧道被前高电压阱区与高电压阱区围绕;一场环型物,位于高电压阱区内且占据高电压阱区的顶部,其中场环型物具有第一导电型;一漏极区,位于高电压阱区内;一绝缘区,位于场环型物上方;一栅极电极,位于一部分的绝缘区上方;以及一源极区,位于与栅极电极一侧的漏极区相对的一侧,其中源极区与漏极区具有第二导电型。
根据本发明的又另一形态,一种半导体结构,包括:一半导体基底,具有一第一导电型;一前高电压阱区,位于半导体基底内,其中前高电压阱区具有与第一导电型相反的一第二导电型;一高电压阱区,位于前高电压阱区上方并与其接触,其中高电压阱区具有第二导电型;场环型物,具有第一导电型,位于高电压阱区内且占据其顶部,其中前高电压阱区、高电压阱区、及场环型物各包括一直线区及一曲线区;一隧道,具有第一导电型且自高电压阱区的上表面延伸至前高电压阱区的下表面,并实际连接场环型物与半导体基底;一漏极区,位于高电压阱区内;一绝缘区,位于场环型物上方,并与其接触;一栅极电极,位于一部分的绝缘区上方;以及一源极区,位于与栅极电极一侧的漏极区相对的一侧,其中源极区与漏极区具有第二导电型。
根据本发明的又另一形态,一种半导体结构的制造方法,包括:提供一半导体基底,其具有一第一导电型;于半导体基底内形成一前高电压阱区,其中前高电压阱区具有与第一导电型相反的一第二导电型;于前高电压阱区上方形成一高电压阱区,其中高电压阱区具有第二导电型;形成具有第一导电型的一隧道,其自高电压阱区的上表面延伸至前高电压阱区的下表面;以及形成占据高电压阱区顶部的一场环型物,其中场环型物具有第一导电型且与隧道实际接触。
根据本发明的又另一形态,一种半导体结构的制造方法,包括:提供一半导体基底,其具有一第一导电型;在半导体基底上方形成一第一光致抗蚀剂层,其中第一光致抗蚀剂层包括一第一柱体覆盖一部分的半导体基底,且其中第一柱体与其他部分的第一光致抗蚀剂层实际隔开;利用第一光致抗蚀剂层对半导体基底的顶部进行注入,以形成一前高电压阱区,其中前高电压阱区具有与第一导电型相反的一第二导电型;在半导体基底与前高电压阱区上方外延生长一半导体层,以形成一外延层;在外延层上方形成一第二光致抗蚀剂层,其中第二光致抗蚀剂层包括一第二柱体覆盖一部分的外延层,且其中第二柱体与其他部分的第二光致抗蚀剂层实际隔开;且位于与第一光致抗蚀剂层的第一柱体相同的垂直位置;利用第二光致抗蚀剂层对外延层进行注入,以在前高电压阱区上方形成一高电压阱区,并与其接触,其中高电压阱区具有第二导电型;在外延层上方形成一第三光致抗蚀剂层,其中第三光致抗蚀剂层不具有隔开的柱体位于高电压阱区正上方;对高电压阱区顶部进行注入,以形成具有第二导电型的一场环型物;在场环型物及一部分的高电压阱区上方形成一绝缘区,并与其接触;在一部分的绝缘区上方形成一栅极电极;以及对外延层进行注入,以在栅极电极的相对侧形成源极及漏极。
根据上述本发明实施例,超高电压MOSFET的导通电阻可降低,且装置的击穿电压得以增加。同样也可改善超高电压MOSFET的稳定性。再者,本发明实施例好处在于不需使用额外的掩模。
附图说明
图1A是示出公知超高电压金属-氧化物-半导体场效应晶体管(MOSFET)的剖面示意图。
图1B是示出公知具有场环型物的超高电压MOSFET的剖面示意图。
图2是示出根据本发明实施例的平面示意图。
图3A至图3I是示出图2的实施例的中间制造过程,且其为沿着图2的A-A’及B-B’线的剖面示意图。
图4是示出图2的实施例的剖面示意图,且为沿着图2的C-C’线的剖面示意图。
图5是示出根据本发明另一实施例的平面示意图,其中超高电压MOSFET的漏极区为U型。
图6是示出根据本发明又另一实施例的平面示意图,其中隧道为环型。
图7是示出多个样品的击穿电压,其为本发明实施例与公知超高电压MOSFET样品比较结果。
图8是示出个别装置的击穿电压与场环型物内捕获电荷量的关系曲线图。
【主要元件符号说明】
公知
100、150~超高电压金属-氧化物-半导体场效应晶体管(UHV MOSFET)装置;101~P型基底;103~高电压N型阱区;105~N型(N+)漏极;107~场氧化层;109~场环型物;110~栅极电极;111~栅极介电层;113~P型层;115~高电压P型阱区;117~N型(N+)源极;119~P型捡拾区。
本实施例
10~超高电压金属-氧化物-半导体场效应晶体管(UHV MOSFET);20~半导体基底;24~前高电压N型阱区(前HVNW区);26、36~光致抗蚀剂层;27、37~光致抗蚀剂柱体;28~掺杂的半导体层(外延层);34~高电压N型阱区(HVNW区);40~N型阱区;42~P型阱区;44~隧道;441、442~隧道部;46~相反掺杂区(场环型物);52~场介电层(绝缘层);54~绝缘层;56~栅极介电层;58~栅极电极;60~源极区;62~漏极区;66~捡拾区;W1~宽度。
具体实施方式
以下说明本发明优选实施例制造与使用。然而,必须了解的是本发明提供许多适当的实施例的发明概念,可实施于不同的特定背景。述及的特定实施例仅用于说明以特定的方法来制造及使用本发明,而并非用以局限本发明的范围。
以下提供一种具有低导通电阻、提高击穿电压、及增加稳定性的新的高电压金属-氧化物-半导体场效应晶体管(MOSFET),并详细说明装置的制造过程。在本发明各个实施例及图式中,相同的部件使用相同的标号。
请参照图2,其示出UHV MOSFET 10的平面示意图。为了清楚起见,仅选择说明部分部件。其余的部件可参照其他剖面示意图的说明,例如图3H所示。UHV MOSFET 10包括直线区及位于直线区两端的曲线区。斜线区为部分的前高电压N型阱区(前HVNW区)24及HVNW区34(请参照图3H)。漏极区62形成于HVNW区24及HVNW区34的中心且被其所围绕。源极区60则环绕前HVNW区24及HVNW区34而构成一封闭圈。通常UHVMOSFET 10会占据一大区域,因而源极区60与漏极区62相较于UHVMOSFET 10的长度及宽度来说则较为狭窄。因此,源极区60与漏极区62仅用线条绘示之。然而,举例来说,实际上源极区60与漏极区62具有数微米的宽度。
UHV MOSFET 10包括一个或一个以上的隧道44,其构成场环型物46(请参照图3H)与半导体基底20电性连接的路径。以下将说明UHVMOSFET 10的制造以及隧道44的功能。
图3A至图3H示出图2的实施例的中间制造过程,且其为沿着图2的A-A’及B-B’线的剖面示意图。提供一半导体基底20。半导体基底20最好为包含硅并具有轻掺杂的P型杂质。然而,也可使用其他常用的半导体材料,例如SiGe。在半导体基底20的一顶部内形成一前HVNW区24且可通过在半导体基底20的顶部内注入(implanting)N型杂质而形成,例如磷。光致抗蚀剂层26则用作注入掩模(mask)。另外也可选用其他N型杂质,例如砷、锑、或其组合等等。在一实施例中,注入的剂量在1×1010/cm2至1×1016/cm2的范围。前HVNW区24的厚度最好在2微米(μm)至10微米的范围且更佳的厚度约为8.5微米。然而,可以理解的是上述列举的尺寸仅为范例说明且可随着使用不同的制造技术而作更动。在形成前HVNW区24之后,去除光致抗蚀剂层26。
在一实施例中,光致抗蚀剂层26具有前HVNW区24开口且开口内留有覆盖半导体基底20的一个或一个以上隔开的光致抗蚀剂柱体27。半导体基底20的露出部分可通过注入而转成N型,形成前HVNW区24。半导体基底20被光致抗蚀剂柱体27的部分构成隧道44的一隧道部441。
可以理解的是在后续的高温制造工艺中,注入前HVNW区24的N型杂质将会扩散至隧道部441。为了确保至少隧道部441的中心部不会因为扩散而转成N型并保有一P型路径连结前HVNW区24的顶部及底部,光致抗蚀剂柱体27最好具有大的宽度W1。在一实施例中,宽度W1大于6微米,且最好在2微米(μm)至100微米的范围。可以理解的是形成P型隧道44所需的最小宽度W1是与P型半导体基底20内的P型杂质浓度以及前HVNW区24内注入的N型杂质浓度有关。
图3B示出在半导体基底20及前HVNW区24上方形成掺杂的半导体层28。掺杂的半导体层28包括一半导体材料,例如硅,且由外延生长而成。因此,掺杂的半导体层28也另称为外延层28。掺杂的半导体层28的厚度可大于8.5微米。掺杂的半导体层28最好是在进行外延生长的同时,原位(in-situ)掺杂P型杂质。
图3B也示出使用光致抗蚀剂层36形成高电压N型阱区(HVNW区)34。HVNW区34可通过注入N型掺杂物而形成,例如磷、砷、锑等等。HVNW区34的浓度最好是大于前HVNW区24的浓度且形成的剂量在1×1010/cm2至1×1016/cm2的范围。另外,HVNW区34及前HVNW区24也可具有大体相同的杂质浓度。在一实施例中,HVNW区34的厚度最好是大体相同于外延层28的厚度,因而使HVNW区34与前HVNW区24相邻。
隧道44必须延伸进入HVNW区34。因此,光致抗蚀剂层36具有一隔开的光致抗蚀剂柱体37垂直对准于隧道部441。如此一来,隧道部442会形成于HVNW区34内。隧道部442并未直接受到注入。再者,隧道部442最好够宽,而使得在后续扩散制造工艺之后,至少隧道部442的中心部不会转成N型。形成光致抗蚀剂层36的所使用的掩模(用于定义光刻图案)最好是与形成光致抗蚀剂层26的相同。因此,隧道部442垂直对准且电性连接至隧道部441。然而,若制造工艺产生变异,隧道部441与隧道部442可能会发生误对准(misalign),但仍会局部重叠。若使用不同的掩模来形成光致抗蚀剂层26及36,也可能发生这种情形。
图3C示出N型阱区40的制造。N型阱区40最好是通过一光致抗蚀剂层(未绘示)并注入N型杂质而形成的。举例而言,其浓度大于HVNW区34的浓度。在一实施例中,注入的剂量在1×1010/cm2至1×1016/cm2的范围。N型阱区40最好具有一下表面,其高于HVNW区34的下表面。另外,N型阱区40的下表面也可切齐或低于HVNW区34的下表面。
图3D示出P型阱区42的制造。形成的P型阱区42邻近于HVNW区34。在一实施例中,P型阱区42与HVNW区34隔开,如图3D所示。再另一实施例中,P型阱区42与HVNW区34相邻而在二个阱区之间构成一接面。P型阱区42可通过一光致抗蚀剂层(未绘示)并对外延层28的所需部分注入P型杂质而形成的,例如硼、铟等等。注入的剂量在1×1010/cm2至1×1016/cm2的范围。在一实施例中,P型阱区42的深度在2微米至6微米的范围,而优选的深度约在4微米。
图3E示出以P型掺杂物对HVNW区34进行相反掺杂(counter-doping)而形成相反掺杂区46。在一实施例中,相反掺杂区46为环型(请参照图2,且相反掺杂区46构成围绕漏极区62的环型物,因而在内文说明中也另称为场环型物(field ring)46。场环型物46可通过以P型掺杂物掺杂HVNW区34的顶部至小于HVNW区34深度的一深度而形成。场环型物46的厚度需够厚,使其足以在后续形成如图3F所示的场介电层52之后,仍可在场介电层52的下方保有部分的场环型物46。场环型物46的深度在0.4微米至2微米的范围,而优选的深度约在1微米。场环型物46的底部与HVNW区34的底部隔开。场环型物46可与N型阱区40相邻或隔开。再者,场环型物46的底部与隧道44接触,使隧道44电性连接场环型物46与半导体基底20。
图3F示出绝缘层(场介电层)52形成于一部分的HVNW区34上方。另一绝缘层54可形成于部分的P型阱区42以及部分的P型外延层28的上方。绝缘层52及54可利用局部硅氧化(local oxidation of silicon,LOCOS)技术或是浅沟槽隔离(shallow trench isolation)技术而形成。
图3G示出栅极介电层56与栅极电极58的制造。栅极介电层56形成于场介电层52顶部上方并延伸覆盖一部分的P型阱区42。栅极电极58形成于栅极介电层56上方。栅极电极58为导电的,且可使用掺杂的多晶硅、金属、或金属合金等等材料。在栅极电极58包含掺杂的多晶硅的情形中,栅极电极58的表面可硅化(silicide)。
图3H示出在P型阱区42内形成源极区60以及在N型阱区40内形成漏极区62。源极区60及漏极区62可通过注入N型掺杂物而形成,例如磷,且浓度在1×1019/cm3至2×1020/cm3的范围。捡拾(pickup)区66为P型,其形成于P型阱区42内且浓度在1×1019/cm3至2×1020/cm3的范围。
图3H所示的结构将受到具有热预算的种种步骤。举例而言,可在图3E及图3F中的步骤之间实施一阱区驱入(drive-in)制造工艺(具有一高温,例如,1000℃)。再者,集成电路制造工艺及封装制造工艺包含其他高温步骤。因此,直接注入区24及34内的杂质将会分别扩散到隧道部441及442。在历经集成电路制造工艺及封装制造工艺中的所有热预算之后,最终结构类似于图3G所示,除了隧道的直径因其外侧部转成N型而缩小以外。而隧道44的内侧部维持P型。
图3I示出本发明另一实施例。在本实施例中,初始步骤类似于图3A至图3E所示,除了没有隧道44形成于前HVNW区24与HVNW区34内以外。在形成如图3E所示的结构之后,形成一光致抗蚀剂层(未绘示),其具有一开口而露出部分的场环型物46。实施注入以形成穿过开口的P型隧道44。隧道44自场环型物46的上表面延伸至前HVNW区24的下表面,如图3I所示。在此种情形中,场环型物46内的隧道44部分的P型杂质浓度高于余留的场环型物46内P型杂质浓度。为了确保场环型物46与半导体基底20之间没有断点,注入程序包含数个不同能量的注入。隧道44的底部最好低于前HVNW区24的底部以存在容许限度。在形成隧道44之后,可实施图3F至图3G的步骤,以完成UHV MOSFET 10的制造。
图4是示出图2中UHV MOSFET 10的另一实施例的剖面示意图,且为沿着图2的C-C’线的剖面示意图。没有出现隧道。
UHV MOSFET 10最好是包含一个以上的隧道44,如图2所示。所需的隧道44数量取决于UHV MOSFET 10的尺寸,且较大的UHV MOSFET 10尺寸最好是具有较多的隧道。隧道44的分布最好是均匀地跨过场环型物46。隧道44的上视形状包括方形、矩形、圆形、或八边形等等。本发明实施例可应用于具有其他形状的MOSFET中。举例而言,图5示出另一类型的UHVMOSFET 10,其漏极区62为U型,且对应的UHV MOSFET 10具有马蹄铁型。此装置类似于弯折图2所示的装置,直到漏极区62的两端彼此平行。再者,形成的P型隧道44用以连接场环型物46及半导体基底20(未绘示于图5,其剖面示意图实质相同于图3H/3I及图4所示)。
图6示出另一UHV MOSFET 10,其包括源极区60及漏极区62。漏极区62及源极区60两者在末端构成弧型。在本实施例中,形成的P型隧道44用以连接场环型物46及半导体基底20(未绘示,剖面图实质相同于图3G及图4所示)。须注意的是隧道44可形成于具有任何其他外型的任何其他类型的MOSFET内,即使击穿电压仅小于100伏特,例如,公知的矩型高电压MOSFET。
图7是示出本发明实施例与公知超高电压MOSFET效能比较的实验结果。有两组样品进行测试。第一组样品的结构绘示于图3H中,同时第二组样品的结构类似于图3H所示,除了没有形成隧道44以外。X轴表示样品的数量,而Y轴表示样品的击穿电压。须注意的是第一组样品(以圆圈示之)的击穿电压稳定大于800伏特,而第二组样品(以方块示之)的击穿电压则在650伏特至800伏特的广泛范围。
本发明实施例的UHV MOSFET的击穿电压改善机制并不清楚。其中一个可能的解释是由于超高电压施加于MOSFET时,通过高能量的作用而造成原子具有高离子化速率(ionization rate)。此种情形造成场环型物46内产生超额电荷。然而,由于公知UHV MOSFET的场环型物因背对背式二极体形成于场环型物与半导体基底之间而电性浮接(floating),超额电荷无法放电,因而导致UHV MOSFET的效能降低。而P型隧道44电性连接场环型物46与P型半导体基底20,使超额电荷得以放电。图8是示出确认超额电荷影响的模拟结果,其中模拟UHV MOSFET的驱动电流Id为漏极对源极电压的一函数。在此模拟中不同总量的超额电荷注入场环型物内,并模拟出个别UHV MOSFET的I-V曲线。需注意的是击穿电压随着场环型物46内电荷总量的增加而降低,因而证实超额电荷的不良影响。
任何所属技术领域中具有通常知识者可以理解此处范例说明仅为本发明的实施例。举例而言,虽然所述的实施例为N型UHV MOSFET,在其他实施例中也可以是P型UHV MOSFET,而其中源极/漏极区、高电压阱区、前高电压阱区、阱区、基底、及隧道等等的导电型则对应转换。
虽然本发明已以优选实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中的普通技术人员,在不脱离本发明的精神和范围内,当可作更动与润饰。举例而言,构成结构的材料,其沉积方法有很多种,任何能够与此处所述实施例获得大体相同结果的沉积方法都可使用于本发明中。
再者,本发明的保护范围并未局限于说明书内所述方法的特定实施例,任何所属技术领域中的普通技术人员可从本发明揭示内容中理解用以在此处所述实施例中实施大体相同功能或获得大体相同结果的现行方法或未来所发展出的方法都可使用于本发明中。因此,本发明的保护范围当视随附的权利要求所界定的范围为准。
Claims (9)
1.一种超高压金属-氧化物-半导体场效应晶体管,包括:
一半导体基底,具有一第一导电型;
一前高电压阱区,位于该半导体基底内,其中该前高电压阱区具有与该第一导电型相反的一第二导电型;
一高电压阱区,位于该前高电压阱区上方,其中该高电压阱区具有该第二导电型;
一场环型物,具有该第一导电型且占据该高电压阱区的顶部;
一隧道,具有该第一导电型且位于该前高电压阱区与该高电压阱区内且电性连接该场环型物与该半导体基底,
一绝缘区,位于该场环型物及一部分的该高电压阱区上方,并与其接触;
一漏极区,位于该高电压阱区内,且与该绝缘区相邻;
一栅极电极,位于一部分的该绝缘区上方;以及
一源极区,位于与该栅极电极一侧的该漏极区相对的一侧。
2.如权利要求1所述的超高压金属-氧化物-半导体场效应晶体管,其中该场环型物构成围绕该漏极区的环型物,该场环型物包括直线区与曲线区。
3.如权利要求1所述的超高压金属-氧化物-半导体场效应晶体管,其中该隧道延伸至该场环型物的上表面,该场环型物内的该隧道的一部分具有一第一导电型杂质浓度且高于该场环型物内的一第一导电型杂质浓度。
4.一种超高压金属-氧化物-半导体场效应晶体管,包括:
一半导体基底,具有一第一导电型;
一前高电压阱区,位于该半导体基底内,其中该前高电压阱区具有与该第一导电型相反的一第二导电型;
一高电压阱区,位于该前高电压阱区上方并与其接触,其中该高电压阱区具有该第二导电型;
多个隧道,具有该第一导电型且自该高电压阱区的上表面延伸至该前高电压阱区的下表面,其中每一隧道被该前高电压阱区与该高电压阱区围绕;
一场环型物,位于该高电压阱区内且占据该高电压阱区的顶部,其中该场环型物具有该第一导电型;
一漏极区,位于该高电压阱区内;
一绝缘区,位于该场环型物上方;
一栅极电极,位于一部分的该绝缘区上方;以及
一源极区,位于与该栅极电极一侧的该漏极区相对的一侧,其中该源极区与该漏极区具有该第二导电型。
5.如权利要求4所述的超高压金属-氧化物-半导体场效应晶体管,其中所述多个隧道位于该场环型物下方,且电性连接该场环型物与该半导体基底。
6.如权利要求4所述的超高压金属-氧化物-半导体场效应晶体管,其中所述多个隧道延伸穿过该场环型物至该场环型物的上表面,该场环型物内部分的所述多个隧道具有一第一导电型杂质浓度且高于该场环型物内的一第一导电型杂质浓度。
7.一种超高压金属-氧化物-半导体场效应晶体管,包括:
一半导体基底,具有一第一导电型;
一前高电压阱区,位于该半导体基底内,其中该前高电压阱区具有与该一导电型相反的一第二导电型;
一高电压阱区,位于该前高电压阱区上方并与其接触,其中该高电压阱区具有该第二导电型;
一场环型物,具有该第一导电型,位于该高电压阱区内且占据其顶部,其中该前高电压阱区、该高电压阱区、及该场环型物各包括一直线区及一曲线区;
一隧道,具有该第一导电型且自该高电压阱区的上表面延伸至该前高电压阱区的下表面,并实际连接该场环型物与该半导体基底;
一漏极区,位于该高电压阱区内;
一绝缘区,位于该场环型物上方,并与其接触;
一栅极电极,位于一部分的该绝缘区上方;以及
一源极区,位于与该栅极电极一侧的该漏极区相对的一侧,其中该源极区与该漏极区具有该第二导电型。
8.如权利要求7所述的超高压金属-氧化物-半导体场效应晶体管,其中该隧道位于该前高电压阱区的该曲线区内与该高电压阱区的该曲线区内。
9.如权利要求7所述的超高压金属-氧化物-半导体场效应晶体管,其中该隧道位于该前高电压阱区的该直线区与该高电压阱区的该直线区的其中一个内。
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US7989890B2 (en) * | 2006-10-13 | 2011-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral power MOSFET with high breakdown voltage and low on-resistance |
US7960786B2 (en) | 2008-07-09 | 2011-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Breakdown voltages of ultra-high voltage devices by forming tunnels |
US8378422B2 (en) * | 2009-02-06 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection device comprising a plurality of highly doped areas within a well |
US8319255B2 (en) * | 2010-04-01 | 2012-11-27 | Texas Instruments Incorporated | Low side Zener reference voltage extended drain SCR clamps |
TWI501374B (zh) * | 2011-05-17 | 2015-09-21 | Richtek Technology Corp | 超高壓元件構造之改良 |
CN102903752B (zh) * | 2011-07-27 | 2015-03-25 | 立锜科技股份有限公司 | 高压元件及其制造方法 |
TWI500139B (zh) * | 2012-05-25 | 2015-09-11 | Richtek Technology Corp | 混和高壓元件及其製造方法 |
US9698024B2 (en) | 2012-12-06 | 2017-07-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Partial SOI on power device for breakdown voltage improvement |
US8779555B2 (en) * | 2012-12-06 | 2014-07-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Partial SOI on power device for breakdown voltage improvement |
US9240463B2 (en) | 2013-05-24 | 2016-01-19 | Globalfoundries Inc. | High voltage laterally diffused metal oxide semiconductor |
US9236449B2 (en) | 2013-07-11 | 2016-01-12 | Globalfoundries Inc. | High voltage laterally diffused metal oxide semiconductor |
US9299832B2 (en) * | 2013-12-17 | 2016-03-29 | Texas Instruments Incorporated | High voltage lateral DMOS transistor with optimized source-side blocking capability |
US9070766B1 (en) * | 2014-01-27 | 2015-06-30 | Macronix International Co., Ltd. | Semiconductor device and method of forming the same |
TWI719747B (zh) * | 2019-12-10 | 2021-02-21 | 新唐科技股份有限公司 | 半導體裝置結構及其製造方法 |
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US7893490B2 (en) * | 2007-04-30 | 2011-02-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | HVNMOS structure for reducing on-resistance and preventing BJT triggering |
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