CN101552239B - 制造半导体器件的方法 - Google Patents

制造半导体器件的方法 Download PDF

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CN101552239B
CN101552239B CN2009101326110A CN200910132611A CN101552239B CN 101552239 B CN101552239 B CN 101552239B CN 2009101326110 A CN2009101326110 A CN 2009101326110A CN 200910132611 A CN200910132611 A CN 200910132611A CN 101552239 B CN101552239 B CN 101552239B
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conductive layer
etching
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朴相勋
曹允硕
曹祥薰
李春熙
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SK Hynix Inc
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Abstract

本发明涉及制造半导体器件的方法。在制造具有垂直沟道的半导体器件的方法及图案化该半导体器件的栅电极的方法中，通过多个蚀刻工艺来移除初始导电层。

Description

制造半导体器件的方法
相关申请
本发明要求2008年4月4日申请的韩国专利申请No.10-2008-0031477的优先权，其全文通过引用的方式并入本文中。
技术领域
本发明内容涉及制造半导体器件的方法，且更具体涉及制造具有从顶部至底部方向上形成的沟道(在本文中称为垂直沟道)的半导体器件的方法。
背景技术
为减小尺寸，通过将源极区和漏极区布置在有源区的上部和下部中而将半导体器件设计成具有垂直沟道。
图1A和图1B为描述发明者已知的能够制造具有垂直沟道的半导体器件的方法的示意性横截面图。
如图1A中所示，在衬底11上形成多个栅极硬掩模图案12，且使用所述多个栅极硬掩模图案作为蚀刻阻挡或掩模而形成柱状物头13。接着，在每一个柱状物头13和相应栅极硬掩模图案12的侧壁上形成侧壁钝化层14，通过使用侧壁钝化层14作为蚀刻阻挡或掩模来各向同性地蚀刻衬底11形成柱状物颈15。柱状物颈15与柱状物头13一起限定柱状物图案。
接着，在柱状物头13的一部分以及柱状物颈15上形成栅极绝缘层16，并沿着衬底的轮廓沉积导电层17。
如图1B中所示，通过各向异性地蚀刻导电层17而形成栅电极17A以围绕柱状物颈15。
在已知的制造方法中，在导电层17的各向异性蚀刻期间，衬底11可能会部分损失，如图1B的圆圈18中所示。衬底11的潜在损失使所制造的半导体器件的操作特性劣化。
具体地，实施导电层17的各向异性蚀刻，直至形成在柱状物头13的侧壁处的侧壁钝化层14暴露为止。因此，潜在地，沉积在相邻柱状物图案之间的导电层17可能被过度蚀刻。因此，如图1B的圆圈18中所示，衬底11的一部分可能会无意中损失。
尽管可将具有极佳选择性的蚀刻配方(etching recipe)用于导电层17的各向异性蚀刻，但因为选择性并非无限的，所以仍存在限制。
发明内容
根据一个或多个实施方案，一种在衬底上制造半导体器件的方法包括：在衬底上形成具有柱状物头和柱状物颈的至少一个柱状物图案；形成围绕柱状物颈的栅极绝缘层；在其中柱状物颈上具有栅极绝缘层的衬底上方形成导电层；和通过对导电层实施多个蚀刻工艺而形成围绕柱状物颈上的栅极绝缘层的栅电极。
根据一个或多个实施方案，一种由沉积在衬底上的导电层形成栅电极的方法(在衬底上具有包括柱状物头、柱状物颈的至少一个柱状物图案以及围绕柱状物颈的栅极绝缘层)包括：对导电层依次实施多个不同蚀刻工艺以形成围绕柱状物颈上的栅极绝缘层的栅电极；其中所述多个蚀刻工艺中的每一个均部分地移除导电层的厚度，以减小过度蚀刻衬底和/或栅极绝缘层的可能性。
附图说明
通过举例而非限制地结合附图说明各种实施方案，其中相同的附图标记表示相同的元件。
图1A及图1B为描述制造具有垂直沟道的半导体器件的已知方法的示意横截面图。
图2A至图2F为说明根据一些实施方案的制造具有垂直沟道的半导体器件的方法的示意横截面图。
具体实施方式
如图2A中所示，在衬底21上形成多个栅极硬掩模图案22，通过使用所述多个栅极硬掩模图案22作为蚀刻阻挡或掩模来蚀刻衬底21而形成柱状物头23。
在一些实施方案中，栅极硬掩模图案22由氮化物层(具体地，氮化硅层)制成。
在各栅极硬掩模图案22和柱状物头23的侧壁上形成侧壁钝化层24，通过使用侧壁钝化层24作为蚀刻阻挡或掩模来各向异性地蚀刻衬底21而形成柱状物颈25。
通过在沿着具有柱状物头23的衬底的轮廓沉积氮化物层之后实施回蚀工艺而形成侧壁钝化层24。
在下文中，将柱状物头23与相应柱状物颈25一起称为柱状物图案。柱状物图案为有源区。
接着，形成栅极绝缘层26以至少围绕柱状物颈25。
在具有柱状物图案和形成于其上的栅极绝缘层26的衬底上形成导电层27。
在一些实施方案中，导电层27由至少多晶硅层和/或至少金属层形成。用于导电层27的金属层包括选自钨(W)、钴(Co)、镍(Ni)、氮化钛层(TiN)和钛(Ti)中的至少一种。例如，在一个实施方案中，导电层27包括钛层和氮化钛层的堆叠结构。
接着，在具有导电层27的衬底的整个上表面上形成牺牲层28。
牺牲层28在后续工艺中保护栅极绝缘层26和在柱状物图案之间的衬底21。可使用完全填充相邻柱状物图案之间的间隙的绝缘层作为牺牲层28。例如，在一些实施方案中，牺牲层28可以是通过旋涂沉积的旋涂介电层。
如图2B中所示，通过部分地移除牺牲层28的一部分而形成牺牲图案28A。因此，形成在栅极硬掩模图案22的顶壁以及柱状物头23和栅极硬掩模图案22的侧壁上的导电层27的一部分被暴露。
在一些实施方案例中，实施各向同性蚀刻工艺以部分地移除牺牲层28。在一些实施方案中，将蚀刻目标设定为高于柱状物头23与柱状物颈25之间的边界来实施各向同性蚀刻工艺。即，在各向同性蚀刻工艺之后的牺牲层图案28A的顶表面保持为高于柱状物头23与柱状物颈25之间的边界。
如图2C中所示，在一些实施方案中，通过实施各向同性蚀刻工艺来移除导电层27的暴露部分。在各向同性蚀刻工艺期间，形成在柱状物颈25的侧壁上的导电层27受牺牲层28保护，因此仅蚀刻形成在牺牲层图案28A的顶表面上的导电层27的暴露部分。结果，获得一次蚀刻的导电层27A。
如图2D中所示，在一些实施方案中，通过使用侧壁钝化层24作为蚀刻阻挡或掩模来实施各向异性蚀刻工艺，以部分地移除位于柱状物头23与柱状物颈25之间的边界处的经一次蚀刻的导电层27A。在一些实施方案中，选择蚀刻配方，以使导电层27和牺牲层图案28A的相邻部分比在相邻柱状物图案之间的牺牲层图案28A的中心部分更快地受到蚀刻。因此，经一次蚀刻的导电层27A变成经两次蚀刻的导电层27B，导电层27B具有在柱状物头23与柱状物颈25之间的边界处的垂直轮廓。
如图2E中所示，首先在具有经两次蚀刻的导电层27B的衬底上沉积绝缘层，接着通过实施各向异性蚀刻工艺而将绝缘层形成为具有间隔物形状(spacer shape)的钝化层29。
钝化层29为由氮化物层制成的薄膜，其增强侧壁钝化层24以防止柱状物图案在随后工艺中暴露。
接着，在一些实施方案中，通过湿蚀刻移除牺牲层28A。
如图2F中所示，通过使用钝化层29作为蚀刻阻挡或掩模来各向异性地蚀刻经两次蚀刻的导电层27B，而形成栅电极27C以围绕柱状物颈25。在一些实施方案中，随后废弃或以其它方式移除钝化层29。因此，栅电极27C具有垂直侧壁。
由于栅电极27C在从栅极硬掩模图案22和柱状物头23的侧壁蚀刻导电层27(如图2C及图2D所示)之后形成，因此由于蚀刻目标的降低，防止了栅极绝缘层26和衬底21的潜在损失。
在所公开的实施方案中，通过在多个步骤中图案化导电层27而形成栅电极27C。由于将导电层27的所要蚀刻目标分为若干较小蚀刻目标(例如，如在图2F中30、31及32所指示)，因此与当利用一个大的蚀刻目标40实施单蚀刻工艺时相比，可防止栅极绝缘层26和衬底21的潜在损伤。在一些实施方案中，对导电层27实施的多个蚀刻工艺不仅包括至少各向同性蚀刻工艺，还包括至少各向异性蚀刻工艺。
此处，附图标记30表示图2C的蚀刻工艺的蚀刻目标，附图标记31表示图2D的蚀刻工艺的蚀刻目标，附图标记32表示图2F的蚀刻工艺的蚀刻目标。
上述的制造半导体器件的方法可防止或至少减小栅极绝缘层和衬底在形成栅电极的过程中的潜在损失。
因此，半导体器件的稳定性和可靠性可得到改善，且制造良品率亦可得到改善。
尽管已描述了各种实施方案，但对本领域技术人员而言显而易见的是，可做出各种改变和修改。

Claims (14)

1.一种在衬底上制造半导体器件的方法，所述方法包括：
在所述衬底上形成具有柱状物头和柱状物颈的至少一个柱状物图案；
形成围绕所述柱状物颈的栅极绝缘层；
在其中所述柱状物颈上具有所述栅极绝缘层的衬底上形成导电层；和
通过对所述导电层实施多个蚀刻工艺而形成围绕位于所述柱状物颈上的所述栅极绝缘层的栅电极，
其中对所述导电层实施的所述多个蚀刻工艺包括：
对由部分填充相邻柱状物图案之间间隙的牺牲层图案所暴露的所述导电层的部分实施的各向同性蚀刻工艺；
对已经各向同性蚀刻的导电层和所述牺牲层图案的一部分实施的第一各向异性蚀刻工艺，以获得经一次各向异性蚀刻的导电层和经各向异性蚀刻的牺牲层图案；和
在将所述经各向异性蚀刻的牺牲层图案移除之后对所述经一次各向异性蚀刻的导电层实施用以获得所述栅电极的第二各向异性蚀刻工艺。
2.根据权利要求1的方法，其中限定所述导电层的所述暴露部分的所述牺牲层图案的顶表面高于所述柱状物颈与所述柱状物头之间的边界。
3.根据权利要求1的方法，还包括：
在所述经一次各向异性蚀刻的导电层的侧壁上和在所述各向同性蚀刻工艺和所述第一各向异性蚀刻工艺之后暴露的所述柱状物头的侧壁上形成呈间隔物形状的钝化层。
4.根据权利要求3的方法，其中所述钝化层包括氮化物层。
5.根据权利要求1的方法，其中通过湿蚀刻来移除所述经各向异性蚀刻的牺牲层图案。
6.根据权利要求2的方法，其中通过以下步骤形成所述牺牲层图案：
沉积牺牲层以填充所述相邻柱状物图案之间的所述间隙；和
部分移除所述牺牲层以获得所述牺牲层图案。
7.根据权利要求2的方法，其中将所述第一各向异性蚀刻工艺的蚀刻目标设定为低于所述柱状物头与所述柱状物颈之间的所述边界。
8.根据权利要求2的方法，其中选择所述第一各向异性蚀刻工艺的蚀刻配方，以使得所述经各向同性蚀刻的导电层和所述牺牲层图案的相邻部分比在所述相邻柱状物图案之间的所述牺牲层图案的中心部分更快地受到蚀刻。
9.一种由沉积在衬底上的导电层形成栅电极的方法，所述衬底在其上具有包括柱状物头、柱状物颈的至少一个柱状物图案以及围绕所述柱状物颈的栅极绝缘层，所述方法包括：
形成部分填充相邻柱状物图案之间间隙的牺牲层图案；
对所述导电层依次实施多个不同蚀刻工艺以形成围绕位于所述柱状物颈上的所述栅极绝缘层的所述栅电极；
其中所述多个蚀刻工艺中的每一个均部分地移除所述导电层的厚度，以减小过度蚀刻所述衬底和/或所述栅极绝缘层的可能性；和
其中对所述导电层实施的所述多个蚀刻工艺包括各向同性蚀刻工艺、第一各向异性蚀刻工艺和第二各向异性蚀刻工艺，
其中所述各向同性蚀刻工艺从所述柱状物头上方开始移除所述导电层直到第一蚀刻目标，所述第一蚀刻目标高于所述柱状物颈与所述柱状物头之间的边界；
第一各向异性蚀刻工艺从所述第一蚀刻目标开始移除所述经各向同性蚀刻的导电层直到所述边界，从所述边界开始部分地移除所述经各向同性蚀刻的导电层的侧面部分直到第二蚀刻目标；和移除所述牺牲层图案的一部分以获得所述经一次各向异性蚀刻的导电层和所述经各向异性蚀刻的牺牲层图案；和
第二各向异性蚀刻工艺部分地移除低于所述第二蚀刻目标但不在所述柱状物头下方的所述经各向异性蚀刻的导电层。
10.根据权利要求9的方法，
其中所述牺牲层图案的顶表面限定所述第一蚀刻目标，且在所述各向同性蚀刻工艺期间移除在所述牺牲层图案的所述顶表面以上所暴露的所述导电层的部分。
11.根据权利要求9的方法，其中在所述第一各向异性蚀刻工艺期间，所述导电层蚀刻得比所述牺牲层图案快。
12.根据权利要求10的方法，还包括
在所述第一各向异性蚀刻工艺之后且在所述第二各向性蚀刻工艺之前，移除所述牺牲层图案。
13.根据权利要求12的方法，还包括
在移除所述牺牲层图案之后，在所述第一各向异性蚀刻目标以上的所述导电层和所述柱状物头的侧壁上形成呈间隔物形状的钝化层；
其中在所述第二各向异性蚀刻工艺期间，使用所述钝化层作为蚀刻阻挡或掩模。
14.根据权利要求10的方法，其中通过以下步骤形成所述牺牲层图案：
沉积牺牲层以填充所述相邻柱状物图案之间的所述间隙；和
部分地移除所述牺牲层直至所述第一蚀刻目标以获得所述牺牲层图案。
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