CN101546742B - 半导体器件的安装结构体及使用安装结构体的电子设备 - Google Patents

半导体器件的安装结构体及使用安装结构体的电子设备 Download PDF

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CN101546742B
CN101546742B CN2009101298479A CN200910129847A CN101546742B CN 101546742 B CN101546742 B CN 101546742B CN 2009101298479 A CN2009101298479 A CN 2009101298479A CN 200910129847 A CN200910129847 A CN 200910129847A CN 101546742 B CN101546742 B CN 101546742B
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semiconductor device
circuit board
supporter
flexible circuit
assembling structure
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CN101546742A (zh
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渡边真司
山崎隆雄
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NEC Corp
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Abstract

提供一种半导体器件的安装结构体及使用安装结构体的低成本的电子设备,该安装结构体具有良好的平坦度,成品率高,并且能够层叠为低成本的封装堆栈型,所述电子设备通过适用本安装结构体,实现高功能化及小型化。在安装结构体(60)中,半导体器件(50)下表面的焊锡凸点(5)熔融连接在挠性布线基板(7)的电极上,挠性布线基板(7)包覆半导体器件(50),从而与半导体器件(50)的侧面的一部分及上表面的一部分粘接固定,在半导体器件(50)的上表面形成有电极,并且在半导体器件(50)的下表面或侧面与挠性布线基板(7)之间的至少一部分包含有支撑体(90)。

Description

半导体器件的安装结构体及使用安装结构体的电子设备
技术领域
本发明涉及一种半导体器件的安装结构体,尤其涉及将多个半导体器件安装结构体层叠而安装的三维安装型的安装结构体。并且涉及使用这些安装结构体的电子设备。
背景技术
随着电子设备的高功能化,带来部件的增加,设备的小型化及薄型化的发展,随之半导体器件也要求小型化、薄型化。其中,作为适用于具有小型化要求的移动设备上的半导体器件,例如可以列举如专利文献1中记载的被称为BGA(Ball Grid Array,球栅阵列)或CSP(Chip Size Package,芯片尺寸封装)的封装的底面作为连接端子将焊锡球配置成格子状的如图7所示的封装,因其占据区域窄,能够配置更多端子,因此被广泛使用。在图7中,110是半导体装置,112是基板,114是半导体芯片,116是凸点,118是结构物,120是粘接剂,122是底层树脂,124是凸球,126是凹陷部,128是间隙。
近几年,进一步开发了在一个半导体器件中内置多个半导体芯片的芯片堆栈型的半导体器件,其特别在移动设备中,成为必须的封装。
另外,在半导体器件上内置多个芯片时,在半导体芯片不是进行过充分检查的合格的半导体芯片的情况下,或在组合了不能确保高成品率的半导体芯片的情况下,封装后的成品率急剧恶化,因此高成本成为问题。
并且,在组合的半导体芯片由其他公司供货的情况下,由于半导体芯片的状态很难得到与半导体器件同等的质量保证,所以无法期望高成品率,并且有必要实施用于品质保证的单独检查,从而有必要进行检查设备的引进、检查程序的开发等,因此成为成本增加的主要原因。
因此,如图8所示,本申请人提出了一种封装堆栈型半导体器件,其将半导体芯片分别进行封装化,将这些封装分别检查后层叠(专利文献2)。在图8中,101是半导体芯片,102是热塑性树脂,103是绝缘性树脂,104是导体,105是电极垫,106是平板,108是焊锡凸点,109是主板,110是布线图案,111是软质内插基板。
专利文献1:日本专利第3395164号公报
专利文献2:日本特开2004-146751号公报
但是,即使在这种情况下,也不能解决半导体芯片由其他公司供货时无法得到与半导体器件同等的质量保证的问题,因此半导体芯片的可用性、低成本化的问题依然存在。
因此,不将引起高成本的半导体芯片构成为能够以封装的状态层叠的封装,而将普通的半导体器件、质量有保障的市场上出售的半导体封装作为“能够层叠封装的封装(安装结构体)”而重构(Reconstruction)。但是根据本发明人们的观点,在外部端子采用焊锡凸点的半导体器件中,存在很难确保焊锡凸点所需的平坦度的问题。
此外,作为用于解决该问题的一个方法,申请人在2007年9月19日申请的日本特愿2007-242396中,提出了一种挠性电路基板在最外部焊锡球的外侧区域弯曲的半导体器件。
发明内容
在本发明的第1方面,一种安装结构体,将在下表面具有焊锡凸点作为外部端子的一个或多个半导体器件用形成有布线的具有挠性的布线基板包覆,并且在半导体器件的外部端子形成面一侧及外部端子形成面一侧的表背相反面一侧这两侧具有外部电极,安装结构体的特征在于,在挠性布线基板上形成有至少一层布线层,在半导体器件的外部端子形成面和挠性布线基板之间将支撑体粘接固定而配置。
优选的是,所述半导体器件的外部端子形成面的表背相反面的至少一部分,与挠性布线基板粘接固定。
并且,优选的是,所述半导体器件的侧面的至少一部分与挠性布线基板粘接固定。
并且,优选的是,支撑体的外形尺寸是与半导体器件的外形尺寸相同的尺寸,或是在半导体器件的外形尺寸以下的尺寸,并且在支撑体上至少在外部端子的位置设有贯通孔,以使支撑体与半导体器件的外部端子不接触。
并且,可以在半导体器件中外部端子形成面的周边外端部的全部区域或局部配置支撑体。即,也可以将支撑体分割配置,以能将焊锡凸点的高度限制在一定范围内。在这里外部端子形成面的周边外端部是指外部端子形成面中比外部端子中最外侧的端子更靠外侧的范围。
并且,优选的是,在挠性布线基板上没有配置用于与半导体器件粘接的粘接层时,支撑体的厚度,与在没有支撑体的情况下通过回流法将半导体器件与挠性布线基板熔融接合的状态下的、焊锡凸点的高度相同,或稍大于该高度,在挠性布线基板上配置有用于与半导体器件粘接的粘接层时,支撑体的厚度与从焊锡凸点的高度减去该粘接层的厚度后的长度相同,或稍大于该长度。由此,挠性布线基板不会给焊锡凸点不必要的压力,在将焊锡凸点回流连接的情况下能使焊锡凸点的高度在一定范围内一致。
并且,优选的是,支撑体上,在支撑体的外周端的至少一部分设有竖起部,竖起部在半导体器件的侧面和挠性布线基板之间从支撑体的外周端朝向直角方向竖起。支撑体的外周端是指支撑体的最靠外侧的部分。
并且,优选的是,半导体器件的侧面的至少一部分和半导体器件的下表面的至少一部分这两部分与支撑体接触而固定。
并且,优选的是,半导体器件的侧面的至少一部分和半导体器件的下表面的至少一部分这两部分与支撑体夹着粘接材料粘接固定。
并且,优选的是,支撑体的竖起部的至少一部分与挠性布线基板粘接固定。
并且,优选的是,支撑体具有与挠性布线基板的热膨胀系数相同或者在挠性布线基板的热膨胀系数以下的热膨胀系数。
并且,优选的是,支撑体用粘接剂与挠性布线基板及半导体器件中的至少一方粘接固定。
该粘接剂可以为导电性粘接剂。
并且,优选的是,支撑体由具有导电性的材料构成,并且挠性布线基板的接地图案和支撑体通过导电性凸点电连接。
并且,优选的是,与弯曲挠性布线基板的位置相应的、支撑体的最外周角部,被去掉角而成为C倒角或圆弧形的形状。
并且,优选的是,在挠性布线基板上形成有至少1层粘接层,半导体器件和挠性布线基板的至少一部分通过粘接层粘接固定。
粘接层可以是热塑性树脂。
粘接层可以是热固化前的热固性树脂。
本发明第2方面的层叠型半导体器件,其特征在于,包括上述安装结构体。
优选的是,上述层叠型半导体器件,还安装有无源部件。
本发明第3方面的电子设备,其特征在于,包括上述层叠型半导体器件。
根据本发明,能够提供一种具有良好平坦度的高成品率的安装结构体,并且能够提供一种低成本的封装堆栈型的安装结构体,进而能够提供一种通过适用本安装结构体而实现高功能化及小型化的低成本电子设备。
附图说明
图1是本发明实施例1中的安装结构体的概略剖视图及制造方法。
图2是挠性布线基板与半导体器件的侧面不粘接时的安装结构体的概略剖视图。
图3是本发明实施例2中的安装结构体的概略剖视图。
图4是本发明实施例3中的安装结构体的概略剖视图。
图5是本发明实施例4中的安装结构体的概略(局部)剖视图。
图6是本发明实施例5中的安装结构体的概略剖视图。
图7是现有的半导体器件的第1例的概略剖视图。
图8是现有的半导体器件的第2例的概略剖视图及制造方法。
图9是没有使用本发明所涉及的结构而重构的半导体器件的概略剖视图及制造方法。
具体实施方式
在说明本发明所涉及的安装结构体之前,对发明者所经历的问题进行说明。在将普通的半导体器件、质量有保障的市面上销售的半导体器件,作为“能够层叠封装的封装(安装结构体)”重构的情况下,会发生如图9所示的状况。
图9(a)是在适合高密度安装的外部端子上采用焊锡凸点的普通CSP封装(半导体器件)的剖视图。半导体芯片1安装在布线基板3上,半导体芯片1的电极与布线基板3的布线图案通过引线接合法,用接合线2进行电连接。进而,以将这些用模具树脂4覆盖而封合。在布线基板3的安装有半导体芯片1的面相反侧的面上,作为用于与安装半导体器件的布线基板连接的外部端子,形成有焊锡凸点5。
图9(b)、图9(c)、图9(d)表示能够层叠封装的半导体器件(安装结构体)的结构剖面及其制造流程,所述半导体器件,为了能够将在外部端子上具有焊锡凸点5的普通的半导体器件(半导体器件)以三维方式层叠,通过具有将半导体器件下表面的电极与上表面的电极电连接的布线图案的挠性布线基板7,包覆半导体器件而重构。
图9(b)是在具有布线图案的挠性布线基板7上将半导体器件通过回流法等普通的安装方法安装之后的剖视图。在挠性布线基板7的半导体器件安装面上,以将半导体器件与布线基板粘接固定为目的,形成热塑性树脂6。
图9(c)是将半导体器件用挠性布线基板7包覆并粘接固定而重构的半导体器件的剖视图。在室温下,焊锡为固体,因此焊锡凸点5的高度保持着半导体器件安装在挠性布线基板7上时的状态。另一方面,在挠性布线基板7上,由于包覆半导体器件而与焊锡凸点5连接的部位,会残留左右方向的拉伸应力。
图9(d)是通过回流法将用于连接其他布线基板的焊锡凸点8安装后的重构的半导体器件的剖视图。在形成焊锡凸点8时,由于在半导体器件整体上施加了熔点以上的温度,因此焊锡凸点5也会熔融,残留在挠性布线基板7上的拉伸应力会被释放。因此,挠性布线基板7成为弯曲的状态,即使焊锡凸点5处于固化的状态,也会保持弯曲的状态。因此,所有的焊锡凸点8难以接触同一平面(绝对平面)。
其中,例如在形成焊锡凸点8时,即使通过局部加热而在焊锡凸点5没有熔融的状态下形成的情况下,在将本半导体器件安装在其他安装基板上时,由于施加由回流产生的热负荷,结果焊锡凸点5也会熔融,导致挠性布线基板7产生弯曲。
即,将该半导体器件安装在其他布线基板上时的最大问题在于,由挠性布线基板7的弯曲所产生的焊锡凸点8的平坦度。在一般情况下,公知的是,在焊锡凸点的平坦度超过0.08mm时,会发生焊接不良,而半导体器件的焊锡凸点的平坦度的标准在0.08mm以下。因此,如该半导体器件,若挠性布线基板7为弯曲的结构,则难以保证0.08mm以下的平坦度。
以下参照附图,对解决该问题的本发明的实施例进行详细说明。
(实施例1)
图1表示本发明涉及的安装结构体的基本的一个实施例及其制造方法的概略剖视图。图1(a)是适合高密度安装的外部端子采用了焊锡凸点5的普通CSP封装(半导体器件)50的剖视图。半导体芯片1安装在布线基板3上,半导体芯片1的电极与布线基板3的布线图案,通过引线接合法,用接合线2电连接。并且,用模具树脂4进行封合,以覆盖上述各部分。在布线基板3上安装有半导体芯片1的面的相反侧的面上,作为用于与安装半导体器件50的布线基板连接的外部端子,形成有焊锡凸点5。
在这里,作为一个例子,记载了通过引线接合法构成的半导体器件50,但不限于此,只要是在半导体器件的下表面形成有焊锡凸点的封装,则同样可以适用于通过倒装芯片法构成的封装等。
图1(b)至图1(e)表示能够层叠封装的安装结构体60的一例的概略结构剖视图及其制造流程,所述安装结构体60,为了能够将在外部端子上具有焊锡凸点5的普通的封装型半导体器件50以三维方式层叠,通过具有将半导体器件50下表面的电极与上表面的电极电连接的布线图案的挠性布线基板7,包覆半导体器件50而重构。
图1(b)是在单面上形成有热塑性树脂6作为粘接层且具有布线图案的挠性布线基板7上、将两个支撑体90分别粘结固定在与半导体器件50下表面(外部端子形成面)的周边外端部相应的位置上的剖视图。周边外端部是指比最外侧的外部端子更靠外侧的区域。在这里,通过加热使热塑性树脂6显现粘接性,从而将支撑体90夹着热塑性树脂6固定在挠性布线基板7上。
图1(c)是在图1(b)的挠性布线基板7上安装有半导体器件50的状态剖视图。在半导体器件50和挠性布线基板7之间的一部分上构成的支撑体90的厚度,需要与焊锡凸点5的高度相等程度或在其以下,以使焊锡熔融而与挠性布线基板7连接。
并且,优选的是,支撑体90的厚度(高度)为与如下高度相当的厚度:在没有支撑体90的情况下通过回流工序使焊锡熔融而与挠性布线基板7连接时的、从半导体器件50的焊锡凸点5的设置面到热塑性树脂6的表面为止的高度。
并且,支撑体90的外形尺寸(纵、横)为与半导体器件50的外形尺寸(纵、横)相同或在其以下的尺寸,其是如下的结构:至少将存在外部端子的范围切除,以防止其与半导体器件50的外部端子接触。还考虑在半导体器件50的外部端子形成面的周边外端部中,仅设置在角部或边缘部的一部分上。即,也可以将支撑体分割而配置,以能将焊锡凸点的高度限制在恒定的范围内。
通过回流工序使焊锡凸点5熔融,焊锡在挠性布线基板7的电极上涂敷扩散,从而焊锡凸点5的高度变得低于熔融前的高度,但通过如上所述将支撑体90的厚度(高度)设计成热塑性树脂6和支撑体90接触的程度的高度,不会发生焊锡的消沉引起的高度偏差。因此,还能期待抑制在半导体器件50上表面的挠性布线基板7上形成的电极的位置偏差的效果。
在这里,作为支撑体90的材质,与无机/有机无关地可适用各种材料。其中,在支撑体90为如沿着半导体器件50的外周配置的环状结构的情况下,由于因安装后的环境温度而重复膨胀、收缩,因此从焊锡凸点连接部的可靠性的观点出发,优选支撑体90具有与半导体器件50、安装有通过本发明重构的半导体器件(安装结构体)的其他布线基板、或挠性布线基板7接近的热膨胀系数。
由于它们都在10ppm/℃~30ppm/℃的范围内,因此例如支撑体90为有机材料时可适用玻璃环氧,其为无机材料时可适用铝、铜、不锈钢等。
在本实施例1中,表示了在挠性布线基板7上安装有一个半导体器件50的例子,但不限于此,可在挠性布线基板上一起安装多个半导体器件50或其他电子器件。
图1(d)为从图1(c)的状态用挠性布线基板7包覆半导体器件50而粘接固定的状态的剖视图。其同样通过加热使热塑性树脂6显现粘接性,使半导体器件50与挠性布线基板7夹着热塑性树脂6而固定。
在这里,优选半导体器件50的侧面与挠性布线基板7粘接固定。在半导体器件50的侧面与挠性布线基板7没有粘接固定的情况下,回流热负荷时的安装结构体60的剖视图如图2所示。半导体器件50的布线基板通常采用玻璃环氧,其热膨胀系数在从常温时到回流温度区域的范围内为10~15ppm/℃。另一方面,挠性布线基板7的热膨胀系数在20ppm/℃左右,因此在回流热负荷时,如图2所示地成为因挠性布线基板7的膨胀而松弛的状态。并且在加上位于器件侧面部位的挠性布线基板7的膨胀,松弛进一步增加,焊锡凸点5的平坦度恶化。
在本结构中,半导体器件50的侧面和挠性布线基板7粘接固定,至少能够使位于半导体器件50侧面部位的挠性布线基板7的膨胀引起的影响限制为最小限度。并且为了抑制半导体器件50下表面的挠性布线基板7的膨胀引起的松弛,支撑体90优选适用具有与挠性布线基板7的热膨胀系数相同或更大的热膨胀系数的材料。由此,由于即使在热负荷时也因支撑体90而在挠性布线基板7上产生张力,因此能抑制平坦度恶化。即使在半导体器件50的侧面形状为凹凸的情况等、难以在侧面整个区域进行粘接固定的情况下,也优选至少半导体器件50侧面的一部分和挠性布线基板7粘接固定。
并且在本实施例1中,表示了支撑体90粘接固定在挠性布线基板7上的例子,但支撑体90也可以粘接固定在半导体器件50一侧,进而也可以粘接固定在半导体器件50和挠性布线基板7这两侧。
图1(e)是通过回流焊形成用于连接到其他布线基板上的焊锡凸点8后的剖视图。如上所述,通过形成半导体器件50的侧面和挠性布线基板7粘接固定,并且在半导体器件50下表面和挠性布线基板7之间粘接固定而配置支撑体90的结构,在回流热负荷时以及在回流后的常温时这两种状态下,均能够实现与具有良好平坦度的封装层叠相对应的安装结构体60。
并且,也可以在半导体器件50的下表面与挠性布线基板7之间填充底层树脂(未图示)。由此,对于伴随动作时的发热及环境变化而产生的温度周期性负荷、跌落撞击等负荷,能够提高连接部的可靠性。
接着,用图3及图4对将本发明的安装结构体封装层叠的实施例进行说明。
(实施例2)
图3是封装层叠型半导体器件(安装结构体)的概略剖视图,该封装层叠型半导体器件在下层配置本发明所涉及的重构的半导体器件(安装结构体60),在上层层叠没有重构的半导体器件50后,进行了回流焊连接。在图3中,半导体器件50为同一种制品,但作为上层的半导体器件50,也可以配置不同的制品,或者配置晶片级CSP等不同结构的半导体器件、传感器、无源部件(电容器、电阻、逆变器等)等而构成。
(实施例3)
图4是在图3的结构中进一步增加层叠封装数量的例子。在这里,作为一例,表示为能够实现封装层叠而在下层配置3层本发明所涉及的重构的半导体器件(安装结构体60),且在最上层层叠普通的半导体器件50的结构。并且,关于层叠3层的重构的半导体器件(安装结构体),与层数无关,并且不限于同一半导体器件制品。
此外,层叠的全部半导体器件,也可以用本发明的重构的半导体器件(安装结构体60)构成。
本结构的其他效果在于,通过在支撑体90上适用导热率高的材料,能够使半导体器件50散热。作为这种支撑体90的材料,可以适当地利用以铜、铝、不锈钢为代表的金属材料及碳石墨等。并且,在该情况下,对于粘接支撑体90的粘接材料(未图示)也优选导热率高的材料,例如可以适当利用含有金属填料的导电性粘接材料等。粘接材料可以不是固化而粘接的材料,例如也可以为胶状的散热化合物及润滑脂等。
并且,通过在与挠性布线基板7弯曲的部分相应的支撑体90的角部实施C倒角或圆弧状倒角加工,可以减小挠性布线基板7上的布线的曲率,从而不仅可以抑制由机械性弯曲引起的布线断线,还可以降低通过布线的高速信号的反射引起的电噪音,因此可以更为适当地利用。
(实施例4)
参照图5对本发明所涉及的安装结构体的其他实施例进行详细说明。图5中的局部放大图(圆内)是表示在图1(e)所示结构的安装结构体的一部分上通过导电性凸点14将支撑体90与构成于挠性布线基板7上的接地图案11电连接的例子的概略剖视图。局部放大图还表示配置于挠性布线基板7上的布线图案12、包覆挠性布线基板7的绝缘层13及覆盖树脂15、和配置于覆盖树脂15的布线图案12。其中,支撑体90的材料可以适用具有导电性的材料,例如可以由铝、铜、不锈钢等构成。
由此,在配置于安装结构体上层的半导体制品和下层的半导体器件或安装这些安装结构体的其他布线基板之间进行高速信号处理时,能够将配置于挠性布线基板7上的用于传递信号的布线图案12形成为微带传输线结构。
在挠性布线基板7只具有单层布线层的情况下,不能作为微带传输线结构,但通过包括支撑体90,支撑体90的材料具有导电性,并且将支撑体9与配置于挠性布线基板7的接地图案11进行电连接,即使在只具有单层布线层的挠性布线基板7中,也能构成微带传输线。
由此,在非常高速的半导体制品中,同样能够实现具有优异的电特性的封装层叠型的安装结构体。
另外,在图5的局部放大图中,支撑体90的角部没有成为倒角,但可以实施C倒角或圆弧形倒角加工。
(实施例5)
参照图6对本发明的安装结构体的其他实施例进行详细说明。
在图1所示的实施例1中,其结构为仅在半导体器件50的下表面配置了支撑体90,在这种情况下,通过用挠性布线基板7包覆半导体器件50而粘接固定,在半导体器件50的上表面配置电极时,为了高精度地对电极的位置进行定位,需要使支撑体90的安装位置高精度地对齐而配置。因此在实施例5中,形成从支撑体90的外周端向半导体器件50的侧面方向竖起的竖起部91,成为使其与半导体器件50的侧面和下表面这两部分紧密贴合的形状。由此,能够与半导体器件50抵接而定位,能使半导体器件50上表面的电极位置的精度更准确。
图6(a)是在适合高密度安装的外部端子上采用焊锡凸点5的普通CSP封装(半导体器件50)的剖视图。
图6(b)至图6(e)表示能够层叠封装的安装结构体的概略结构剖面及其制造流程,所述安装结构体,为了能够将在外部端子上具有焊锡凸点5的普通的半导体器件50以三维方式层叠,通过具有将半导体器件50下表面的电极与上表面的电极电连接的布线图案的挠性布线基板7,包覆半导体器件而重构。
图6(b)是将具有竖起部91的支撑体90通过粘接材料10粘接固定在半导体器件50的侧面和底面的一部分上的状态的剖视图。此时,支撑体90通过与半导体器件50的下表面及侧面抵接的方法紧密贴合而进行配置。另外,在附图中在半导体器件的下表面、侧面这两部分通过粘接材料10进行粘接,但也可以仅与下表面或侧面的任一方粘接。在这里,粘接材料10可适用薄膜状的材料或液体状的材料等各种材料。
支撑体90可以在半导体器件50底面(外部端子形成面)的整个周边外端部设置,也可以设置在角部或边缘部等的局部上。
图6(c)表示将图6(b)的半导体器件50通过回流法安装在挠性布线基板7上的状态。焊锡凸点5,通过与挠性布线基板7的电极熔融接合而消沉,支撑体90的底面与配置在挠性布线基板7上的热塑性树脂6的表面接触。半导体器件50下表面的支撑体90的厚度为与没有支撑体90时通过回流方式与挠性布线基板7熔融接合时的、焊锡凸点的高度相同的高度(没有粘接层的情况),或与从该焊锡凸点的高度减去粘接层(热塑性树脂6)的厚度后的高度相同的高度(有粘接层的情况),优选为支撑体90的底面与挠性布线基板7或热塑性树脂6的表面接触的厚度,为了使其更可靠地接触,优选稍微更厚一些。
图6(d)是从图6(c)的状态用挠性布线基板7包覆具有竖起部91的支撑体90整体而粘接固定的状态的剖视图。通过抵接法对半导体器件50的下表面、侧面这两部分进行定位,能使半导体器件50和支撑体90紧密贴合而配置,并且使因配置支撑体90而引起的尺寸增加最小化。通过该紧密贴合而配置的结构,能高精度地构成安装有支撑体90的安装结构体60的外形。因此,能固定由挠性布线基板7包覆的长度,可获得能够抑制在安装结构体上方的挠性布线基板7上形成的电极的位置偏差的效果。
在这种情况下,同样为了减少由于回流工序中的热而引起的挠性布线基板7松弛,优选使竖起部91侧面的一部分或整个表面与挠性布线基板7粘接固定。
在这里,作为支撑体90的材质,与无机/有机无关地可适用各种材料。其中,在支撑体90为如沿着半导体器件50的外周配置的环状结构的情况下,由于因安装后的环境温度而重复膨胀、收缩,因此从焊锡凸点5的连接可靠性的观点出发,优选支撑体90具有与半导体器件50、安装有通过本发明重构的半导体封装(安装结构体)的其他布线基板、或挠性布线基板7接近的热膨胀系数。
由于它们都在10ppm/℃~30ppm/℃的范围内,因此例如支撑体90为有机材料时可适用玻璃环氧,其为无机材料时可适用铝、铜、不锈钢等,更有选的是,选择支撑体90的热膨胀系数比挠性布线基板7小的材料。其原因在于,从回流温度冷却时,由于与支撑体90相比,挠性布线基板7的收缩量更大,成为在挠性布线基板7上施加有张力的状态,因此能使挠性布线基板7更加平坦化。
以上,对本发明的实施例作了各种说明,但本发明不限于上述实施例,在不脱离本发明主旨的范围内,当然还能进行更多的改变。

Claims (19)

1.一种安装结构体,将在下表面具有焊锡凸点作为外部端子的一个或多个半导体器件用形成有布线的具有挠性的布线基板包覆,并且在该半导体器件的该外部端子形成面一侧及外部端子形成面一侧的表背相反面一侧这两侧具有外部电极,所述安装结构体的特征在于,
在该挠性布线基板上形成有至少一层布线层,
在该半导体器件的该外部端子形成面和该挠性布线基板之间,将支撑体粘接固定而配置,
所述支撑体中,在该支撑体的外周端的至少一部分设有竖起部,该竖起部在所述半导体器件的侧面和所述挠性布线基板之间从该支撑体的外周端朝向直角方向竖起。
2.如权利要求1所述的安装结构体,其特征在于,
所述半导体器件的外部端子形成面的表背相反面的至少一部分,与所述挠性布线基板粘接固定。
3.如权利要求1所述的安装结构体,其特征在于,
所述半导体器件的侧面的至少一部分与所述挠性布线基板粘接固定。
4.如权利要求1或2所述的安装结构体,其特征在于,
所述支撑体的外形尺寸是与所述半导体器件的外形尺寸相同的尺寸,或是小于所述半导体器件的外形尺寸的尺寸,并且在该支撑体上至少在该外部端子的位置设有贯通孔,以使该支撑体与该半导体器件的外部端子不接触。
5.如权利要求1或2所述的安装结构体,其特征在于,
在所述半导体器件中所述外部端子形成面的周边外端部的全部区域或局部,配置有所述支撑体。
6.如权利要求1或2所述的安装结构体,其特征在于,
在所述挠性布线基板上没有配置用于与所述半导体器件粘接的粘接层时,所述支撑体的厚度,与在没有该支撑体的情况下通过回流法将所述半导体器件与所述挠性布线基板熔融接合的状态下的、所述焊锡凸点的高度相同,或稍大于该高度,
在该挠性布线基板上配置有用于与该半导体器件粘接的粘接层时,所述支撑体的厚度与从所述焊锡凸点的高度减去该粘接层的厚度后的高度相同,或稍大于该长度。
7.如权利要求1所述的安装结构体,其特征在于,
所述半导体器件的侧面的至少一部分和该半导体器件的下表面的至少一部分这两部分与所述支撑体接触而固定。
8.如权利要求1所述的安装结构体,其特征在于,
所述半导体器件的侧面的至少一部分和该半导体器件的下表面的至少一部分这两部分与所述支撑体夹着粘接材料粘接固定。
9.如权利要求1所述的安装结构体,其特征在于,
所述支撑体的所述竖起部的至少一部分与所述挠性布线基板粘接固定。
10.如权利要求1或2所述的安装结构体,其特征在于,
所述支撑体具有与所述挠性布线基板的热膨胀系数相同或者小于所述挠性布线基板的热膨胀系数的热膨胀系数。
11.如权利要求1或2所述的安装结构体,其特征在于,
所述支撑体用粘接剂与所述挠性布线基板及所述半导体器件中的至少一方粘接固定。
12.如权利要求11所述的安装结构体,其特征在于,
所述粘接剂为导电性粘接剂。
13.如权利要求1或2所述的安装结构体,其特征在于,
所述支撑体由具有导电性的材料构成,并且所述挠性布线基板的接地图案和该支撑体通过导电性凸点电连接。
14.如权利要求1或2所述的安装结构体,其特征在于,
与弯曲所述挠性布线基板的位置相应的、所述支撑体的最外周角部,被去掉角而成为C倒角或圆弧形的形状。
15.如权利要求1或2所述的安装结构体,其特征在于,
在所述挠性布线基板上形成有至少1层粘接层,所述半导体器件和该挠性布线基板的至少一部分通过该粘接层粘接固定。
16.如权利要求15所述的安装结构体,其特征在于,
所述粘接层由热塑性树脂或热固化前的热固性树脂构成。
17.一种层叠型半导体器件,其特征在于,
包括权利要求1所述的安装结构体。
18.如权利要求17所述的层叠型半导体器件,其特征在于,
还安装有无源部件。
19.一种电子设备,其特征在于,
包括权利要求17或18所述的层叠型半导体器件。
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