CN101533785B - 薄tim无核高密度无凸点封装的形成方法和由此形成的结构 - Google Patents

薄tim无核高密度无凸点封装的形成方法和由此形成的结构 Download PDF

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CN101533785B
CN101533785B CN2008101661595A CN200810166159A CN101533785B CN 101533785 B CN101533785 B CN 101533785B CN 2008101661595 A CN2008101661595 A CN 2008101661595A CN 200810166159 A CN200810166159 A CN 200810166159A CN 101533785 B CN101533785 B CN 101533785B
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汤加苗
D·陆
赵柔刚
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Abstract

本发明描述形成微电子器件结构的方法。这些方法可包括：将多个支承环放置在支承架的粘性层上，其中支承环被置于支承架的空腔内；将多个薄管芯放置在支承架的底座上，其中薄管芯的顶面基本与支承环的顶面齐平；然后在管芯的顶面上堆积多层。

Description

薄TIM无核高密度无凸点封装的形成方法和由此形成的结构
发明背景
[0001]微电子管芯在被用于封装应用中时可提供很多优点。例如，在将这种薄管芯用在微电子结构和/或微电子封装结构中时可提高热和电性能。
附图简述
[0002]尽管说明书归纳出具体指出并明确要求被视为本发明的权利要求，但在结合附图阅读本发明的以下描述可更容易地确定本发明的优点，附图中：
[0003]图1a-1m示出根据本发明的实施例的结构。
具体实施方式
[0004]在以下的详细描述中，对作为例示示出实施本发明的特定实施例的附图进行参考。足够详细地描述这些实施例以使本领域的技术人员能够实施本发明。可以理解，本发明的各实施例尽管不同但未必相互排斥。例如，本文中结合一个实施例描述的特定特征、结构或特性可在不背离本发明的精神和范围的情况下在其他实施例中实现。此外，将理解可在不背离本发明的精神和范围的情况下修改每个公开的实施例中各元件的位置和安排。因此，以下的详细描述不是限制的意思，且本发明的范围仅由适当解释的所附权利要求连同权利要求授权的全范围的等价技术方案所限制。附图中，各视图中相同的附图标记指示相同或相似功能。
[0005]描述形成微电子结构的方法。这些方法可包括：将多个支承环放置在支承架的粘性层上，其中支承环被置于支承架的空腔内；将多个薄管芯放置在支承架的底座上，其中薄管芯的顶面基本与支承环的顶面齐平；然后在管芯的顶面上堆积叠加多个层。本发明的方法使得具有薄的热界面材料(TIM)的薄管芯能够用在例如高密度无核无凸点微电子封装中。这种实现显著提高了利用本发明的方法和结构的微电子结构的热和/或电性能。
[0006]图1a-1m示出形成微电子结构的方法的实施例，例如用于形成部分无凸点、无核微电子封装的方法。图1a示出衬底支架100的横截面。衬底支架100可为管芯的放置提供支承结构，且还可包括底座104和空腔102。空腔可具有深度103，其中深度103的大小可取决于具体应用。
[0007]可在衬底支架100上形成基本覆盖底座104和空腔102的可释放层106。在一个实施例中，可释放层106可包括随后可被固化的硅酮层。在其他实施例中，可释放层106可包括任何在固化后有粘性的材料，且可提供对随后放置在支承架100上的管芯的相当大的粘附力，但还不是强到阻止在后续处理步骤期间管芯从支承架100脱离的粘结剂。
[0008]可将至少一个支承环108放置在释放层108上，其中可将各个支承环108放置在各个空腔102内(图1b)。在一个实施例中，可利用拾取和放置技术来放置至少一个支承环108的每一个，如本领域中所已知的。在一个实施例中，该至少一个支承环108可包括FR4(阻燃剂4)、铜、SS(不锈钢)、铝、硅和陶瓷材料中的至少之一。在一个实施例中，至少一个支承环108的高度115可高于底座104的高度117。在一个实施例中，支承环高度115和底座105高度117之差可以约是随后放置在底座104上的管芯的高度(即厚度)。在至少一个支承环108的侧壁111和支承架100的底座104的侧壁103之间可存在间隙109。
[0009]图1c描述了设置在支承架100上的支承环108的俯视图，其中空腔102由支承环108包围。在另一实施例中，至少一个支承环108可被预先构造成支承环镶板110(图1d)，使得支承环镶板110可被放置在支承架100的多个空腔102中(图1e)。在一个实施例中，支承环110的高度115可高于它们包围的多个底座104的高度117。
[0010]在一个实施例中，可将至少一个管芯112放置在至少一个底座104上(图1f)，使得管芯的晶体管侧面向上，而管芯的后侧119设置在释放层106上。在一个实施例中，可通过利用拾取和放置工艺来将至少一个管芯放置在至少一个底座104上。可释放层106可将至少一个管芯112保持基本平坦并将其保持在衬底支架100的至少一个底座104的适当位置上。
[0011]在一个实施例中，至少一个管芯112的厚度114可与支承架108的高度115和底座104的高度117之差基本相同。在一个实施例中，至少一个管芯112的厚度114可介于约25微米至约500微米。在一个实施例中，至少一个管芯112可与至少一个支承环108的顶面116基本齐平。以此方式，可显著减小和/或消除管芯翘曲，因此在利用本发明的各实施例制造器件期间大大提高可靠性和成品率。
[0012]在一个实施例中，包封剂118可分散在间隙109内，它用于包封衬底支架100内的至少一个管芯112(图1g)。然后可使包封剂118固化，且在某些实施例中，包封剂118可包括低粘度聚合物。包封剂118可基本填充间隙109，且还可将至少一个管芯112连接至至少一个支承环108。在某些情况下，包封剂可包括在机械强度大的材料。必须足够注意以保证没有包封剂118分散在至少一个管芯112的顶面120上，因为包封剂可污染管芯顶侧的导电焊盘并干扰管芯和积层之间的电连接。
[0013]在某些实施例中，包封剂118可为设置在衬底支架100上的管芯112提供机械刚度和强度，因此减少管芯翘曲问题。因为在堆积多个层之前将至少一个支承环108放置在衬底支架上，所以可将管芯的厚度修整成与底座和至少一个支承环之间的高度差基本上相同，所以这允许以基本平坦的方式放置非常薄的TIM(在随后的组装处理期间)，且还提供用于避免管芯翘曲的机械刚度。
[0014]可将各种衬底积层122添加至至少一个管芯112的顶面120和支承环108的顶面116(图1h)，其中衬底积层122可构成例如一部分封装。积层122可包括诸如电介质层和铜层之类的材料，但积层122的具体成分将取决于具体应用。
[0015]在一个实施例中，衬底积层122、至少一个管芯112、包封剂118和至少一个支承环108可构成一部分封装结构124。在一个实施例中，封装结构124可包括一部分高密度、无核、无凸点封装结构124，其中至少一个管芯112可不使用凸点—例如不使用焊料凸点—而与封装衬底积层122电连接。
[0016]可通过将支承架100从封装结构124拉开来而从封装结构124释放126支承架100(图1i)。由于与至少一个管芯112与封装结构124的粘附力相比，释放层106和至少一个管芯112之间的粘附力较弱，因此可从封装结构124容易地去除衬底支架100。在一个实施例中，封装结构124可被单片化128成包含单个管芯的单独部分(图1j)。
[0017]在一个实施例中，可将热界面材料(TIM)130附连至至少一个管芯112的后侧119(图1k-11)。在一个实施例中，TIM130可具有约10微米至约150微米的厚度，且在某些实施例中可包括预制焊料(solder perform)。诸如但不限于散热片的排热结构132可被附连至TIM130。图1m描述了一部分高密度、无核、无凸点封装结构136，其中至少一个管芯112可不使用凸点—例如不使用焊料凸点—而与积层122电连接134。
[0018]在用于封装应用中时薄微电子管芯112的使用可提供很多优点。例如，当这种薄管芯112与薄(TIM)130结合时可增强热性能。在某些情况下，这种薄管芯112的厚度114可比用于将薄管芯112放入封装结构124的衬底支架100的厚度140小很多(图1i)。
[0019]因此，本发明的实施例的优点包括但不限于实现薄管芯、薄TIM高密度无核无凸点封装制造，且显著提高这种封装结构的热和电性能。由于衬底支架的机械刚度，即使没有消除也可基本去除积层的翘曲，因此完成的最后封装将具有非常少量的翘曲。
[0020]尽管上述的描述具有可用于本发明的方法的特定步骤和材料，但本领域的技术人员将意识到可进行很多修改和替换。因此，旨在将所有这些修改、改变、替换和添加视为落入由所附权利要求书定义的本发明的精神和范围内。此外，应意识到微电子器件的某些方面在本领域中是已知的。因此，应意识到本文提供的附图仅示出属于本发明的实施的部分示例性微电子结构。因此本发明不限于本文所述的结构。

Claims (20)

1.一种形成微电子结构的方法，其包括：
在支承架上形成释放层，其中所述支承架包括至少一个底座和空腔，且所述释放层覆盖所述至少一个底座和空腔；
将多个支承环放置在所述空腔中；
将多个管芯放置在所述底座上，其中所述管芯的顶面与所述支承环的顶面基本齐平；
用包封剂填充所述管芯的侧壁和所述支承环的侧壁之间的间隙；
在所述管芯的顶面上堆积多个层。
2.如权利要求1所述的方法，其特征在于，还包括将所述支承架从所述释放层释放。
3.如权利要求1所述的方法，其特征在于，还包括将所述管芯单片化成单个封装。
4.如权利要求1所述的方法，其特征在于，还包括将TIM附连至所述管芯的底面。
5.如权利要求4所述的方法，其特征在于，还包括将散热片附连至所述TIM。
6.如权利要求4所述的方法，其特征在于，所述管芯和在所述管芯的顶面上所堆积的多个层之间的至少一个互连包括无凸点管芯衬底互连。
7.一种形成微电子结构的方法，其包括：
将多个支承环放置在支承架的释放层上，其中所述支承架包括底座和空腔，所述释放层覆盖所述底座和所述空腔，并且其中所述支承环置于所述支承架的所述空腔内；
将多个管芯放置在所述支承架的所述底座上，其中所述管芯的顶面与所述支承环的顶面基本齐平；
在所述管芯的顶面上堆积多个层。
8.如权利要求7所述的方法，其特征在于，还包括用包封剂填充所述管芯的侧壁和所述支承环的侧壁之间的间隙。
9.如权利要求7所述的方法，其特征在于，所述管芯具有在约25微米至约500微米之间的厚度。
10.如权利要求7所述的方法，其特征在于，还包括将TIM附连至所述管芯的底面。
11.如权利要求10所述的方法，其特征在于，所述TIM具有在约10微米至约150微米之间的厚度。
12.如权利要求7所述的方法，其特征在于，所述管芯具有在约25微米至约500微米之间的厚度。
13.一种微电子结构，其包括：
设置在支承架上的释放层，其中所述支承架包括至少一个底座和空腔，且所述释放层覆盖所述至少一个底座和空腔；
设置在所述空腔中的多个支承环；
设置在所述底座上的多个管芯，其中所述管芯的顶面与所述支承环的顶面基本齐平；
设置在所述管芯的顶面上的多个积层。
14.如权利要求13所述的微电子结构，其特征在于，还包括设置在所述管芯的底面上的TIM。
15.如权利要求13所述的微电子结构，其特征在于，还包括设置在所述管芯的侧壁和所述支承环的侧壁之间的包封剂。
16.如权利要求13所述的微电子结构，其特征在于，所述管芯具有在约25微米至约500微米之间的厚度。
17.如权利要求13所述的微电子结构，其特征在于，所述TIM具有在约10微米至约150微米之间的厚度。
18.如权利要求13所述的微电子结构，其特征在于，所述管芯和积层之间的至少一个互连包括无凸点管芯衬底互连。
19.如权利要求17所述的微电子结构，其特征在于，还包括设置在所述TIM上的散热片。
20.如权利要求13所述的微电子结构，其特征在于，所述释放层包括硅酮。
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