CN101506943A - 补偿亚稳定化合物基异质结双极晶体管 - Google Patents
补偿亚稳定化合物基异质结双极晶体管 Download PDFInfo
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- 150000001875 compounds Chemical class 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 65
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 25
- 229910052799 carbon Inorganic materials 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 17
- 229910052732 germanium Inorganic materials 0.000 claims description 13
- 230000007547 defect Effects 0.000 claims description 8
- 230000008859 change Effects 0.000 claims description 7
- 238000009826 distribution Methods 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 claims 1
- 239000002800 charge carrier Substances 0.000 claims 1
- 230000002708 enhancing effect Effects 0.000 claims 1
- 230000008521 reorganization Effects 0.000 claims 1
- 229910010271 silicon carbide Inorganic materials 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 9
- 238000011065 in-situ storage Methods 0.000 abstract description 5
- 239000010409 thin film Substances 0.000 abstract description 4
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 39
- 238000005516 engineering process Methods 0.000 description 25
- 229910052710 silicon Inorganic materials 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 241000894007 species Species 0.000 description 10
- 229910045601 alloy Inorganic materials 0.000 description 8
- 239000000956 alloy Substances 0.000 description 8
- 238000000137 annealing Methods 0.000 description 8
- 238000000407 epitaxy Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000011435 rock Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 230000002950 deficient Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 230000006798 recombination Effects 0.000 description 5
- 238000005215 recombination Methods 0.000 description 5
- 239000012528 membrane Substances 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 208000006536 Ephemeral Fever Diseases 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 235000010627 Phaseolus vulgaris Nutrition 0.000 description 2
- 244000046052 Phaseolus vulgaris Species 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- 229910000078 germane Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- 239000007833 carbon precursor Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
一种用于通过应变补偿原子种类的取代布置来假晶生长和集成原位掺杂的应变补偿亚稳定化合物基(107)到电子器件(100)如例如SiGe NPN HBT中的方法。本发明也应用于其它电子器件中的应变层，比如MOS应用、竖直薄膜晶体管(VTFT)和各种其它电子器件类型。由SiGe以外的化合物半导体如例如GaAs、InP和AlGaAs形成的异质结和异质结构器件也可顺应于这里描述的有益工艺。
Description
技术领域
[01]本发明通常主要地涉及集成电路(IC)的制作方法。具体而言，本发明是制作和集成亚稳定硅锗(SiGe)基区到异质结双极晶体管(HBT)中的方法。
背景技术
[02]SiGe HBT在增益、频率响应、噪声参数方面较硅(硅)双极结晶体管(BJT)而言具有显著优点并且保留以相对低的成本与CMOS器件集成的能力。据报道SiGeHBT的截止频率(Fτ)超过300GHz，这较GaAs器件而言颇受称道。然而，GaAs器件成本相对高并且无法实现如例如BiCMOS器件的集成水平。硅兼容的SiGe HBT提供了迅速取代其它化合物半导体器件的低成本、高速度、低功率解决方案。
[03]SiGe优点的实现归因于能带隙，该能带隙在HBT的一个或者多个Si-SiGe异质结产生能量带移位，由此造成给定基极-射极偏置的电流密度增加以及更高增益。将Ge添加到Si晶格可实现更低电阻率。更高电流密度和更低基极电阻值允许单位增益截止频率和最大振荡频率较可比硅BJT而言有所提高并且可与其它化合物器件如GaAs相媲美。然而，射极集极击穿电压(尤其是BVCEO)与电流增益(β)成反比。为了增强Fτ和减少功率而需要的结构和工艺改变导致越来越高的电流增益以及因此导致越来越低的集极-射极击穿电压。
[04]提高的Ge分数就给定层厚度和掺杂碎片而言造成积极重组电流增加和电流增益减少。已经实验上确认这一效果延及30％Ge以外。与具有高Ge含量的假晶(pseudomorphic)SiGe中的缺陷形成有关的文献表明该效果对于40％以上的Ge分数将继续增加(即Kasper等人的“Properties of Silicon Germanium and SiGe：Carbon”，INSPEC，2000)。因此，增加Ge分数高到足以减少高速器件中的电流增益这一折衷提供了一种补偿BVCEO随着带宽继续缩减而不可避免的增益增加和降级的方式。
[05]然而，对于在出现过度应变松驰和总体晶态缺陷可以将多少Ge添加到Si晶格具有限制。作为与底层硅匹配的晶格的SiGe层的临界厚度(hc)是(1)Ge的百分比、(2)SiGe膜厚度、(3)盖层厚度、(4)HBT膜堆叠处理温度以及(5继硅锗沉积之后的热退火温度的函数。在临界厚度hc以上，SiGe膜是亚稳定和/或不稳定区，这意味着它容易随着施加足够大的热能而松驰。因此，亚稳定度主要地取决于百分比Ge、SiGe层厚度、盖层厚度和归因于热能的工艺诱发应变。描述至此的常规SiGe HBT的SiGe基的构造是稳定、假晶或者晶格匹配层的构造。同时期现有技术的过程包括生长稳定、应变或者晶格匹配的含碳SiGe合金以防止硼分布在基区中扩散。
[06]由于松驰造成晶格瑕疵这一事实而通常避免亚稳定膜生长。这些瑕疵造成重组中心；因此出现少数载流子寿命(τb)降低而基极重组电流(IRB)增加。如果不加以控制，则归因于晶格瑕疵的结果性不良晶体力量将使器件性能降级。“桥接”效应也会导致过量漏电流以及极低电流增益。膜也会对工艺诱发的热应变很敏感而因此将不可制造。因此，为了避免这一类降级，迄今为止的HBT设计实现了具有在膜生长的稳定区中的基区的器件，该稳定区等同于等于或者小于临界厚度hc的SiGe厚度。
[07]比如在以下数篇论文中讨论了亚稳定SiGe的性质：D.C.Houghton，“StrainRelaxation Kinetics in Si1-xGex/Si Heterostructures”，Journal of Applied Physics，第70卷第2136-2151页(1991年8月15日)以及G.S.Kar等人的“Effect of carbon on lattice strainand hole mobility in Si1-xGex alloys”，Dept.of Physics and Meteorology，Indian Institute ofTechnology，Kharagpur 721302，India，Journal of Materials Science：Materials inElectronics，第13卷第49-55页(2002)。另外，U′Ren等人的美国专利第6,586,297号(`297专利)和第6,781,214号(`213专利)分别描述了用于将亚稳定基集成到高性能HBT中和有关结构。
[08]`294专利描述了一种异质结双极晶体管，该晶体管包括在位于亚稳定外延SiGe基之上的单晶集极和射极上的亚稳定外延硅锗基。
[09]在外延反应器中生长亚稳定外延SiGe基，其中亚稳定外延SiGe基是包括在膜生长过程中原位(in-situ)混入的更改传导性的掺杂物的应变晶态结构；添加掺杂物的目的仅在于建立具体传导性类型。`297专利描述了一种方法，该方法包括在900℃至950℃的温度短暂热退火以避免使亚稳定SiGe膜层松驰。
[10]`214专利描述了一种通过以大于20个原子百分比的锗浓度在集极上形成亚稳定外延SiGe基来制作的异质结双极晶体。然后在亚稳定外延SiGe基之上制作射极。根据晶体管类型npn或者pnp以n或者p型杂质来掺杂射极。然后在峰式(spike)退火工艺中加热HBT以将亚稳定外延硅锗基维持为应变晶态结构并且扩散掺杂物以形成射极-基极结构。在外延反应器中生长亚稳定外延SiGe基，其中亚稳定外延SiGe基是包括在膜生长过程中原位混入的掺杂物的应变静态结构；添加掺杂物的目的仅在于建立具体传导性类型。`214专利描述了一种方法，该方法包括在900℃至950℃的温度短暂热退火以避免使亚稳定SiGe膜层松驰。
[11]然而，在这些前述文献中描述的用于形成亚稳定SiGe膜的方法仍易受热应变如滑移错位和螺纹(threading)错位的不利影响；所有这些热应变都与膜松驰相关联。在高亚稳定度的膜中，根据亚稳定度在退火工艺过程中在极短时间间隔中(比如在短暂退火和/或快速退火工艺过程中秒的第一分数)可能发生松驰。
[12]因此，需要一种用以生长和集成应变补偿亚稳定SiGe层以便应用于SiGeHBT的方法。这样的方法应当允许本领域技术人员例如控制和利用缺陷密度以求器件优化、实现极高的能量带偏移和等级(ΔEG(0)和ΔEG(等级))而不招致过度“桥接”缺陷如滑移或者螺纹错位并且提供一种用以实现通常由于它们极度亚稳定或者甚至不稳定的性质而不可靠和/或不可重复的膜的批量可制造性的方法。
[13]这些改进各自允许使用本来高亚稳定度(或者甚至不稳定)的膜以便实现高的Ge浓度所赋与的优点。
发明内容
[14]本发明是一种用于假晶生长和集成也可以原位掺杂的应变补偿亚稳定和/或不稳定化合物基到电子的方法，应变补偿原子种类(atomic species)的取代和/或填隙布置。该方法允许控制缺陷密度并且因此控制少数载流子寿命、基极重组电流、基极电流和电流增益以及击穿。此外，无需应变补偿也可以有实现更大Ge分数的能力，并且维持应变三个匹配膜实现了能量带偏移更大而且因此电流密度大大提高以及因此Fτ和Fmax因数显著提高的器件。
[15]本发明也应用于包括各种其它电子器件类型中的应变层，包括MOS应用、竖直薄膜晶体管(VTFT)、共振隧道二极管(RTD)和各种其它电子器件类型中的应变SiGe、应变Ge和/或应变Si。由SiGe以外的化合物半导体如例如GaAs、InP和AlGaAs形成的异质结和异质结构器件也可以顺应于这里描述的有益工艺。对传导性影响不明显的元素常常将取代地和/或填隙地混合的任何应变补偿元素都可顺应于这里呈现的方法。
[16]对传导性影响不明显的元素常常是合乎需要的。因此，当使用应变补偿IV族半导体如Si、Ge和/或SiGe时，可能希望避免II/III族或者V/VI族以避免影响传导性。然而，这并不排除将“更改传导性”的元素用于应变补偿也同时有效地更改传导性的双重目的。
[17]通过这里描述的方法来制作的一种电子器件在一个示例实施例中包括具有衬底，该衬底在衬底的第一表面之上沉积的化合物半导体膜。对于使用锗浓度以及在已经形成化合物半导体之后的工艺中利用的热循环，通过超过临界厚度hc在亚稳定状态沉积化合物半导体膜。在膜生长过程中原位添加取代性的应变补偿原子种类(例如碳)以控制缺陷密度并且避免在其余处理过程中的完全松驰。
附图说明
[18]图1是根据本发明在形成HBT的一部分时使用的膜堆叠的示例横截面。
[19]图2是描绘了作为Ge含量的函数的临界厚度的曲线。
[20]图3是应变晶格匹配亚稳定SiGe膜的Xrd摇摆曲线。
[21]图4是在热退火之后图3的Xrd摇摆曲线。
具体实施方式
[22]应变补偿原子种类是在添加时从晶态膜的晶格参数的本征值更改晶格参数的种类。本征晶格参数是无应变补偿核素的膜或者层的晶格参数。为求SiGe的应变补偿，一种应变补偿原子种类是碳。一个原子百分比的取代碳将补偿八个百分比到十个百分比的Ge。此外还可以在SiGe中取代地置入约2.5个百分比的碳或者足够的碳以应变补偿20至25个百分比的Ge。因此，Ge水平大于40个百分比的假晶应变补偿亚稳定和/或不稳定膜对于电子器件用途而言是可能的(也就是使用四个百分比到五个百分比的碳)。
[23]即使一个示例实施例提供了减少应变，但是也可以添加晶格常数大于Si或者Ge的应变补偿原子种类以有意地增加应变。这一类应变修改例如作为用于能隙和/或晶格设计工程的工具也将是适宜的；缺陷设计工程也可以很好地利用应变修改。应变修改对于增强“应变补偿膜”和任何相邻膜层中的载流子迁移率也将是有用的。
[24]这里描述的方法与用于形成SiGe HBT的先前方法不同在于强调有目的地生长亚稳定和/或不稳定基层以及有计划地混入取代和/或填隙碳。取代和/或填隙碳应变补偿了HBT基区以避免应变松驰并且允许缺陷设计工程使电流增益与IC和Ft增强去耦合以及集成下游热退火工艺，由此避免过度碳扩散而将膜维持于应变状态。
[25]参照图1，在形成HBT的应变补偿层时使用的示例膜堆叠100包括衬底101、外延层103、基本种子层105、应变补偿亚稳定SiGe基区107、基本盖层109和多晶硅射极层111。本领域技术人员将认识到可以将其它材料用于射极层111，如例如多晶SiGe。
[26]在一个具体示例实施例中，衬底101是p型20欧姆-厘米<100>硅晶片。外延层103通过LPCVD来生长并且根据技术应用和对击穿电压和集极电阻的要求而可以是p型或者n型。砷和/或磷可以掺杂到外延层103和衬底107中以提供低电阻集极区。可以扩散或者注入砷和磷。如果被注入，则本领域技术人员将认识到注入能量和剂量必须取决于对集极电阻、击穿电压等的具体技术要求。本领域技术人员也将认识到可以利用其它方法来掺杂此区，比如扩散或者LPCVD(原位掺杂)。
[27]在硅衬底101的情况下，在生长之前，应当清洁硅生长表面(通常用湿性化学物如氢氟酸)以去除任何原生氧化物和表面污物。可以在同一LPCVD工艺中制作基本种子层105、亚稳定基区107和基本盖层109。对于通常将范围为500℃至900℃的温度用于各层的外延生长。硅烷(SiH4)和锗烷(GeH4)是用于硅和SiGe沉积的典型气体。乙硼烷(B2H6)和砷化氢(AsH3)是常见p型和n型掺杂源。氢气(H2)可以用作载体气体，然而可以使用其它气体如氦。
[28]在另一具体示例实施例中，衬底101是硼掺杂浓度约为1015个原子/立方厘米的<100>p型硅晶片。可选地，衬底101也可以例如是n型硅镜片或者是包括p型或者n型传导性的化合物半传导材料如硅锗的衬底。衬底101也可以是绝缘体上硅(SOI)或者绝缘体上硅锗。外延层103沉积为厚度在0.3μm与2μm之间、继而是基本种子层105。通常添加外延层作为低掺杂区以调整(tailor)击穿电压和/或集极电阻。
[29]在这一实施例中，基本种子层105包括外延生长为厚度范围10nm至100nm的硅，不过可以使用其它半传导材料，比如具有很低Ge含量的硅锗。应变补偿亚稳定SiGe层107沉积为厚度大于临界厚度hc、继而是例如包括硅的基本盖层109。
基于Ge在亚稳定区的上届和下届内的原子百分比来确定临界厚度hc。这一临界厚度确定是基于People/Bean和Matthews/Blakeslee的历史工作并且为本领域技术人员所知。
[30]作为一个例子，图2示出了对于具有20％Ge的膜而言临界厚度hc根据如亚稳定区的底边所限定的People/Bean曲线约为20nm而具有28％Ge的膜具有仅9nm的hc。因此，为了生长厚度也是20nm的具有28％Ge的完全“应变补偿”膜，可以添加碳以减少晶格参数和应变补偿8％的Ge。在20nm、28％Ge膜的整个SiGe晶格中添加1％的碳会把应变减少到近似于20nm、20％Ge膜的碎片。然而，本领域技术人员将认识到出于缺陷设计工程的目的而可能技术上希望提供仅足以部分地应变补偿的碳，例如添加0.5％的碳。可选地，出于增添热处理鲁棒性的目的而可以添加2％的碳。
[31]此外还可能希望将驻留性好的膜生长到亚稳定区中、然后仅部分地补偿该膜以便针对缺陷和/或晶格设计工程而维持某一亚稳定度。
[32]本领域技术人员将认识到比如图2的数据和图表这样的数据和图表是为了提供近似，但是其它手段如Xrd摇摆曲线对于辅助针对某一膜结构和/或器件而确定最优亚稳定度位于何处是必要的。参照图3，本领域技术人员将知道在硅峰与“SiGe驼峰(hump)”之间的不同“边缘环(fringe ring)”表示了晶格匹配或者应变层。
[33]Xrd摇摆曲线中边缘的缺失和/或“模糊”将表示继热退火循环之后的膜松驰(图4)。本领域技术人员也将知道继膜生长之后以及也继下游热处理之后获取的Xrd摇摆曲线将提供对于调整应变补偿工艺和/或热工艺以避免完全应变或者晶格松驰而言必需的信息。
[34]可以利用其它实验方式，比如使电器件经过电性测试以标识对于特定器件或者技术而言可接受的应变补偿水平。这一可接受水平将取决于器件电性参数、对于HBT而言尤其是集极电流、基极电流、电流增益和击穿电压。针对其它器件类型和/或技术可以表征和控制其它电性参数。
[35]应当利用实验方法来表征单独工艺，这些实验方法用以确定它们的工艺相对于比如上文讨论的那样的理论和经验推导图表所示稳定/亚稳定/松驰区域而言驻留于何处。这一表征将需要借助比如Xrd摇摆曲线、器件电测试和SIM(次级离子质谱仪)进行分析以揭示尤其是应变补偿种类如碳的掺杂物扩散。
[36]即使无图表，Xrd摇摆曲线仍可提供用于开发应变补偿膜所必需的定量和定性数据，而1％的碳补偿8％至10％的Ge这一“经验规则”是公认准则。一些亚稳定和/或不稳定膜和/或器件根据在现代理论和经验知识体中没有考虑的比如膜几何形状、热应变和物理诱发应变(来自相邻膜和结构)这样的因素而可以需要或多或少的碳。因此，这里提供的准则将有助于开发亚稳定“应变补偿”膜和/或器件并且旨在于作为一种用于提供改进的工艺和器件的系统。这些准则也为能带隙设计工程(即Jc、Fτ、Fmax)以及缺陷和/或晶格设计工程(即少数载流子寿命设计工程、基极重组电流设计工程、基极电流设计工程、电流增益设计工程和击穿优化)提供更大程度的设计工程灵活性。
[37]进一步参照图1，多晶硅射极层111在这一示例实施例中包括可以沉积为厚度在0.05μm与0.30μm之间的n型多晶硅。然而，也可以利用其它膜如多晶SiGe。
[38]在应变补偿亚稳定SiGe层107的生长过程中利用碳前体(例如甲烷(CH4)或者乙炔(C2H2))来添加碳。用于形成应变补偿亚稳定SiGe层107的前体例如包括分别用于碳、硅和锗成分的甲基硅烷(CH3SiH3)、硅烷(SiH4)和锗烷(GeH4)。氢气(H2)通常用作所有层沉积的载体气体。在应变补偿亚稳定SiGe层107的中心附近以薄截面的更改传导性的掺杂物进行原位参照产生p型中性基区。这一中性基区夹在两个SiGe缩退或者间隔物层(未示出)之间。p型杂质可以是普遍用乙硼烷(B2H6)前体来供应的硼。在应变压缩亚稳定SiGe层107的顶部上外延地生长基本盖层109。基本盖层109(硅)将SiGe层维持于应变状态。通常以在0.05μm与0.1μm之间的厚度生长盖层。本领域技术人员将认识到盖层维持SiGe层内的应变均衡并且随需适当地调整厚度。
[39]与应变补偿亚稳定SiGe层107相关联的Ge的分布一般是梯形，不过本领域技术人将认识到其它Ge分布如三角形、方形或者具有曲率的分布是可能的。多晶硅射极层111例如可以是n型原位掺杂多晶硅。砷烷(ASH3)可以用作n型掺杂物前体，该前体利用氢气作为用于该工艺的载体气体。射极层111可以是单晶硅、多晶硅、非晶体或者单晶硅、多晶硅或者非晶体构造的复合材料。在一个具体示例实施例中，SiGe沉积温度范围为550℃至650℃，不过低于600℃的温度一般对于许多高级制作工艺可能是优选的，其中加工压强范围为1托至100托。假晶SiGe生长在比如高达或者甚至超过900℃的更高温度是可能的。
[40]虽然按照示例实施例描述了本发明，但是本领域技术人员将认识到这里描述的技术可容易地应用于其它形式的制作技术和器件。例如，应变补偿技术可以应用于其它技术如FinFET、环绕门FET、竖直薄膜晶体管(VTFT)、超陡结、共振隧道二极管(RTD)和用于光子学的光学波导。因此，可以选择应变补偿亚稳定SiGe层107的分布、厚度和浓度以适应各种需要。也可以用可以诱发给定掺杂物类型扩散性削弱的其它元素来应变补偿亚稳定SiGe层107。
[41]另外，虽然具体描述了工艺步骤和技术，但是本领域技术人员将认识到可以利用仍然包含于所附权利要求的范围内的其它技术和方法。例如，有若干技术用于沉积和掺杂膜层(例如化学气相沉积、等离子体增强化学气相沉积、分子束外延、原子层沉积等)。虽然并非所有技术都可顺应于这里描述的所有膜类型，但是本领域技术人员将认识到多种替代方法可以用于沉积或者以别的方式形成给定层和/或膜层。
[42]此外，半导体产业的许多联盟产业可以利用应变补偿技术。例如，数据存储产业中的薄膜头(TFH)工艺、平板显示器产业中的有源矩阵液晶显示器(AMLCD)或者微机电产业(MEM)可以容易地利用这里描述的工艺和技术。术语“半导体”因此应当理解为包括前述和有关产业。附图和说明书因而视为举例说明的而非限制性意义的。
Claims (32)
1.一种用于制作化合物半导体膜的方法，所述方法包括：
提供具有第一表面的衬底；
在所述衬底的所述第一表面之上形成所述化合物半导体膜，所述化合物半导体膜具有所述化合物半导体的第一半传导材料的高浓度使得所述化合物半导体在亚稳定状态；以及
用应变补偿原子种类掺杂所述化合物半导体膜。
2.如权利要求1所述的方法，还包括选择所述应变补偿种类的浓度以控制缺陷密度和增强能带隙或者晶格特征。
3.如权利要求1所述的方法，其中所述化合物半导体基本上由硅锗组成。
4.如权利要求1所述的方法，其中所述化合物半导体的所述第一半传导材料是锗。
5.如权利要求1所述的方法，其中所述化合物半导体基本上由磷化铟镓组成。
6.如权利要求1所述的方法，其中所述化合物半导体基本上由碳化硅组成。
7.如权利要求1所述的方法，其中所述化合物半导体基本上由砷化镓组成。
8.如权利要求1所述的方法，其中所述化合物半导体基本上由磷化铟组成。
9.如权利要求1所述的方法，其中所述化合物半导体基本上由砷化铝镓组成。
10.如权利要求1所述的方法，其中所述应变补偿种类是碳。
11.如权利要求1所述的方法，其中选择所述应变补偿种类以减少所述化合物半导体的晶格应变。
12.如权利要求1所述的方法，其中选择所述应变补偿种类以增加所述化合物半导体的晶格应变。
13.如权利要求1所述的方法，其中原位执行所述用所述应变补偿原子种类掺杂所述化合物半导体的步骤。
14.如权利要求1所述的方法，其中选择所述应变补偿原子种类以更改载流子重组。
15.如权利要求1所述的方法，其中选择所述应变补偿原子种类以更改传导带结构。
16.如权利要求1所述的方法，其中选择所述应变补偿原子种类以更改传导价带结构。
17.如权利要求1所述的方法，还包括成形所述第一半传导材料为具有梯形形状。
18.如权利要求1所述的方法，还包括成形所述第一半传导材料为具有三角形形状。
19.如权利要求1所述的方法，还包括成形所述第一半传导材料为具有方形形状。
20.如权利要求1所述的方法，还包括成形所述第一半传导材料为具有弯曲形状。
21.如权利要求1所述的方法，其中在范围为500℃至900℃的温度发生所述形成所述化合物半导体的步骤。
22.如权利要求1所述的方法，其中在范围为500℃至低于600℃的温度发生所述形成所述化合物半导体的步骤。
23.如权利要求1所述的方法，还包括形成所述化合物半导体膜至大于临界厚度hc的厚度。
24.一种电子器件，包括：
衬底；
在所述衬底的第一表面之上沉积的化合物半导体膜，所述化合物半导体膜具有所述化合物半导体的第一半传导材料的高浓度，使得所述第一半传导材料在亚稳定状态；以及
取代地掺杂到所述化合物半导体中的应变补偿原子种类。
25.如权利要求24所述的电子器件，其中所述化合物半导体基本上由硅锗组成。
26.如权利要求24所述的电子器件，其中所述化合物半导体的所述第一半传导材料是锗。
27.如权利要求24所述的电子器件，其中所述应变补偿种类是碳。
28.一种用于制作异质结双极晶体管的方法，所述方法包括：
提供具有第一表面的衬底；
在所述衬底的所述第一表面之上形成硅锗膜，所述硅锗膜被选择为在亚稳定状态；以及
用应变补偿原子种类掺杂所述化合物半导体膜，所述应变补偿原子种类包括碳。
29.如权利要求28所述的方法，还包括调整所述第一半传导材料为具有梯形浓度分布形状。
30.如权利要求28所述的方法，还包括调整所述第一半传导材料为具有三角浓度分布形状。
31.如权利要求28所述的方法，还包括调整所述第一半传导材料为具有方形浓度分布形状。
32.如权利要求28所述的方法，还包括调整所述第一半传导材料为具有弯曲浓度分布。
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| KR (1) | KR20080075143A (zh) |
| CN (1) | CN101506943A (zh) |
| TW (1) | TW200802851A (zh) |
| WO (1) | WO2007056708A2 (zh) |
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| US7550758B2 (en) | 2006-10-31 | 2009-06-23 | Atmel Corporation | Method for providing a nanoscale, high electron mobility transistor (HEMT) on insulator |
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| US20090189159A1 (en) * | 2008-01-28 | 2009-07-30 | Atmel Corporation | Gettering layer on substrate |
| SE535380C2 (sv) * | 2011-01-31 | 2012-07-17 | Fairchild Semiconductor | Bipolär transistor i kiselkarbid med övervuxen emitter |
| US9048108B2 (en) * | 2012-05-22 | 2015-06-02 | International Business Machines Corporation | Integrated circuit with on chip planar diode and CMOS devices |
| US9385233B2 (en) * | 2013-06-26 | 2016-07-05 | Globalfoundries Inc. | Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide |
| US9093496B2 (en) | 2013-07-18 | 2015-07-28 | Globalfoundries Inc. | Process for faciltiating fin isolation schemes |
| US9349730B2 (en) | 2013-07-18 | 2016-05-24 | Globalfoundries Inc. | Fin transformation process and isolation structures facilitating different Fin isolation schemes |
| US9716174B2 (en) | 2013-07-18 | 2017-07-25 | Globalfoundries Inc. | Electrical isolation of FinFET active region by selective oxidation of sacrificial layer |
| US9224865B2 (en) | 2013-07-18 | 2015-12-29 | Globalfoundries Inc. | FinFET with insulator under channel |
| US9105677B2 (en) | 2013-10-22 | 2015-08-11 | International Business Machines Corporation | Base profile of self-aligned bipolar transistors for power amplifier applications |
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-
2005
- 2005-11-07 US US11/268,154 patent/US20070102834A1/en not_active Abandoned
-
2006
- 2006-11-03 WO PCT/US2006/060555 patent/WO2007056708A2/en active Search and Examination
- 2006-11-03 KR KR1020087013413A patent/KR20080075143A/ko not_active Application Discontinuation
- 2006-11-03 CN CNA2006800506182A patent/CN101506943A/zh active Pending
- 2006-11-03 JP JP2008540379A patent/JP2009521098A/ja not_active Withdrawn
- 2006-11-03 EP EP06839718A patent/EP1949420A2/en not_active Withdrawn
- 2006-11-06 TW TW095140935A patent/TW200802851A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007056708A3 (en) | 2009-05-07 |
| US20070102834A1 (en) | 2007-05-10 |
| KR20080075143A (ko) | 2008-08-14 |
| WO2007056708A2 (en) | 2007-05-18 |
| JP2009521098A (ja) | 2009-05-28 |
| EP1949420A2 (en) | 2008-07-30 |
| TW200802851A (en) | 2008-01-01 |
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