CN101496138A - 用于提供垂直晶片-到-晶片互连的金属填充的通孔结构 - Google Patents

用于提供垂直晶片-到-晶片互连的金属填充的通孔结构 Download PDF

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CN101496138A
CN101496138A CNA2007800282364A CN200780028236A CN101496138A CN 101496138 A CN101496138 A CN 101496138A CN A2007800282364 A CNA2007800282364 A CN A2007800282364A CN 200780028236 A CN200780028236 A CN 200780028236A CN 101496138 A CN101496138 A CN 101496138A
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wafer
hole
metal column
dielectric material
metal
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CN101496138B (zh
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H·B·波格
虞蓉卿
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International Business Machines Corp
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International Business Machines Corp
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Abstract

本发明提供了一种用于提供垂直晶片－到－晶片互连结构的通孔互连的制造方法，以及通过所述方法形成的垂直互连结构。本发明的方法仅使用金属柱用于垂直互连，由此金属柱不产生α辐射。本发明的方法包括插入步骤、加热步骤、减薄步骤以及背面处理。

Description

用于提供垂直晶片-到-晶片互连的金属填充的通孔结构
技术领域
本发明涉及半导体结构，更具体而言，涉及用于提供垂直晶片-到-晶片互连的可靠的金属填充的通孔(through via)结构。本发明还涉及用于提供垂直晶片-到-晶片互连的这样的可靠的金属填充的通孔结构的制造方法。
背景技术
在当前的半导体技术中，存在这样的趋势，即通过将二维(2D)芯片形式转变为三维(3D)芯片形式以增加半导体芯片的性能。这要求晶片-到-晶片之间是垂直互连。可以用通常被称为倒装晶片焊料连接或C4的尺寸减小的焊料凸起面阵列互连方案来制造垂直互连。然而，目前基于铅的C4本身就是α辐射源，其典型地妨碍了对无辐射互连材料的需求。因为α辐射可以在半导体器件中引入软错误，所以是不希望的。
另外，目前考虑的新的无铅C4主要由本身就是α辐射源的锡(Sn)构成。因此，这些新的C4不能确保可以消除α辐射问题。
用金属柱(stud)-到-衬垫方法可以获得另一种互连。在例如Pogge等人的美国专利No.6,444,560中描述了这种方法，被称为T&J(转移和接合)方法。典型的T&J互连包括用合金金属(优选Sn)覆盖的金属柱(优选Cu)。Sn帮助金属柱合金至相对的金属衬垫(典型地，同样为Cu)。关于前述C4技术，T&J方法包括同样为α辐射源的Sn。
为了提供将第二半导体芯片附着到第一半导体芯片的能力，需要第二芯片中的垂直通孔，以便产生从第一芯片通过第二芯片并到位于第二芯片之下的支撑衬底的电通路。已经有多个半导体制造商实践了通孔工艺。但是，高效通孔制造和通孔金属填充仍然是挑战。关注的是制造平滑的垂直通孔而不是某种形式的波纹状表面通孔。后者会在金属填充的通孔中引入金属空隙，这会导致不可接受的导电性改变。
根据上述讨论，需要提供一种用于制造改善的金属填充的通孔的可选的方法，以克服上述通孔问题并避免由C4或可能的基于Sn的合金T&J互连所产生的α辐射源问题。
发明内容
本发明提供了一种制造可靠的金属通孔的方法，所述方法在提供垂直晶片-到-晶片(或者芯片-到-芯片)互连结构时是有用的。根据本发明，提供了一种制造金属填充的通孔的方法，所述方法克服了通孔处理的上述缺点。另外，本发明的方法避免了使用C4或Sn基合金T&J互连时令人担忧的α辐射源问题。本发明的方法通过将金属柱用于垂直连接而实现了上述目的。也就是，本发明的方法利用了基本上由金属构成的柱；在存在本申请中的金属柱时，不使用Sn或其它α辐射产生源。
根据本发明，使用标准互连处理将金属柱电镀敷到第一半导体晶片(即，器件晶片)的下侧。然后将每个柱插入到第二半导体晶片的对应的聚酰亚胺涂敷的通孔中，以形成本发明的3D互连结构。根据本发明，第二半导体晶片可以具有或不具有位于其上的半导体电路，即器件。因此，根据本发明，第二半导体晶片可以用作能够吸收来自外部源的辐射的隔离物。在本发明的另一实施例中，第二半导体晶片具有位于其上的电路。在该具体的实施例中，典型地，至少一个互连层被设置在第一与第二半导体晶片之间。在上述讨论中，注意，第一和第二晶片还暗指包括第一和第二半导体芯片。在本发明的这样的实施例中，本发明的技术可以用于提供垂直芯片-到-芯片互连。
在随后的加热步骤期间，上述聚酰亚胺涂层用作流动并包围金属柱的接合材料。在本发明中使用的每个柱典型地，但不必总是，被设计成芽接(bud)到第二晶片的最终的通孔的底表面中。然而，不是所有的情况都需要芽接。也就是，每个金属柱的高度都可以略短于最终的通孔的深度。一旦插入并随后加热，聚酰亚胺流动并完全包围金属柱以用作金属柱与介质通孔衬里之间的应力缓冲。然后，一旦附着了第二晶片，便使用已有的平坦化方法减薄第二晶片。
本发明的方法避免了对合金金属柱的需要，并且制造了从第一晶片通过第二晶片的连续的金属通路。
一般而言，本发明的方法包括以下步骤：
提供第一晶片和第二晶片，所述第一晶片具有设置在其表面上的至少一个金属柱并且所述第二晶片包括至少一个聚酰亚胺涂敷的通孔；
将所述第一晶片的所述至少一个金属柱插入到所述第二晶片的所述至少一个聚酰亚胺涂敷的通孔中以提供组合的结构；
加热所述组合的结构以使相对的聚酰亚胺表面接合并开始流动以完全包围每个金属柱；
减薄所述第二晶片以暴露位于所述至少一个聚酰亚胺涂敷的通孔内的所述至少一个金属柱的表面；以及
在所述减薄的第二晶片的表面上形成构图的聚酰亚胺涂层和在所述至少一个金属柱的所述暴露的表面上形成金属衬垫。
注意，当使用含Si晶片时，通常使用氧化物并将其适当地构图以在例如形成聚酰亚胺和金属柱的其它处理之前保护晶片。
在本申请的优选的实施例中，所述方法包括如下步骤：
提供第一晶片和第二晶片，所述第一晶片具有设置在其表面上的至少一个Cu柱以及所述第二晶片包括至少一个聚酰亚胺涂敷的通孔；
将所述第一晶片的所述至少一个Cu柱插入到所述第二晶片的所述至少一个聚酰亚胺涂敷的通孔中以提供组合的结构；
加热所述组合的结构以使相对的聚酰亚胺表面接合并开始流动以完全包围每个Cu柱；
减薄所述第二晶片以暴露位于所述至少一个聚酰亚胺涂敷的通孔内的所述至少一个Cu柱的表面；以及
在所述减薄的第二晶片的表面上形成构图的聚酰亚胺涂层和在所述至少一个Cu柱的所述暴露表面上形成Cu衬垫。
本发明的上述方法避免了将金属柱合金化到金属衬垫的需要，然而，它们制造了从所述第一晶片(例如，器件晶片)穿过所述第二晶片(附着晶片或第二器件晶片)的连续的金属通路。
除了上述方法以外，本发明还提供了垂直晶片-到-晶片互连结构。更具体而言，本发明的垂直晶片-到-晶片互连结构包括：
第一晶片和第二晶片，所述第一晶片与第二晶片通过从所述第一晶片的表面延伸出的至少一个金属柱配合(mate)，所述至少一个金属柱从所述第一晶片的所述表面延伸到所述第二晶片的对应的通孔中，其中聚酰亚胺涂层存在于所述通孔中、在所述第一和第二晶片的配合表面上和在没有配合到所述第一晶片的所述第二晶片的另一表面上，并且其中所述至少一个金属柱提供了从所述第一晶片穿过所述第二晶片的连续的金属通路。
附图说明
图1是示例了在本发明中采用的第一晶片和第二晶片的图示表示(通过截面图)；
图2是示例了将设置在第一晶片背面的金属柱插入到在第二晶片中形成的涂敷有聚酰亚胺的通孔之后的结构的图示表示(通过截面图)；
图3是示例了在附着和减薄之后的图2的结构的图示表示(通过截面图)；
图4是示例了在用聚酰亚胺和金属衬垫进行了背面处理之后的图3的结构的图示表示(通过截面图)；
图5A-5C是示例了可选的实施例的图示表示(通过截面图)，其中没有将金属柱设计成完全芽接到通孔的底部；以及
图6A-6D是示例了本发明的另一实施例的图示表示(通过截面图)，其中互连层被设置在第一晶片与第二晶片之间。
具体实施方式
本申请描述了一种仅利用金属柱来制造垂直晶片-到-晶片互连结构的方法以及由该方法形成的结构，现在将参考下面的描述和本申请的附图更详细的描述本申请。注意，提供本申请的附图用于示例的目的，因此没有按比例绘制。
在随后的描述中，为了提供对本发明的全面理解，阐述了大量的具体细节，例如特定的结构、部件、材料、尺寸、处理步骤和技术。然而，本领域的技术人员应该理解，本发明可以在没有这些特定细节的情况下采用可行的可选方法选择进行实施。在另一实例中，为了避免模糊本发明，没有详细地描述公知的结构或处理步骤。
应该理解，当将例如层、区域或衬底的元件描述为“在另一元件上”或“在另一元件之上”时，其可以直接在其它元件上或者还可以存在中间元件。相反，当将元件描述为“直接在另一元件上”或“直接在另一元件之上”时，则不存在中间元件。还应该理解，当将元件描述为“在另一元件下”或“在另一元件之下”时，其可以直接在其它元件下或之下，或者可以存在中间元件。相反，当将元件描述为“直接在另一元件下”或“直接在另一元件之下”时，则不存在中间元件。
如上所述，本发明提供了一种利用修改的转移和接合方法制造可靠金属填充的通孔的方法以提供垂直晶片-到-晶片(或芯片-到-芯片)互连结构，其中避免了金属柱的合金化。在本发明中，柱基本上由不是α辐射源的导电金属构成。概括而言，本发明的方法包括首先提供第一晶片和第二晶片。根据本发明，第一晶片具有到这样的表面的至少一个金属柱互连，该表面典型地但不必总是与半导体器件相对，以及第二晶片包括至少一个聚酰亚胺涂敷的通孔。第二半导体晶片在其中可以具有或不具有半导体线路。接下来，将第一晶片的至少一个金属柱插入到第二晶片的至少一个聚酰亚胺涂敷的通孔中。在完全插入之后，将现在组合的第一和第二晶片加热到这样的温度，该温度会引起相对的聚酰亚胺表面接合并开始流动以完全包围每个金属柱。然后，对第二晶片实施减薄步骤以暴露位于至少一个聚酰亚胺涂敷的通孔中的至少一个金属柱的表面。然后，通过涂敷在减薄的第二晶片的表面上的聚酰亚胺和在至少一个金属柱的暴露的表面上的金属衬垫来进行背面处理。
现在根据图1-4描述上面简要描述的本发明的制造方法。可以注意到，在这些附图中示出了金属柱完全芽接至通孔的底部。虽然示出了该特定的实施例，但是本发明还构思了图5A-5C所示出的实施例。在本申请的这些附图和该实施例中，金属柱被设计成没有完全芽接至通孔的底部。另外，本发明还构思了一个实施例，其中将至少一个互连层设置在第一与第二晶片之间，优选这两个晶片都包含半导体器件。
还应该注意，没有在本申请提供的附图中示出所有的工艺细节。例如，在这里没有总是示出或描述使用氧化物绝缘第一和第二晶片表面。而且，在本申请中没有示出或描述在第一晶片和可选的第二晶片上形成器件。另外，在进行了本发明的各种处理步骤之后，可以在第二晶片的下侧进行附加的处理(没有更详细的示出或描述)。例如，优选在形成接触衬垫之前，在第二晶片的下侧形成构图的氧化物。在一些实施例中，在金属柱周围形成宽接触衬垫以确保良好的金属接触和用于衬底的更大的封装衬垫连接所需的更大的区域。
现在，参考图1-4，其中示出了本发明的第一实施例。在该实施例中，金属柱被设计成完全芽接至通孔的底部。术语“完全芽接”指金属柱被设计成具有一高度，该高度确保金属柱的顶表面与通孔的底壁部分直接接触。优选使用包括介质材料和聚酰亚胺的通孔衬里为底壁部分加衬里。
图1示例了本发明的第一步骤，其中提供第一晶片(此后称为器件晶片)10和第二晶片(此后称为附着晶片)20。根据本发明的该实施例，器件晶片10是其中形成了至少一个半导体器件(未示出)的晶片，而附着晶片20是隔离物，该隔离物用于吸收来自外部源例如C4和/或陶瓷衬底的α辐射。如图1所示，器件晶片10包括具有位于其表面上的构图的第一介质材料14的第一半导体衬底12。构图的第一介质材料14与位于其上的聚酰亚胺涂层16或其它类似的接合材料的构图相似。如所示，器件晶片10还包括位于第一半导体衬底12的表面上并设置在构图的第一介质材料14和聚酰亚胺涂层16之间的至少一个金属柱18。
附着晶片20包括第二半导体衬底22，第二半导体衬底22具有在其中形成的至少一个通孔24。注意，在本申请的此刻，至少一个通孔24典型地没有完全延伸穿过附着晶片。附着晶片20还包括为至少一个通孔24的暴露的表面(包括底和侧壁)以及位于邻近的通孔之间的第二半导体衬底22的表面加衬里的第二介质材料26。聚酰亚胺涂层28被设置在第二介质材料26上以便覆盖存在于至少一个通孔24的侧壁上以及邻近通孔24的第二衬底22的暴露的表面上的介质材料。
利用本领域的技术人员公知的技术制造器件晶片10。例如，在衬底和器件处理之后，向典型地与半导体器件相对的第一半导体衬底12的表面施加第一介质材料14。第一半导体衬底12包括任何的半导电材料，包括但不仅限于：Si、Ge、SiGe、SiC、SiGeC、Ga、GaAs、InAs、InP和所有其它III/V或II/VI化合物半导体。第一半导体衬底12还可以包括有机半导体或如Si/SiGe、绝缘体上硅(SOI)或绝缘体上SiGe(SGOI)的分层半导体。在本发明的一些实施例中，优选第一半导体衬底12由含Si半导体材料即包括硅的半导体材料构成。第一半导体衬底12可以是掺杂、未掺杂的或其中包含掺杂和未掺杂的区域。
当使用SOI衬底时，这些衬底包括至少部分地通过掩埋绝缘层分离的顶或底半导体例如Si层。掩埋绝缘层包括，例如晶体或非晶氧化物、氮化物或其任何组合。优选地，掩埋绝缘层是氧化物。典型地，在层转移方法的初始阶段期间或在离子注入和退火工艺期间形成掩埋绝缘层，例如，SIMOX(通过离子注入氧来分离)。
第一半导体衬底12可以具有单一晶体取向或者还可以使用可选的具有不同晶体取向表面区域的混合半导体衬底。混合衬底允许在可以增强形成的特定器件的性能的特定的晶体取向上制造器件。例如，混合衬底允许提供一种结构，其中在(110)晶体取向上形成pFET而在(100)晶体取向上形成nFET。当使用混合衬底时，其可以具有类似于SOI的特性、类似于体的特性或类似于SOI和体的组合的特性。
第一介质材料14包括氧化物、氧氮化物、氮化物或其多层。在本发明的一个实施例中，第一介质材料14包括例如SiO2的氧化物。第一介质材料14可以通过例如化学气相淀积(CVD)、等离子体增强化学气相淀积(PECVD)、原子层淀积(ALD)、蒸发、化学溶液淀积和其它类似的淀积技术形成。可选地，可以通过例如氧化、氮化或其组合的热工艺来形成第一介质材料14。
第一介质材料14的厚度可以根据其形成技术以及所使用的介质材料的类型改变。典型地，第一介质材料14具有约100到约2000nm的厚度，优选具有约500到约1000nm的厚度。
在第一介质材料14的顶上形成热塑性聚酰亚胺(此后称为“聚酰亚胺”)涂层16。利用包括例如CVD、PECVD、蒸发和旋涂的常规淀积工艺形成聚酰亚胺涂层16。聚酰亚胺涂层16用作粘合或接合剂，用于将器件晶片10附着到附着晶片20上。聚酰亚胺涂层16典型地具有约500到约10,000nm的淀积后的厚度，更典型具有约1000到约3000nm的厚度。
在本发明中优选使用的材料是热塑性聚酰亚胺，因为它是延展性的，可以吸收应力并且倾向于具有大于在本申请中使用的半导体衬底的热膨胀(CTE)系数的CTE。
在形成第一介质材料14和聚酰亚胺涂层16之后，在第一介质材料14的暴露的表面上(如果不存在聚酰亚胺涂层)或者在聚酰亚胺涂层16的顶上(如果存在聚酰亚胺涂层)设置构图的光致抗蚀剂(未示出)。通过淀积和光刻形成构图的光致抗蚀剂。淀积步骤包括常规淀积方法，包括例如CVD、PECVD、旋涂和蒸发。光刻方法包括将施加的光致抗蚀剂暴露到辐射图形并利用常规抗蚀剂显影剂显影曝光的抗蚀剂。构图的光致抗蚀剂包括暴露层16或层14的上表面的开口。然后，利用蚀刻方法除去这些开口中的暴露的材料。可以利用干法蚀刻(包括反应离子蚀刻、离子束蚀刻、等离子体蚀刻和激光烧蚀)、湿法蚀刻或其任何组合。蚀刻提供了到第一半导体衬底12的开口，在其中形成至少金属柱18。在蚀刻之后，利用常规的抗蚀剂显影剂剥离构图的光致抗蚀剂。
然后，利用本领域的技术人员公知的任何的常规电镀敷方法将金属柱18形成到开口中。如本领域的技术人员所公知的，金属柱18与存在于器件晶片10上的Cu衬垫或构图的保护层接触。在本申请的附图中即没有示出Cu衬垫也没有示出构图的保护材料。根据本发明，金属柱18由不是α辐射源的导电金属构成。非α辐射源材料的导电金属的实例包括，例如，Cu、Al、W和Au。在上面列出的各种导电金属中，在一些实施例中优选导电金属由Cu构成。
形成的金属柱18的高度既可以设计成芽接到附着衬底的通孔的底壁部分，也可以设计成不芽接到通孔的底壁部分。在这些图中示出了本发明的前面的实施例，而图5A-5C示出了本发明的后面的实施例。
如上所述并且如图1所示，附着晶片20包括具有至少一个聚酰亚胺涂敷的通孔的第二半导体衬底22。第二半导体衬底22可以包括与器件晶片10的第一半导体衬底12相同或不同的半导体材料。典型地，第二半导体衬底22是含Si半导体衬底。
然后，利用上面描述过的常规光刻和蚀刻，将至少一个通孔24形成到附着晶片20的第二半导体衬底22中。如前面指出的，本发明此时形成的通孔24典型地没有延伸穿过第二半导体衬底22的整个厚度。在形成了通孔之后，利用本领域的技术人员公知的常规抗蚀剂剥离方法剥离用于形成通孔的抗蚀剂。
在提供了至少一个通孔24之后，随后在通孔24的所有暴露的表面(侧壁和底壁)以及位于邻近通孔24的第二衬底22的暴露的表面上形成介质材料26。在附着晶片20中用作通孔衬里的介质材料26可以包括与器件晶片的第一介质材料14相同或不同的介质材料。在一些实施例中，优选介质材料26由例如SiO2的氧化物构成。注意，可以利用描述的用于第一介质材料14的上述技术中的一种来形成介质材料26，并且介质材料26的厚度可以落入上述用于第一介质材料14的范围内。
接下来，在位于至少一个通孔24内的介质材料26的侧壁表面上以及位于邻近该通孔24的第二半导体衬底22的部分上的介质材料26的顶上形成热塑性聚酰亚胺(此后称为“聚酰亚胺”)涂层28。如上所述形成聚酰亚胺涂层28并且其厚度也在上述的范围内。
如上所述并且如图1所示，在提供器件晶片10和附着晶片20之后，聚集这两个晶片以便将至少一个金属柱18插入到至少一个通孔24中。例如在图2中示出了在插入之后形成的产生的组合结构。注意，在本发明的该具体的实施例中，金属柱18芽接到通孔24的底壁部分。也就是，每一个金属柱18的上表面紧密接触存在于通孔24中的第二介质材料26。通过向器件晶片10或附着晶片20中的至少一个或更优选两个晶片施加外力来进行插入工艺。
在提供图2示出的组合的结构之后，加热到可以接合相对的聚酰亚胺表面并且同时使聚酰亚胺流动以完全包围每个金属柱18的温度。在能够使聚酰亚胺流动并包围金属柱而不损坏器件晶片10中的器件的温度下进行本申请的该加热步骤。具体而言，通过将图2中示出的结构加热到小于约400℃的温度来实现聚酰亚胺的流动和包围金属柱，而不会损坏器件晶片10中的器件。更具体而言，在约250℃到约375℃的温度下进行本发明的加热步骤。该加热步骤的时长可以改变并依赖于所使用的加热技术的类型。
根据本发明，在存在惰性气氛并且随后在压力下进行加热步骤。可以在本发明中使用的惰性气氛的实例包括He、Ar、Ne、Xe及其混合，例如He和Ar的混合物。
注意，在加热步骤期间可以向被转移并接合到一起的一个或两个晶片施加外力。
在加热之后，聚酰亚胺涂层硬化并包围在第二晶片的至少一个通孔内的至少一个金属柱。
在利用上述处理步骤将两个晶片接合到一起之后，然后，利用常规平坦化方法减薄附着晶片的背面，提供图3示出的结构。如图3所示，附着晶片20的减薄暴露了位于至少一个聚酰亚胺28涂敷的通孔24中的至少一个金属柱18的表面。在本发明中可以使用包括研磨和/或化学机械抛光(CMP)的常规平坦化方法来减薄附着晶片20。还可以单独使用湿法化学蚀刻方法或结合研磨和/或CMP来减薄附着晶片20。
图4示出了在用另一聚酰亚胺涂层30和金属衬垫32进行了背面处理之后形成的结构。如上所述形成聚酰亚胺涂层30。通过各种淀积技术、光刻和蚀刻，来形成优选包括Cu或其他类似金属的金属衬垫32。
注意，背面聚酰亚胺涂层30有助于填充在通孔中沿柱侧壁的任何可能的剩余空隙。还可以改变柱和通孔的特定的几何形状以制造“漏斗状”过孔(未示出)和锥形金属柱(同样未示出)。也可以根据具体需要和设计来改变处理顺序细节。
现在，参考图5A-5C，其示出了本申请的另一实施例。在该实施例中，设计金属柱18具有不能芽接到通孔24的底壁部分的高度。图5A示出了分别在插入和接合之后的初始的两个晶片10和20。图5B示出了在减薄附着晶片20之后的结构。图5C示出了用另一聚酰亚胺涂层30和金属衬垫32进行背面处理之后形成的结构。如上所述形成聚酰亚胺涂层30。注意，除了金属柱的高度被设计成比图1-4中示出的实施例中所使用的高度小以外，用于该第二实施例的所有材料和工艺细节都与上面所描述的相同。该特定的实施例，示例了在形成垂直互连结构时在本发明中所使用的初始金属柱18的高度并不重要。
在上面两个实施例中，第二晶片20不包括任何半导体电路，即器件。在这些实施例中，第二晶片20仅用作第一晶片10与模块(未示出)之间的隔离物。隔离物(即，第二晶片20)的目的是吸收任何的α辐射发射，该α辐射发射由用于将模块互连到本发明的结构的紧邻和/或邻近的C4连接发出。
现在，参考图6A-6D，其描述了本申请的另一实施例。在本发明的该实施例中，本发明的结构包括设置在均包括半导体器件的第一与第二晶片之间的至少一个互连层。图6A示例了包括位于半导体衬底12的表面上的器件区域50的第一晶片10。器件区域50包括一个或多个半导体器件。第一晶片10还包括金属柱18、第一介质层14和聚酰亚胺涂层16。还在层14和16内示出了金属接触52。金属接触52与半导体器件的选定区域接触，例如，场效应晶体管的源极/漏极区域和栅极。通过首先在衬底12上形成半导体器件(未示出)来制造图6A中示出的第一晶片10。下一步，如上所述形成第一介质层14、聚酰亚胺涂层16和接触柱18，接着，通过光刻和蚀刻形成金属接触开口。然后，利用常规淀积方法在接触开口中形成例如Cu、Al、W或AlCu的接触金属。接触金属典型地延伸到接触开口的外部。可选地，可以在金属柱18之前制造金属接触52。
图6A还示出了包括第二半导体衬底22的第二晶片20的存在，第二半导体衬底22包括位于其表面上的半导体器件区域54。第二晶片20还包括至少一个通孔24、第二介质材料26、聚酰亚胺涂层28、接触开口56和接触衬垫58。接触衬垫58由本领域公知的例如Cu的常规金属构成。如上所述，通过首先在第二衬底22上形成半导体器件区域54和金属接触衬垫58并随后形成至少一个过孔开口24来形成图6A示出的第二晶片20。在本发明的一些实施例中，上述处理顺序可以颠倒。接下来，利用上面描述的用于那些层的技术形成层26和28，然后通过光刻和蚀刻形成接触开口56。
图6B示出了将图6A示例的两个晶片如上所述聚集到一起并加热之后的结构。注意，包括接触衬垫58、金属接触52以及第一和第二介质14和26的互连层被设置在第一与第二晶片之间。在本发明的该实施例中，通过上述T&J互连技术，接着插入金属柱18来实现将接触衬垫58同时接合到金属接触52。
图6C示出了在利用上述处理技术减薄了第二晶片20之后的结构。
图6D示出了在利用上述技术用另一聚酰亚胺涂层30和金属衬垫32背面处理之后的结构。
虽然参考其优选的实施例具体示出并描述了本发明，但是本领域的技术人员应该明白，在不脱离本发明的精神和范围的情况下，可以对形式、结构、工艺顺序和细节做出前述和其它改变。因此，旨在本发明不局限于描述和示例的具体形式和细节，而是落入所附权利要求的范围内。
工业适用性
本发明可以工业应用于半导体结构的制造，更具体而言，可以适用于提供晶片-到-晶片或芯片-到-芯片的互连领域。

Claims (30)

1.一种制造垂直晶片-到-晶片互连结构的方法，包括以下步骤：
提供第一晶片(10)和第二晶片(20)，在第一半导体衬底(12)上的所述第一晶片(10)具有设置在其表面上的至少一个金属柱(18)，并且在第二半导体衬底(22)上的所述第二晶片(20)包括至少一个聚酰亚胺涂敷的通孔(24)；
将所述第一晶片(10)的所述至少一个金属柱(18)插入到所述第二晶片(20)的所述至少一个聚酰亚胺涂敷的通孔(24)中以提供组合的结构；
加热所述组合的结构以使相对的聚酰亚胺表面接合并开始流动以完全包围每个金属柱(18)；
减薄所述第二晶片(20)以暴露位于所述至少一个聚酰亚胺涂敷的通孔(24)内的所述至少一个金属柱(18)的表面；以及
在所述减薄的第二晶片的表面上形成构图的聚酰亚胺涂层和在所述至少一个金属柱(18)的所述暴露的表面上形成金属衬垫。
2.根据权利要求1的方法，其中提供所述第一晶片(10)包括在所述第一半导体衬底(12)的表面上淀积介质材料，在所述介质材料(14)上形成聚酰亚胺涂层(16)，在所述介质材料(14)和所述聚酰亚胺涂层(16)中提供开口，以及通过所述开口电镀敷导电金属。
3.根据权利要求1的方法，其中所述至少一个金属柱包括Cu、Al、W或Au。
4.根据权利要求3的方法，其中所述至少一个金属柱包括Cu。
5.根据权利要求1的方法，其中提供所述第二晶片(20)包括在所述第二半导体衬底(22)中形成至少一个通孔(24)，使用介质材料(26)为所述通孔(24)的暴露的表面和所述第二半导体衬底(22)的部分加衬里，以及在所述介质材料(26)的所有暴露的表面上形成聚酰亚胺涂层(28)。
6.根据权利要求1的方法，其中在所述插入之后，每个所述金属柱直接接触为每个通孔的底壁部分加衬里的介质材料。
7.根据权利要求1的方法，其中在所述插入之后，每个所述金属柱不直接接触为每个通孔的底壁部分加衬里的介质材料。
8.根据权利要求1的方法，其中在小于约400℃的温度下进行所述加热。
9.根据权利要求1的方法，其中通过研磨、化学机械抛光、湿法蚀刻或其组合进行所述减薄。
10.根据权利要求1的方法，其中所述至少一个金属柱包括Cu并且所述至少一个金属衬垫包括Cu。
11.根据权利要求1的方法，其中所述第一晶片包括设置在半导体衬底的表面上的半导体器件。
12.根据权利要求11的方法，其中所述第二晶片包括设置在另一半导体衬底的表面上的半导体器件，并且所述第一和第二晶片通过互连层和接合的聚酰亚胺层分离。
13.一种制造垂直晶片-到-晶片互连结构的方法，包括以下步骤：
提供第一晶片和第二晶片，所述第一晶片具有设置在其表面上的至少一个Cu柱并且所述第二晶片包括至少一个聚酰亚胺涂敷的通孔；
将所述第一晶片的所述至少一个Cu柱插入到所述第二晶片的所述至少一个聚酰亚胺涂敷的通孔中以提供组合的结构；
加热所述组合的结构以使相对的聚酰亚胺表面接合并开始流动以完全包围每个Cu柱；
减薄所述第二晶片以暴露位于所述至少一个聚酰亚胺涂敷的通孔内的所述至少一个Cu柱的表面；以及
在所述减薄的第二晶片的表面上形成构图的聚酰亚胺涂层和在所述至少一个Cu柱的所述暴露的表面上形成Cu衬垫。
14.根据权利要求13的方法，其中提供所述器件晶片包括在半导体衬底的表面上淀积介质材料，在所述介质材料上形成聚酰亚胺涂层，在所述介质材料和所述聚酰亚胺涂层中提供开口，以及通过所述开口电镀敷Cu。
15.根据权利要求13的方法，其中提供所述第二晶片包括在半导体衬底中形成至少一个通孔，使用介质材料为所述通孔的暴露的表面和所述半导体衬底的部分加衬里，以及在所述介质材料的至少侧壁上形成聚酰亚胺涂层。
16.根据权利要求13的方法，其中在所述插入之后，每个所述Cu柱直接接触为每个通孔的底壁部分加衬里的介质材料。
17.根据权利要求13的方法，其中在所述插入之后，每个所述Cu柱不直接接触为每个通孔的底壁部分加衬里的介质材料。
18.根据权利要求13的方法，其中在小于约400℃的温度下进行所述加热。
19.根据权利要求13的方法，其中通过研磨、化学机械抛光、湿法蚀刻或其组合进行所述减薄。
20.一种垂直晶片-到-晶片互连结构，包括：
第一晶片和第二晶片，所述第一晶片与第二晶片通过从所述第一晶片的表面延伸出的至少一个金属柱配合，所述至少一个金属柱从所述第一晶片的所述表面延伸到所述第二晶片的对应的通孔中，其中聚酰亚胺涂层存在于所述通孔中、在所述第一和第二晶片的配合表面上和在没有配合到所述第一晶片的所述第二晶片的另一表面上，并且其中所述至少一个金属柱提供了自所述第一晶片通过所述第二晶片的连续的金属通路。
21.根据权利要求20的垂直晶片-到-晶片互连结构，其中所述第一晶片和所述第二晶片包括相同或不同的半导体材料。
22.根据权利要求21的垂直晶片-到-晶片互连结构，其中所述第一晶片和所述第二晶片中的每一个都包括含Si半导体。
23.根据权利要求20的垂直晶片-到-晶片互连结构，其中介质材料为每一个所述通孔的侧壁加衬里。
24.根据权利要求23的垂直晶片-到-晶片互连结构，其中所述介质材料是氧化物。
25.根据权利要求20的垂直晶片-到-晶片互连结构，还包括在每个所述至少一个金属柱的暴露的表面上的金属衬垫，所述金属衬垫位于所述第二晶片的所述表面的顶上。
26.根据权利要求20的垂直晶片-到-晶片互连结构，其中所述至少一个金属柱包括选自Cu、Al、W或Au的导电金属。
27.根据权利要求26的垂直晶片-到-晶片互连结构，其中所述导电金属是Cu。
28.根据权利要求25的垂直晶片-到-晶片互连结构，其中所述金属衬垫由Cu构成并且每个所述金属柱都由Cu构成。
29.根据权利要求20的垂直晶片-到-晶片互连结构，其中所述第一晶片包括设置在半导体衬底的表面上的半导体器件。
30.根据权利要求29的垂直晶片-到-晶片互连结构，其中所述第二晶片包括设置在另一半导体衬底的表面上的半导体器件，并且所述第一和第二晶片通过互连层分离。
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CN110010478A (zh) * 2018-10-10 2019-07-12 浙江集迈科微电子有限公司 一种具有电磁屏蔽功能的射频微系统及成型工艺
CN110010478B (zh) * 2018-10-10 2021-01-26 浙江集迈科微电子有限公司 一种具有电磁屏蔽功能的射频微系统及成型工艺

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KR20090031903A (ko) 2009-03-30
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EP2047500A1 (en) 2009-04-15
TWI417990B (zh) 2013-12-01
US7344959B1 (en) 2008-03-18
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CN101496138B (zh) 2011-03-16

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