TWI417990B - 提供垂直晶圓對晶圓互聯之填充金屬的貫通介層結構 - Google Patents

提供垂直晶圓對晶圓互聯之填充金屬的貫通介層結構 Download PDF

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Publication number
TWI417990B
TWI417990B TW096125172A TW96125172A TWI417990B TW I417990 B TWI417990 B TW I417990B TW 096125172 A TW096125172 A TW 096125172A TW 96125172 A TW96125172 A TW 96125172A TW I417990 B TWI417990 B TW I417990B
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Taiwan
Prior art keywords
wafer
metal
dielectric material
copper
polyimide
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TW096125172A
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English (en)
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TW200822284A (en
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H Bernhard Pogge
Roy R Yu
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Ibm
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Publication of TW200822284A publication Critical patent/TW200822284A/zh
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Description

提供垂直晶圓對晶圓互聯之填充金屬的貫通介層結構
本發明係關於一種半導體結構，而且更特別地關於一種提供垂直晶圓對晶圓互聯之填充金屬的貫通介層結構。同時，本發明亦關於一種提供垂直晶圓對晶圓互聯之填充可信賴金屬貫通介層結構的方法。
目前半導體技術的趨勢由二維晶片形式轉移至三維晶片形式以增加半導體效能。這需要晶圓對晶圓的垂直互聯結構。垂直互聯結構可使用較小尺寸錫鉛凸塊區域陣列互聯形式而產生，這種通常通稱為覆晶鉛錫連接(flip－flop solder connection)或者C4。然而，目前含鉛C4是α輻射源，而且通常與無輻射互聯材料的需求相衝突。因為α輻射可引進軟錯誤(soft error)至半導體裝置，所以α輻射是不受歡迎的。必須注意並非所有半導體設計皆受到α輻射影響。
再者，目前正考慮新的無鉛C4主要含有錫(Sn)，其本身可能是α輻射源。因此，這些新的無鉛C4並無法消除α輻射源的問題。
另一種互聯結構是以金屬凸柱對金屬墊方式(metal stud－to－pad)達成。例如美國專利6,444,560，Pogge等人，描述此方法稱為轉移與接合法(T&J)。典型的T&J互聯結構通常包含使用合金金屬(通常為錫)塗佈的一金屬凸柱(較佳是銅)。錫有助於金屬凸柱與相對的金屬墊(也是銅)產生合金作用。如先前描述的C4技術，T&J法包含可當作α輻射源的錫。
考慮到附接第二半導體晶片至第一半導體晶片的能力係在第二半導體晶片需要一垂直貫通介層，以便具有從第一半導體晶片通過第二半導體晶片而且到達置於第二半導體晶片下方之一支撐基板的一電流路徑。貫通介層(through via)製程已由數個半導體製造商進行。然而，有效的產生貫通介層與貫通介層的填充金屬仍然是一項挑戰。憂慮的是確保平滑的垂直貫通介層的產生，而不是某些種波浪表面的貫通介層。後者在填充金屬貫通介層內會產生金屬孔洞，而導致不良導電變異值。
由此看來，需要提供一種產生改良填充金屬的貫通介層之供選擇之方法，以克服上述貫通介層的憂慮以及避免C4或者含錫合金T&J互聯結構所產生的α輻射源的問題。
本發明提供一種製造可信賴金屬貫通介層的方法，其有效提供垂直晶圓對晶圓(或者甚至晶片對晶片)互聯結構。本發明提供一種製造填充金屬貫通介層的方法，以克服上述貫通介層製程的缺點。再者，本發明方法避免α輻射源問題，而且當使用C4或含錫合金T&J互聯結構時，通常受到α輻射源問題所困擾。本發明方法使用用於垂直連接的金屬凸柱達成上述目的。也就是說，本發明方法使用含有金屬的凸柱；使用本發明的金屬凸柱情形下，不使用錫或其他α輻射產生源。
根據本發明，使用標準互聯製程將金屬凸柱電鍍至第一半導體晶圓(即，裝置晶圓)的底面。隨後，每一凸柱插入第二半導體晶圓的相對應塗佈聚醯亞胺的貫通介層，以形成本發明的三維互聯結構。根據本發明，第二半導體晶圓可具有或者可不具半導體電路(即裝置)於其上。因此，在本發明中，第二半導體晶圓可充當吸收來自外部來源的輻射之間隔層(spacer)。於本發明之另一具體實施例，第二半導體晶圓可具有電路於其上。在這特別的實施例中，至少一互聯層通常設置於第一半導體晶圓與第二半導體晶圓間。於上述的討論中，必須注意第一半導體晶圓與第二半導體晶圓可暗示包含第一半導體晶片與第二半導體晶片。在本發明這樣的實施例中，此發明的技術係用以提供一垂直晶片對晶片(chip－to－chip)互聯。
上述聚醯亞胺塗佈層作為結合材料，而結合材料在隨後加熱步驟期間產生流動並且圍繞金屬凸柱。本發明使用的每一金屬凸柱通常是，但是未必一定芽出(bud)在第二半導體晶圓的最終貫通介層的底部表面。無論如何，芽出凸柱不是在所有情況下都是必要的。也就是說，每一金屬凸柱的高度稍微短於最終貫通介層的深度。一旦插入然後加熱，聚醯亞胺流動且完全圍繞金屬凸柱，以當作金屬凸柱與貫通介層襯層間的應力緩衝層。一旦附接金屬凸柱，即以目前平坦製程薄化第二半導體晶圓。
本發明避免將金屬凸柱合金化，而且產生由第一半導體晶圓至第二半導體晶圓的連續金屬通路。
本發明的方法包含：提供一第一晶圓與一第二晶圓，第一晶圓具有至少一金屬凸柱設置於第一晶圓的表面上，而且第二晶圓具有至少一塗佈聚醯亞胺的貫通介層；插入第一晶圓的至少一金屬凸柱於第二晶圓的至少一塗佈聚醯亞胺的貫通介層，以提供一組合結構；加熱組合結構，使得相對的聚醯亞胺表面進行結合以及啟始流動以完全圍繞每一金屬凸柱；薄化第二晶圓以暴露出位於至少一塗佈聚醯亞胺的貫通介層內的金屬凸柱的表面；以及形成一圖案化聚醯亞胺塗佈層在薄化的第二晶圓表面上，並形成一金屬墊在至少一金屬凸柱的暴露表面上。
必須注意當使用含矽晶圓時，通常使用氧化物而且加以適當圖案化(patterned)以便在其他製程(例如形成聚醯亞胺與金屬凸柱之前)保護晶圓。
根據本發明較佳實施例，本發明方法包含步驟：提供一第一晶圓與一第二晶圓，第一晶圓具有至少一銅凸柱設置於第一晶圓的表面上，而且第二晶圓具有至少一塗佈聚醯亞胺的貫通介層；插入第一晶圓的至少一銅凸柱於第二晶圓的至少一塗佈聚醯亞胺的貫通介層，以提供一組合結構；加熱組合結構，使得相對的聚醯亞胺表面進行結合以及啟始流動以完全塗佈每一銅凸柱；薄化第二晶圓以暴露出位於至少一塗佈聚醯亞胺的貫通介層內的至少一銅凸柱的表面；以及形成一圖案化聚醯亞胺塗佈層在薄化的第二晶圓表面，而且形成一銅墊在至少一銅凸柱的暴露表面上。
上述本發明之方法，係避免合金化金屬凸柱於金屬墊，而且產生由第一半導體晶圓(即，裝置晶圓)至第二半導體晶圓(附接晶圓或第二裝置晶圓)的一連續金屬通路。
除上述方法之外，本發明也提供一垂直的晶圓對晶圓互聯結構。明確地說，本發明的垂直的晶圓對晶圓互聯結構，包含：一第一晶圓與一第二晶圓，係藉由至少一金屬凸柱相匹配，而金屬凸柱由第一晶圓的表面延伸且延伸至第二晶圓的相對應貫通介層，其中一聚醯亞胺塗佈層呈現在貫通介層、第一晶圓與第二晶圓的配合表面以及第二晶圓不與第一晶圓配合的另一表面，且其中至少一金屬凸柱提供由第一晶圓至第二晶圓的一連續金屬通路。
本發明描述製造一垂直晶圓對晶圓互聯結構的方法，而且僅使用金屬凸柱以及由本發明方法形成的結構。參閱以下描述與本發明的附圖，更詳細描述本發明。必須注意本發明的圖式係用於說明，而且不按照比例繪製。
以下詳細說明，提出許多特定項目，例如特殊結構、元件、材質、尺寸、製造步驟與技術，以便完全瞭解本發明。然而，應該明瞭熟習此技藝者不需要這些明確的詳述，就可實施之替換的製程。換言之，不描述熟知的結構或製程步驟，以避免模糊本發明內容。
應該明瞭當一元件作為一層、一區域或一基板設置於其他元件“上面”或“上方”，此元件可直接在其他元件上或者可能出現中間元件。相反地，當一元件稱為設置於其他元件“直接在上面”或者“直接在上方”，則不出現中間元件。應該明瞭當一元件稱為在其他元件“下表面”或“下方”，此元件可能直接在其他元件的下表面或者在下方，或者中間元件係可能出現。相反地，當一元件稱為設置於其他元件“直接在下表面”或者“直接在下方”，則不出現中間元件。
如上所述，本發明提供一種製造填充金屬貫通介層，使用轉移與接合法(T&J)以產生一垂直晶圓對晶圓(或者晶片對晶片)互聯結構，其中可避免金屬合金化(alloying)。在本發明中，金屬凸柱包含非α輻射產生源的一導電性金屬。一般來說，本發明的方法包含：首先提供一第一晶圓與一第二晶圓。根據本發明，第一晶圓具有至少一金屬凸柱互聯至一表面，而表面通常但未必總是相對的半導體裝置，而且第二晶圓具有至少一塗佈聚醯亞胺的貫通介層。第二晶圓可具有或者不具有半導體電路。其次，第一晶圓的至少一金屬凸柱係插入第二晶圓的至少塗佈聚醯亞胺的貫通介層。在完全插入後，加熱結合後的第一晶圓與第二晶圓到達一溫度，此溫度致使相對的聚醯亞胺表面結合並啟始流動以完全圍繞每一金屬凸柱。然後，薄化步驟實施在第二晶圓上，以暴露出置於至少一塗佈聚醯亞胺的貫通介層內的至少一金屬凸柱的表面。隨後，實施具有已薄化第二晶圓表面的聚醯亞胺塗佈層以及至少一金屬凸柱的暴露表面上的金屬墊的背面製程。
上述本發明的製造方法係相關於圖1－4而描述。應該注意圖式顯示金屬凸柱完全芽出至貫通介層的底部。雖然顯示特定實施例，但是本發明也考慮圖5A－5C的實施例。在本發明的圖式與實施例中，金屬凸柱並不完全突出至貫通介層的底部。此外，本發明也考慮一實施例，其中至少一貫通結構設置於第一晶圓與第二晶圓間，而且兩個晶圓通常包含半導體裝置。
更進一步注意到並非所有製程細節皆顯示於本發明的圖式中。例如，具有氧化物的第一晶圓與第二晶圓的表面絕緣性未必顯示於圖式中。再者，在第一晶圓以及選擇性在第二晶圓上形成裝置不顯示或描述於本案。在實施本發明的不同製程步驟後，外加製程步驟(未更詳細顯示或者描述)可實施在第二晶圓的下面。例如，形成接觸墊前，圖案化氧化物通常產生於第二晶圓的下面。在其他實施例中，寬的接觸墊可形成在金屬凸柱周圍，以確保良好金屬接觸與較大面積，用於基板的較大封裝墊接合需求。
參閱圖1-4，顯示本發明實施例。金屬凸柱完全芽出至貫通介層的底部。名詞“完全芽出”係指出金屬凸柱具有一高度，以確保金屬凸柱的上表面直接接觸貫通介層的底壁部份。通常以包含介電材質與聚醯亞胺之貫通介層襯層(liner)襯塗底壁部份，亦即為底壁部份加襯層。本說明書之“襯塗”一詞，意指“為某物加襯層”。
圖1顯示本發明的第1步驟，其中顯示第一晶圓(此後稱為裝置晶圓)10與第二晶圓(此後稱為附接晶圓)20。根據本發明實施例，裝置晶圓10是一形成有至少一半導體裝置(未顯示)的晶圓，而且附接晶圓20是一間隔層，可用於吸收來自外部來源的α輻射，例如C4及/或陶瓷基板。如圖1顯示裝置晶圓10包含一第一半導體基板12，具有一圖案化第一介電材質14位於其表面。圖案化第一介電材質14與位於其上之聚醯亞胺塗佈層16或者其他類似的結合材質具有相似的圖案。如圖1所顯示，裝置晶圓10也包含位於設置在圖案化第一介電材質14與聚醯亞胺塗佈層16間之第一半導體基板12表面的至少一金屬凸柱18。
附接晶圓20包含一具有形成於其中之至少一貫通介層24的第二半導體基板22。須注意至少一貫通介層24通常不完全延伸穿過附接晶圓20。附接晶圓20也包含一第二介電材質26，其為至少一貫通介層24的暴露表面(包含底面與側壁)以及介於相鄰介層間的第二半導體基板22的表面加襯層。聚醯亞胺塗佈層28設置於第二介電材質26以便覆蓋出現在至少一貫通介層24的側壁之介電材質，以及鄰近貫通介層24的第二半導體基板22之暴露表面。
裝置晶圓10使用熟習此技藝者熟知的技術製造。例如，在基板與裝置製程後，第一介電材質14係應用至第一半導體基板12的表面，而且通常第一半導體基板12是相對於半導體裝置。第一半導體基板12包含任何半導體材質，這包含但不侷限於矽、鍺、矽化鍺(SiGe)、SiC(碳化矽)、碳矽化鍺(SiGeC)、鎵、砷化鎵(GaAs)、砷化銦(InAs)、磷化銦(InP)以及所有III/V族或II/VI族化合物半導體。第一半導體基板12也包含有機半導體或層狀半導體例如矽/矽化鍺、絕緣層上矽(SOI)或絕緣層上矽化鍺(SGOI)。在其他實施例中，第一半導體基板12較佳包括含矽半導體材質，即包含矽的半導體材質。第一半導體基板12可為受摻雜的、未受摻雜的或者其內包含摻雜區域與未摻雜區域。
當使用SOI基板，這些基板包含頂部與底部半導體(即矽)層，其至少部份由埋入式絕緣層分隔。例如，埋入式絕緣層包含結晶型或非晶型氧化物、氮化物或其任何組合。較佳地，埋入式絕緣層是氧化物。通常，在層轉移製程的最初階段期間或在離子植入與退火製程期間，例如氧離子植入分離(SIMOX)，形成埋入式絕緣層。
第一半導體基板12具有一單一結晶方向，或者使用具有不同結晶方向的表面區域之混合半導體基板。混合基板允許依照一特定結晶方向產生一裝置，以增進特定裝置的效能。例如，混合基板提供一結構，其中，nFET可在(100)結晶方向上形成，pFET可在(110)結晶方向上形成。當使用一混合基板時，可包含類似SOI的特性、類似塊狀(bulk-like)特性或前述兩者特性的組合。
第一介電材質14包含氧化物、氮氧化物、氮化物或其多層結構。在本發明的實施例中，第一介電材質14包含例如二氧化矽(SiO2)的氧化物。第一介電材質14藉由習知沉積技術，例如化學氣相沉積製程(CVD)、電漿輔助化學氣相沉積製程(PECVD)、原子層沉積製程(ALD)、蒸鍍製程、化學溶液沉積製程(chemical solution deposition)以及其他類似沉積技術 而形成。選替地，第一介電材質14可藉由熱製程形成，例如氧化、氮化或其組合。
第一介電材質14的厚度依照其形成技術及所用介電材質的類型而改變。通常，第一介電材質14具有大約100nm至2000nm間的厚度，當厚度是介在500nm至1000nm間是較佳地。
熱塑性聚醯亞胺(此後稱為“聚醯亞胺(polyimide)”)塗佈層16是形成在第一介電材質14的頂部。聚醯亞胺塗佈層16使用習知沉積製程例如CVD、PECVD、蒸鍍法與旋轉塗佈法(spin-on coating)而形成。聚醯亞胺塗佈層16作為黏著層或結合劑，用以附接裝置晶圓10至附接晶圓20。聚醯亞胺塗佈層16通常具有初鍍(as-deposited)厚度大約500nm至大約10000nm間，甚至更典型地是大約1000nm至3000nm間。
於本發明中較佳使用一種熱塑性聚醯亞胺材料，因為熱塑性聚醯亞胺是可延展的、可吸收應力，而且傾向具有一熱膨脹係數(CTE)，係大於本發明使用的半導體基板的熱膨脹係數。
在形成第一介電材質14與聚醯亞胺塗佈層16後，設置圖案化光阻(未顯示)於第一介電材質14的暴 露表面(假如聚醯亞胺塗佈層不存在)或者於聚醯亞胺塗佈層16的頂端(假如聚醯亞胺塗佈層存在)。藉由沉積製程與微影製程而形成圖案化光阻。沉積步驟包含一習知沉積製程包括，例如，CVD、PECVD、旋轉塗佈製程與蒸鍍製程。微影製程包含步驟：將塗佈的光阻暴露於輻射圖案並使用習知光阻顯影劑顯像曝光光阻。圖案化光阻包含暴露出第一介電材質14與聚醯亞胺塗佈層16的頂部表面之開口。隨後，使用蝕刻製程，移除這些開口內暴露的材質。使用乾蝕刻製程(包含反應離子蝕刻、離子束、電漿蝕刻與雷射蝕刻)、濕蝕刻製程或其任何組合製程。蝕刻製程提供開口給第一半導體基板12於形成至少金屬凸柱18之處。蝕刻製程後，使用習知光阻顯影劑，剝除圖案化光阻。
隨後，使用熟習此技藝者的任何習知電鍍製程，形成金屬凸柱18在開口內。如熟習此技藝者所熟知者，金屬凸柱18係接觸銅金屬墊或者圖案化保護層，其存在於裝置晶圓10上。銅墊或者圖案化保護層都並未出現在本發明的圖式中。根據本發明，金屬凸柱18包含非α輻射源的導電性金屬。導電性金屬係非α輻射源材質包含，例如，銅、鋁、鎢與金。上述導電性金屬中，本發明實施例的較佳導電性金屬包含銅。
金屬凸柱18的高度可芽出至附接晶圓的貫通介 層的底壁部份，或者不芽出至貫通介層的底壁部份。本發明先前的實施例係顯示這些圖，而且圖5A-5C顯示本發明之後的實施例。
如上述且如圖1所示，附接晶圓20包含具有至少一聚醯亞胺塗佈層的第二半導體晶圓22。第二半導體晶圓22包含相同或不同的半導體材料作為於裝置晶圓10的第一半導體基板12。通常，第二半導體晶圓22是含矽半導體基板。
使用習知微影製程與蝕刻技術，隨後形成至少一貫通介層24在附接晶圓20的第二半導體晶圓22內。如上所述，本發明形成的至少一貫通介層24通常不延伸穿過第二半導體晶圓22的全部厚度。在形成貫通介層後，所使用的光阻使用習知光阻清除製程加以清除。
在提供至少一貫通介層24後，介電材質26隨後形成在至少一貫通介層24的所有暴露表面(側壁與底壁)和鄰近於貫通介層24之第二半導體晶圓22的暴露表面。介電材質26作為附接晶圓20的貫通介層襯層而且包含相同或不同材質作為裝置晶圓10的第一介電材質14。在其他實施例中，介電材質26較佳包含例如二氧化矽(SiO2)的氧化物。須注意介電材質26可使用上述用於第一介電材質14的技術形成，並且介電 材質26的厚度落在上述第一介電材質14的範圍。
其次，熱塑性聚醯亞胺(此後稱為“聚醯亞胺”)塗佈層28係形成在至少一貫通介層24內之介電材質26的側壁表面與形成在鄰近於至少一貫通介層24之第二半導體晶圓22部份上之介電材質26的頂部。聚醯亞胺塗佈層28可如上述方式形成且其厚度亦落於上述範圍”
在提供顯示於圖1的裝置晶圓10與附接晶圓20後，結合這兩晶圓，以插入金屬凸柱18於貫通介層24。插入後的最終組合結構係顯示於圖2。注意在本發明的特定實施例中，金屬凸柱18芽出至貫通介層24的底壁部份。也就是說，每一金屬凸柱18的上表面接觸到出現在貫通介層24之介電材質26。插入過程施加外力至裝置晶圓10或附接晶圓20或較佳地為兩晶圓。
在提供如圖2顯示的組合結構後，加熱其至一溫度，使得相對於聚醯亞胺表面結合，而且同時使得聚醯亞胺流動，以完全圍繞每一金屬凸柱18。本發明的加熱步驟所實施的溫度可達到聚醯亞胺流動與金屬凸柱18圍繞，但是不會破壞存在於裝置晶圓10的裝置。明確地說，加熱圖2的結構達到低於大約400℃的溫 度，且達到聚醯亞胺流動與金屬凸柱18圍繞，而不破壞存在於裝置晶圓10的裝置。通常，本發明的加熱步驟在大約250℃至375℃間的溫度加以實施。加熱步驟的時間可不同以及依照使用的加熱技術而定。
根據本發明，實施加熱步驟係在鈍氣環境與隨後的壓力下。可用於本發明中之鈍氣環境的範例包含氦、氬、氖、氙與其混合氣體，例如氦與氬的混合氣體。
需要注意在加熱步驟期間，可施加外力在轉移且組合一起的其中之一或者兩個晶圓。
在加熱後，聚醯亞胺塗佈層硬化而且使金屬凸柱陷於第二晶圓之貫通介層內。
使用上述步驟結合兩晶圓後，隨後使用習知平坦化製程薄化附接晶圓20的背面，以提供例如圖3所顯示的結構。如圖3所示，附接晶圓20的薄化暴露出位於貫通介層24的聚醯亞胺塗佈層28內之至少一金屬凸柱18的表面。使用於本發明以薄化附接晶圓20之習知平坦化製程包含研磨及/或化學機械研磨製程(CMP)。濕蝕刻製程亦可單獨使用或者配合研磨及/或化學機械研磨製程(CMP)以薄化附接晶圓20。
圖4顯示，在背面製程後，此結構係產生另一個聚醯亞胺塗佈層30與金屬墊32。形成聚醯亞胺塗佈層30如上所述。較佳包含銅或其他類似金屬之金屬墊32藉由不同沉積、微影與蝕刻製程而形成。
必須注意背面的聚醯亞胺塗佈層30有助於沿著貫通介層的凸柱側壁填充任何可能剩餘孔洞層。凸柱與貫通介層的幾何形狀可加以改變，以創造“漏斗狀”介層(未顯示)以及梯形金屬凸柱(未顯示)。製程順序詳細內容也可針對明確需要與設計而改變。
參考圖5A-5C，顯示本發明的另一實施例。在此實施例中，金屬凸柱18具有一高度而且不芽出出至貫通介層24的底壁部分。圖5A顯示分別插入及結合後的最初兩晶圓10、20。圖5B顯示薄化附接晶圓20後的結構。圖5C顯示在背面製程後，此結構係產生另一個聚醯亞胺塗佈層30與金屬墊32。聚醯亞胺塗佈層30的形成，如上所述。必須注意除金屬凸柱的高度較低於圖1-4實施例中的金屬凸柱的高度之外，此實施例的所有材質與製程詳細內容是與前述內容相同。此特定實施例顯示金屬凸柱18的高度對於形成垂直的互聯結構並不重要。
在以上兩個實施例中，第二晶圓20上不包含任何半導體電路，即半導體裝置。在這些實施例中，第二晶圓20僅作為介於裝置晶圓10與模組(未顯示)間的一間隔層。間隔層(即附接晶圓20)的目的是用於吸收可能來自接近及/或附近C4連接結構放出的α輻射源，而且C4連接結構是用於互連模組與本發明結構。
參考圖6A-6D，顯示本發明的其他實施例。在本發明此實施例中，本發明結構包含設置於第一晶圓10與第二晶圓20間的至少一互聯層，而且裝置晶圓10與附接晶圓20皆具有半導體裝置。圖6A顯示包含位於第一半導體基板12的表面之裝置區域50的第一晶圓10。裝置區域50包含一或多個半導體裝置。第一晶圓10也包含金屬凸柱18、第一介電材質14與聚醯亞胺塗佈層16。金屬接觸52也顯示於第一介電材質14與聚醯亞胺塗佈層16內。金屬接觸52係接觸半導體裝置的選擇區域，例如場效電晶體的源極/汲極區域與閘極。圖6A的第一晶圓10是首先將半導體裝置(未顯示)形成在第一半導體基板12上而製造。其次，如上所述，形成第一介電材質14、聚醯亞胺塗佈層16與金屬凸柱18，而且，藉由微影法與蝕刻法形成金屬接觸開口。隨後，使用習知沉積製程於接觸開口內形成接觸金屬，例如銅、鋁、鎢或鋁銅合金。接觸金屬通常延伸至接觸開口外。選替地，在形成金屬凸柱18 前，形成金屬接觸52。
圖6A也顯示包含第二半導體基板22的第二晶圓20，而第二半導體基板22包含位於其表面的一半導體裝置區域54。第二晶圓20也包含至少一貫通介層24、介電材質26、聚醯亞胺塗佈層28、接觸開口56與接觸墊58。接觸墊58係由例如銅的習知金屬組成。藉由將半導體裝置區域54與接觸墊58形成圖6A的第二晶圓20在第二基板22上，而且隨後形成如上所述之至少一貫通介層24。在本發明某些實施例中，上述製程是可逆向操作。其次，使用前述技術產生層26、28，而且隨後使用微影製程與蝕刻製程形成接觸開口56。
在圖6A說明兩晶圓後，如上述結合並加熱圖6B顯示結構。必須注意包含接觸墊58、金屬接觸52以及第一介電材質14、26之互聯層係設置於第一與第二晶圓間。在本發明實施例中，使用如上所述之轉移與接合法(T&J)以同時結合接觸墊58至金屬接觸52，隨後插入金屬凸柱18。
圖6C顯示已薄化第二晶圓20後利用上述製程技術的結構。
圖6D顯示實施背面製程後利用上述技術之具有其他聚醯亞胺塗佈層30與金屬墊32的結構。
本發明已藉由實施例加以描述，熟習此技藝者應該瞭解本發明可在附屬申請專利範圍的精神與範圍內的改良情形下實施。因此，本發明實施例不限定於已描述與已說明的明確形式，然而用於包含所有改良將不偏離本發明的精神與範疇。
10‧‧‧第一晶圓
12‧‧‧第一半導體基板
14‧‧‧圖案化第一介電材質
16‧‧‧聚醯亞胺塗佈層
18‧‧‧金屬凸柱
20‧‧‧第二晶圓
22‧‧‧第二半導體基板
24‧‧‧貫通介層
26‧‧‧介電材質
28‧‧‧聚醯亞胺塗佈層
30‧‧‧其他聚醯亞胺塗佈層
32‧‧‧金屬墊
50‧‧‧裝置區域
52‧‧‧金屬接觸
54‧‧‧半導體裝置區域
56‧‧‧接觸開口
58‧‧‧接觸墊
圖1係說明使用於本發明的第一晶圓與第二晶圓的示意圖(截面圖)；圖2係說明設置於第一晶圓背面之金屬凸柱插入形成於第二晶圓的聚醯亞胺塗佈貫通介層後之結構示意圖(截面圖)；圖3係說明經過接附與薄化後，圖2的結構之示意圖(截面圖)；圖4係說明具有聚醯亞胺與金屬墊之背面製程後，圖3的結構之示意圖(截面圖)；圖5A-5C係說明金屬凸柱並未完全芽出至貫通介層的底部的另一實施例之示意圖(截面圖)；以及圖6A-6D係說明設置於第一晶圓與第二晶圓間之互聯層的又另一實施例之示意圖(截面圖)。
10．．．第一晶圓
12．．．第一半導體基板
14．．．圖案化第一介電材質
16．．．聚醯亞胺塗佈層
18．．．金屬凸柱
20．．．第二晶圓
22．．．第二半導體基板
28．．．聚醯亞胺塗佈層
26．．．介電材質
32．．．金屬墊
30．．．聚醯亞胺塗佈層

Claims (30)

  1. 一種製造一垂直晶圓對晶圓互聯結構之方法，包含：提供一第一晶圓與一第二晶圓，該第一晶圓具有至少一金屬凸柱設置於該第一晶圓的一表面上，而該第二晶圓包含至少一塗佈聚醯亞胺的貫通介層；插入該第一晶圓的該至少一金屬凸柱於第二晶圓的該至少一塗佈聚醯亞胺的貫通介層，以提供一組合結構；加熱該組合結構，使得相對的聚醯亞胺表面進行結合並啟始流動以完全圍繞每一金屬凸柱；薄化該第二晶圓以暴露出位於該至少一塗佈聚醯亞胺的貫通介層內的該至少一金屬凸柱的一表面；以及形成一圖案化聚醯亞胺塗佈層在該薄化的第二晶圓的一表面上，並形成一金屬墊在該至少一金屬凸柱的該暴露表面上。
  2. 如申請專利範圍第1項所述之方法，其中該提供該第一晶圓包含沉積一介電材質在一半導體基板的一表面，形成一聚醯亞胺塗佈層在該介電材質上，提供一開口於該介電材質與該聚醯亞胺塗佈層中，以及經由該開口以電鍍一導電性金屬。
  3. 如申請專利範圍第1項所述之方法，其中該至少一金屬凸柱包含銅(Cu)、鋁(Al)、鎢(W)或金(Au)。
  4. 如申請專利範圍第3項所述之方法，其中該至少一金屬凸柱包含銅(Cu)。
  5. 如申請專利範圍第1項所述之方法，其中該提供該第二晶圓包含：形成至少一貫通介層在一半導體基板上，襯塗該貫通介層之該暴露表面與具有一介電材質之部份該半導體基板，以及形成一聚醯亞胺塗佈層在該介電材質的所有暴露表面上。
  6. 如申請專利範圍第1項所述之方法，其中在該插入後每一金屬凸柱是直接接觸襯塗每一貫通介層的底壁部份之一介電材質。
  7. 如申請專利範圍第1項所述之方法，其中在該插入後每一金屬凸柱並非直接接觸襯塗每一貫通介層的底壁部份之一介電材質。
  8. 如申請專利範圍第1項所述之方法，其中該加熱係實施在低於大約400℃的溫度。
  9. 如申請專利範圍第1項所述之方法，其中該薄化係以研磨製程、化學機械研磨製程、濕蝕刻製程或其組合製程而實施。
  10. 如申請專利範圍第1項所述之方法，其中該至少一金屬凸柱包含銅，而該至少一金屬墊包含銅。
  11. 如申請專利範圍第1項所述之方法，其中該第一晶圓包含設置於一半導體基板的一表面之半導體裝置。
  12. 如申請專利範圍第11項所述之方法，其中該第二晶圓包含設置於其他半導體基板的一表面之半導體裝置，而第一與第二晶圓藉由一互聯層與一結合聚醯亞胺層而分隔。
  13. 一種製造一垂直晶圓對晶圓互聯結構之方法，包含：提供一第一晶圓與一第二晶圓，該第一晶圓具有至少一銅凸柱設置於該第一晶圓的一表面上，而且該第二晶圓包含至少一塗佈聚醯亞胺的貫通介層；插入該第一晶圓的該至少一銅凸柱於該第二晶圓的該至少一塗佈聚醯亞胺的貫通介層，以提供 一組合結構；加熱該組合結構，使得相對的聚醯亞胺表面進行結合並啟始流動以完全圍繞每一銅凸柱；薄化該第二晶圓以暴露出位於該至少一塗佈聚醯亞胺的貫通介層內的該至少一銅凸柱的一表面；以及形成一圖案化聚醯亞胺塗佈層在該薄化的第二晶圓的一表面上，並形成一銅墊在該至少一銅凸柱的該暴露表面上。
  14. 如申請專利範圍第13項所述之方法，其中該提供該第一晶圓包含：沉積一介電材質在一半導體基板的一表面，形成一聚醯亞胺塗佈層在該介電材質上，提供一開口於該介電材質與該聚醯亞胺塗佈層中，以及經由該開口以電鍍銅。
  15. 如申請專利範圍第13項所述之方法，其中該提供該第二晶圓包含：形成至少一貫通介層在一半導體基板上，襯塗該貫通介層之該暴露表面與具有一介電材質之部份該半導體基板，以及形成一聚醯亞胺塗佈層在至少該介電材質的側壁上。
  16. 如申請專利範圍第13項所述之方法，其中在該插入後每一銅凸柱是直接接觸襯塗每一貫通介層的 底壁部份之一介電材質。
  17. 如申請專利範圍第13項所述之方法，其中在該插入後每一銅凸柱並非直接接觸觸襯塗每一貫通介層的底壁部份之一介電材質。
  18. 如申請專利範圍第13項所述之方法，其中該加熱步驟係實施在低於大約400℃的溫度。
  19. 如申請專利範圍第13項所述之方法，其中該薄化係以研磨製程、化學機械研磨製程、濕蝕刻製程或其組合製程而實施。
  20. 一種垂直晶圓對晶圓互聯結構，包含：一第一晶圓與一第二晶圓，係藉以由該第一晶圓的一表面延伸之至少一金屬凸柱相匹配，該至少一金屬凸柱由該第一晶圓的該表面延伸入該第二晶圓的一相對應貫通介層，其中一聚醯亞胺塗佈層呈現在該貫通介層、該第一晶圓與第二晶圓的配合表面，以及直接位於該第二晶圓不與該第一晶圓配合的一暴露半導體表面，且其中直接位於該第二晶圓之該暴露半導體表面的該聚醯亞胺塗佈層具有至少一邊緣，而該邊緣與該至少一金屬凸柱之一垂直邊緣接觸，且該至少一金屬凸柱提供由該第一晶 圓至該第二晶圓的一連續金屬通路。
  21. 如申請專利範圍第20項所述之垂直晶圓對晶圓互聯結構，其中該第一晶圓與該第二晶圓包含相同或者不同的半導體材料。
  22. 如申請專利範圍第21項所述之垂直晶圓對晶圓互聯結構，其中該第一晶圓與該第二晶圓皆包含一含矽半導體。
  23. 如申請專利範圍第20項所述之垂直晶圓對晶圓互聯結構，其中一介電材質襯塗每一貫通介層的側壁。
  24. 如申請專利範圍第23項所述之垂直晶圓對晶圓互聯結構，其中該介電材質係為氧化物。
  25. 如申請專利範圍第20項所述之垂直晶圓對晶圓互聯結構，進一步包含在該至少一金屬凸柱的每一暴露表面的一金屬墊，該金屬墊位於該聚醯亞胺塗佈層的一部分上，其中該聚醯亞胺塗佈層直接位於該第二晶圓的該暴露半導體表面上。
  26. 如申請專利範圍第20項所述之垂直晶圓對晶圓互 聯結構，其中該至少一金屬凸柱包含一導電性金屬，該導電性金屬係選自包含銅、鋁、鎢以及金的金屬所組成之群組。
  27. 如申請專利範圍第26項所述之垂直晶圓對晶圓互聯結構，其中該導電性金屬是銅。
  28. 如申請專利範圍第25項所述之垂直晶圓對晶圓互聯結構，其中金屬墊由銅所組成，而且每一金屬凸柱由銅組成。
  29. 如申請專利範圍第20項所述之垂直晶圓對晶圓互聯結構，其中該第一晶圓包含設置於一半導體基板的一表面之半導體裝置。
  30. 如申請專利範圍第20項所述之垂直晶圓對晶圓互聯結構，其中該第二晶圓包含設置於其他半導體基板的一表面之半導體裝置係，而該第一及第二晶圓係藉由一互聯層分開。
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US20080105976A1 (en) 2008-05-08
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