CN101494212A - 焊垫结构、包括该焊垫结构的半导体器件及其制造方法 - Google Patents

焊垫结构、包括该焊垫结构的半导体器件及其制造方法 Download PDF

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Publication number
CN101494212A
CN101494212A CNA2008101910579A CN200810191057A CN101494212A CN 101494212 A CN101494212 A CN 101494212A CN A2008101910579 A CNA2008101910579 A CN A2008101910579A CN 200810191057 A CN200810191057 A CN 200810191057A CN 101494212 A CN101494212 A CN 101494212A
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China
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metal layer
layer
metal
pad structure
metal level
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洪琮沅
崔吉铉
黄烘奎
李钟鸣
郭旻根
成金重
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明公开了一种焊垫结构、包括该焊垫结构的半导体器件及其制造方法。一种用于半导体器件的焊垫结构包括器件的接合区域中的第二上金属层和在第二上金属层之下的第一下金属层。下金属层形成为下金属层的金属不存在于接合区域。因此，如果在例如探测或者接合的工艺过程中在接合区域产生对结构的损坏，下金属层不会暴露到环境。暴露到环境引起的下金属层的金属的氧化被防止，从而提高了器件的可靠性。

Description

焊垫结构、包括该焊垫结构的半导体器件及其制造方法
技术领域
本发明涉及半导体器件及制造半导体器件的方法。具体地，本发明涉及一种用于半导体器件的焊垫结构(bonding pad structure)、包括该焊垫结构的半导体器件以及制造该焊垫结构和包括该焊垫结构的半导体器件的方法。
背景技术
半导体器件典型地包括由导体层(例如金属层)形成的焊垫(bondingpad)。焊垫通常用来测量半导体器件的电特性。测试时，探针在焊垫处与半导体器件接触。当半导体器件安装在封装(package)中时，焊垫也用来与焊线(bonding wire)或者凸块(bump)电接触。
图1是半导体器件中的常规焊垫结构10的示意性截面图。焊垫结构10包括形成在第一层间金属电介质(inter-metal dielectric，IMD)层16中的第一金属层12。位于第二IMD层18中的第二金属层14形成在第一金属层12上。保护绝缘钝化层24形成在第二金属层14和第二IMD层18上。钝化层24可以包括两层，该两层可以是氮化硅层22及在氮化硅层22下面的二氧化硅层20。钝化层24被光敏聚酰亚胺层26覆盖。结构10包括敞开的引线球区域(open wire ball region)28，在测试时探针在该区域接触半导体器件，在封装工艺期间引线在该区域接合到器件或者在该区域形成凸块。
通常，第一金属层12和第二金属层14由铝(Al)制成。然而，随着对器件的高性能、高集成度需求的不断增加，焊垫结构已经开始采用由铜替代铝形成的下金属层12来制造。
当在焊垫上进行探测或者引线接合(wire bonding)时，有可能第一金属层和/或第二金属层被损坏。这会导致第一金属层和/或第二金属层暴露到大气。当下金属层12由铜形成时，铜在暴露到大气时非常易于氧化。铜的下金属层12的氧化使器件退化或者引起器件失效。
发明内容
本发明提供了一种用于半导体器件的焊垫结构、包括该焊垫结构的半导体器件以及制造该结构和器件的方法，该方法中消除了焊垫结构的铜的下金属层的氧化。在本发明的结构中，在引线球区域中没有下金属层的铜存在。因此，如果在焊垫结构上进行接合或者探测，即使接合或者探测引起对结构的损坏，该结构的下金属层的铜的氧化也不会发生。这导致更加可靠的半导体器件。
根据第一方面，本发明涉及一种半导体器件。该器件包括接合区域(bonding area)(可在该区域进行接合)和焊垫结构(在接合区域中并延伸到接合区域以外)。该焊垫结构包括第一金属层以及在第一金属层之上的第二金属层。在第一金属层中，在接合区域没有金属。
第一金属层可以包括铜或者铝。阻挡金属层(barrier metal layer)可以插设在第一金属层与第二金属层之间。阻挡金属层可以由Ta、TaN、TiN和WN中的至少一种组成。
在一个实施例中，第二金属层包括铝。
在一个实施例中，第二金属层包括铜。镀层可以形成在第二金属层上。镀层可以包括镍、铅和金中的至少一种。
在一个实施例中，第一金属层包括电耦接到第二金属层的连续导电区域(continuous conductive region)。
在一个实施例中，第一金属层包括电耦接到第二金属层的多个导电引脚(conductive pin)。
在一个实施例中，第二金属层包括电耦接到第一金属层的接触插塞区域(contact plug region)。接触插塞区域包括与第一金属层接触的多个导电插塞。可选地，接触插塞区域可以包括电耦接到第一金属层的连续导电区域。
在一个实施例中，焊垫结构还包括在第一金属层之下的保护层。
根据另一方面，本发明涉及一种制造半导体器件的方法。根据该方法，提供衬底，接合区域(可在该区域进行接合)在衬底中形成。焊垫结构形成在接合区域中并且延伸到该接合区域之外。焊垫结构的形成包括形成第一金属层以及在第一金属层之上形成第二金属层。第一金属层形成为第一金属层的金属不存在于接合区域。
第一金属层可以由铜或者铝形成。阻挡金属层可以形成在第一金属层与第二金属层之间。阻挡金属层可以包括Ta、TaN、TiN和WN中的至少一种。
在一个实施例中，第二金属层由铝形成。
在一个实施例中，第二金属层由铜形成。镀层可以形成在第二金属层上。镀层可以包括镍、铅和金中的至少一种。
在一个实施例中，第一金属层形成为具有电耦接到第二金属层的连续导电区域。
在一个实施例中，第一金属层形成为具有电耦接到第二金属层的多个导电引脚。
在一个实施例中，第二金属层形成为具有电耦接到第一金属层的接触插塞区域。接触插塞区域可以包括电耦接到第一金属层的多个导电插塞。可选地，接触插塞区域可以包括电耦接到第一金属层的连续导电区域。
在一个实施例中，该方法还包括在第一金属层之下形成保护层。
根据另一方面，本发明涉及一种焊垫结构，该焊垫结构包括第一金属层以及在第一金属层之上的第二金属层。在第一金属层中，第一金属层的金属不存在于接合区域。
第一金属层可以包括铜或者铝。阻挡金属层可以插设在第一金属层与第二金属层之间。阻挡金属层可以包括Ta、TaN、TiN和WN中的至少一种。
在一个实施例中，第二金属层包括铝。
在一个实施例中，第二金属层包括铜。镀层可以形成在第二金属层上。镀层可以包括镍、铅和金中的至少一种。
在一个实施例中，第一金属层包括电耦接到第二金属层的连续导电区域。
在一个实施例中，第一金属层包括电耦接到第二金属层的多个导电引脚。
在一个实施例中，第二金属层包括电耦接到第一金属层的接触插塞区域。接触插塞区域包括电耦接到第一金属层的多个导电插塞。可选地，接触插塞区域可以包括电耦接到第一金属层的连续导电区域。
在一个实施例中，该结构还包括在第一金属层之下的保护层。
根据另一方面，本发明涉及一种焊垫结构的制造方法。根据该方法，形成第一金属层，第二金属层形成在第一金属层之上。第一金属层形成为，在第一金属层中在接合区域没有金属。
第一金属层可以由铜或者铝形成。阻挡金属层可以形成在第一金属层与第二金属层之间。阻挡金属层可以包括Ta、TaN、TiN和WN中的至少一种。
在一个实施例中，第二金属层由铝形成。
在一个实施例中，第二金属层由铜形成。镀层可以形成在第二金属层上。镀层可以包括镍、铅和金中的至少一种。
在一个实施例中，第一金属层包括电耦接到第二金属层的连续导电区域。
在一个实施例中，第一金属层包括电耦接到第二金属层的多个导电引脚。
在一个实施例中，第二金属层形成为具有电耦接到第一金属层的接触插塞区域。接触插塞区域可以包括电耦接到第一金属层的多个导电插塞。可选地，接触插塞区域可以包括电耦接到第一金属层的连续导电区域。
在一个实施例中，该方法还包括在第一金属层之下形成保护层。
附图说明
如附图中所示出的，本发明的上述和其他的特征以及优点将从对本发明的优选方面的更详细的描述变得明显，附图中相同的附图标记在不同的视图中始终指代相同的部件。附图不必按照比例，而是重在阐述本发明的原理。在附图中，为了清晰起见，层和区域的厚度被夸大。
图1是半导体器件中一种常规焊垫结构的示意性截面图。
图2是根据本发明一个实施例的用于半导体器件的焊垫结构的示意性截面图。
图3是图2的第一金属层或者下焊垫层(lower pad layer)的示意性平面顶视图。
图4是沿图3的线IV-IV’截得的下焊垫层的示意性截面图。
图5是图2的焊垫结构中的第二金属层或者上焊垫层(upper pad layer)的示意性平面顶视图。
图6是沿图5的线VI-VI’截得的上焊垫层的示意性截面图。
图7到12是示出图2中示出的半导体器件的焊垫结构的制造工艺的实施例的示意性截面图。
图13是根据本发明另一实施例的半导体器件的焊垫结构的示意性截面图。
图14包含了图13的焊垫结构的上焊垫层的示意性截面图。
图15和16是示出制造图13的焊垫结构的步骤的示意性截面图。
图17是根据本发明另一实施例的半导体器件的焊垫结构的示意性截面图。
图18包含了图17的焊垫结构的下焊垫层的示意性平面顶视图。
图19包含了沿图18的线XIX-XIX’截得的下焊垫层的示意性截面图。
图20和21是示出制造图17的焊垫结构的步骤的示意性截面图。
图22是根据本发明另一实施例的半导体器件的焊垫结构的示意性截面图。
图23包含了使用本发明的焊垫结构的已封装的半导体器件的示意性截面图。
具体实施方式
图2是根据本发明一个实施例的用于半导体器件的焊垫结构100的示意性截面图。焊垫结构100形成在半导体衬底180上。不同的器件182形成在衬底180中。层间电介质(inter-layer dielectric，ILD)层185形成在器件182上。可选的探测保护层150(其可以由绝缘或者导电材料形成)可选地形成在ILD层185中。在第一层间金属电介质(IMD)层160中的第一金属层或者下焊垫层110形成在ILD层185上。第一IMD层160包括沟槽区域162，下焊垫层110的金属导电部分在沟槽区域162中形成。第一金属层或者下焊垫层110可以由例如铜或者铝形成。阻挡金属层190可以形成在下焊垫层110上以防止在随后的工艺步骤期间下焊垫层110的材料的迁移。阻挡金属层190在第一金属层110由铜形成的情况下特别有用。阻挡金属层190可以由例如Ta、TaN、TiN和WN形成。应当指出，阻挡金属层190是可选的层，不是必须使用。
第二IMD层170形成在第一IMD层160和下焊垫层110之上。在第二IMD层170中的第二金属层或者上焊垫层120形成在下焊垫层110上方。上焊垫层120可以由例如铜或者铝形成。上焊垫层120包括接触插塞区域130，接触插塞区域130从上焊垫层120的靠近上焊垫层120的边缘的下表面突出，并通过阻挡金属层190与下焊垫层110对准并且电耦接到下焊垫层110。应当指出，当不存在阻挡金属层190时，上焊垫层120的接触插塞区域130与下焊垫层110接触。钝化层140(其可以包括氧化硅层142和在氧化硅层142上的氮化硅层144)形成在上焊垫层120上。聚酰亚胺层146可以形成在钝化层140上。
在上焊垫层120由铜制成的情况下，附加可选的由镍(Ni)、铅(Pb)和/或金(Au)电镀的镀层121形成在上焊垫层120上。镀层121可以用于防止上焊垫层120氧化，并用于良好的引线接合。
图3是图2的第一金属层或者下焊垫层110的示意性平面顶视图。图4是沿图3的线IV-IV’截得的下焊垫层110的示意性截面图。图5是图2的焊垫结构100中的第二金属层或者上焊垫层120的示意性平面顶视图。图6是沿图5的线VI-VI’截得的上焊垫层120的示意性截面图。
参照图2到6，在此实施例中，下焊垫层110以围绕矩形开口区域112的导电区域的形状形成，矩形开口区域112由第一IMD层160的沟槽部分162限定。上焊垫层120也形成为导电矩形焊垫。上焊垫层120还具有从其下表面突出的接触插塞区域130。接触插塞区域130围绕上焊垫层120的周围形成，从而接触插塞区域130与下焊垫层110的导电区域对准。如所示出的，在此实施例中，接触插塞区域130包括以阵列方式二维地布置的多个小导电引脚或者插塞。在接触插塞区域130中的多个导电引脚或者插塞电耦接到下焊垫层110的导电部分。
如附图所示，由于在下焊垫层110中的开口112，没有下焊垫层110的金属(例如铜)存在于引线接合区域128中。因此，在区域128中探测或者引线接合可能损坏上焊垫层120的地方，在接合区域128中没有铜会暴露到大气。因此，铜的氧化被消除，从而提高了器件的可靠性。
图7到12是制造图2中示出的半导体器件的焊垫结构100的工艺的实施例的示意性截面图。参照图7，器件结构182形成在衬底180中。ILD层185形成在衬底180上，探测保护层150可以形成在ILD层185中。探测保护层150可以由金属或电介质材料形成。探测保护层防止对器件182的破坏，该破坏可能是由层在探测或者接合的压力下断裂引起。探测保护层150是可选的元件。
参照图8，第一IMD层160形成在ILD层185上。第一IMD层160包括沟槽162，在焊垫结构中沟槽162形成在靠近IMD层160的周边。沟槽162用于形成下焊垫层110的填充沟槽162的导电部分。
参照图9，下焊垫层110通过工艺(例如单大马士革工艺)形成在沟槽162中。可选地，阻挡金属层190形成在下焊垫层110上以防止在随后的工艺步骤期间下焊垫层110的金属的迁移。阻挡金属层190可以由例如Ta、TaN、TiN和WN形成。
参照图10，第二IMD层170形成在下焊垫层110之上。第二IMD层170被成形和图案化(例如通过光刻掩模和蚀刻)以形成用于上焊垫层120的主体的主要开口以及多个通孔(via hole)172，通孔172以二维阵列或矩阵布置从而与下焊垫层110的导电部分对准并电耦接到下焊垫层110的导电部分。
参照图11，第二IMD层170中的图案化的开口和通孔172用例如铝或铜的导电材料填充以形成上焊垫层120。在上焊垫层120由铜形成的情况下，可选的Ni/Pd/Au镀层121可以形成在上焊垫层120上。
参照图12，钝化层140形成在上焊垫层120(和可选的Ni/Pd/Au镀层121)以及第二IMD层170上。钝化层140可以包括氧化硅层142和在氧化硅层142上的氮化硅层144。尽管在图12中未示出，聚酰亚胺层146(见图2)可以形成在钝化层140上。
图13是根据本发明另一实施例的半导体器件的焊垫结构100a的示意性截面图。图13的实施例与图2的实施例的区别在于图13的实施例的上焊垫层120a具有不同于图2的实施例的接触插塞区域130的接触插塞区域130a。上焊垫层120a可以由例如铜或者铝形成。
对图13的实施例的与图2的实施例的元件相同的元件的描述将不再重复。
图14包含了图13的焊垫结构100a的上焊垫层120a的示意性截面图。参照图13和14，接触插塞区域130a是连续导电区域，代替了图2的实施例的接触插塞区域130中的导电引脚或者插塞的二维阵列。连续导电接触插塞区域130a电耦接到下焊垫层110。可选地，阻挡金属层190插设在上焊垫层120a与下焊垫层110之间。在不存在阻挡金属层190的情况下，连续导电接触插塞区域130a与下焊垫层110直接接触。
图15和16是示出与制造焊垫结构100的步骤不同的制造焊垫结构100a的步骤的示意性截面图。参照图15，第二IMD层170a形成在下焊垫层110之上。第二IMD层170a被成形和图案化(例如通过光刻掩模和蚀刻)以形成用于上焊垫层120a的主体的主要开口以及用于上焊垫层120a的接触插塞区域130a的开口172a。应当指出，开口172a是连续的开口而不是图2的实施例中的多个通孔172。
参照图16，第二IMD层170a中的图案化的主要开口和开口172a由用于上焊垫层120a的导电材料填充以形成上焊垫层120a。
图17是根据本发明另一实施例的半导体器件的焊垫结构100b的示意性截面图。图17中的实施例与图2中的实施例的区别在于图17的实施例的下焊垫层110b具有与图2的实施例的下焊垫层110的不同的构造。具体地，图17的实施例的下焊垫层110b构造为二维阵列或者矩阵的导电引脚或者插塞，与图2的实施例的下焊垫层110的连续导电区域成对比。第一金属层或下焊垫层110可以由例如铜或者铝形成。阻挡金属层190是可选的，可以不使用。
图17的实施例的与图2和/或图13的实施例的元件相同的元件的描述将不再重复。
图18包含了图17的焊垫结构100b的下焊垫层110b的示意性的平面顶视图。图19包含了沿图18的线XIX-XIX’截得的下焊垫层110b的示意性截面图。参照图17到19，下焊垫层110b包括以二维阵列或者矩阵布置并形成在第一IMD层160b中的多个导电引脚或者插塞。导电引脚电耦接到上焊垫层120的接触插塞区域130中的导电插塞阵列。可选地，阻挡金属层190插设在上焊垫层130与下焊垫层110b之间。然而，当不使用阻挡金属层190时，接触插塞区域130与下焊垫层110b直接接触。应当指出，尽管下焊垫层110b与图2的实施例的上焊垫层130一起示出，它也可以与图13的实施例的上焊垫层130b一起使用。
图20和21示出了与制造焊垫结构100和/或100a中的步骤不同的制造焊垫结构100b中的步骤的示意性截面图。参照图20，第一IMD层160b形成在ILD层185上。第一IMD层160b被成形和图案化(例如通过光刻掩模和蚀刻)以形成将形成下焊垫层110b的区域。具体地，第一IMD层160b被图案化，以具有以二维阵列或者矩阵布置的多个通孔162b，从而当它们用下焊垫层110b的金属填充时，形成具有二维阵列的导电引脚或者插塞的下焊垫层110b。参照图21，下焊垫层110b的金属形成在第一IMD层160b的通孔中以形成具有二维阵列的导电引脚、插塞或者点的下焊垫层110b。
图22是根据本发明另一个实施例的半导体器件的焊垫结构100c的示意性截面图。图22的实施例与图2、13和17的实施例的区别在于，上焊垫层120c不包括之前描述的实施例的接触插塞区域130。替代地，上焊垫层120c的主体电耦接到下焊垫层110而不插入接触插塞区域130。如之前的实施例在上面指出的，阻挡金属层可以插设在上焊垫层120c与下焊垫层110之间。
图22的实施例(其中上焊垫层120c不具有接触插塞区域130)与结合图2的实施例描述的焊垫结构100一起示出。应当指出，这只是为了说明的目的。没有接触插塞区域的上焊垫层120c的实施例可应用于这里所述的所有焊垫结构实施例。
图23包含了使用本发明的焊垫结构的已封装的半导体器件200的示意性截面图。参照图23，电路和本发明的焊垫结构形成在衬底210上，衬底210安装在封装的基座(base)220上。通过焊线连接到引线接合区域28的焊垫结构，焊线230将基底220连接到衬底上的电路。器件被密封在由例如环氧树脂的材料制成的保护封装240中。导电球250将封装的器件200连接到外部电路。
尽管已经参照本发明的示范性实施例对本发明进行了具体地示出和描述，本领域技术人员应当理解，在形式和细节上可以作出各种变化而不背离本发明的由附加的权利要求书所限定的精神和范围。
本申请要求于2008年1月4日提交到韩国知识产权局的韩国专利申请10-2008-0001171的优先权，其全部内容在此引入以作参考。

Claims (60)

1.一种半导体器件，包括：
接合区域，可以在该接合区域进行接合；和
焊垫结构，在所述接合区域中且延伸到所述接合区域之外，所述焊垫结构包括：
第一金属层，和
在所述第一金属层之上的第二金属层，其中，在所述第一金属层中，在所述接合区域没有金属。
2.如权利要求1所述的半导体器件，其中所述第一金属层包括铜。
3.如权利要求1所述的半导体器件，其中所述第一金属层包括铝。
4.如权利要求1所述的半导体器件，还包括在所述第一金属层与所述第二金属层之间的阻挡金属层。
5.如权利要求4所述的半导体器件，其中所述阻挡金属层包括Ta、TaN、TiN和WN中的至少一种。
6.如权利要求1所述的半导体器件，其中所述第二金属层包括铝。
7.如权利要求1所述的半导体器件，其中所述第二金属层包括铜。
8.如权利要求7所述的半导体器件，还包括形成在所述第二金属层上的镀层。
9.如权利要求8所述的半导体器件，其中所述镀层包括镍、铅和金中的至少一种。
10.如权利要求1所述的半导体器件，其中所述第一金属层包括电耦接到所述第二金属层的连续导电区域。
11.如权利要求1所述的半导体器件，其中所述第一金属层包括电耦接到所述第二金属层的多个导电引脚。
12.如权利要求1所述的半导体器件，其中所述第二金属层包括电耦接到所述第一金属层的接触插塞区域。
13.如权利要求12所述的半导体器件，其中所述导电插塞区域包括与所述第一金属层接触的多个导电插塞。
14.如权利要求12所述的半导体器件，其中所述导电插塞区域包括电耦接到所述第一金属层的连续导电区域。
15.如权利要求1所述的半导体器件，还包括在所述第一金属层之下的保护层。
16.一种制造半导体器件的方法，包括：
提供衬底；
在所述衬底中形成接合区域，可在所述接合区域进行接合；
在所述接合区域中形成焊垫结构，并且所述焊垫结构延伸到所述接合区域之外，所述形成焊垫结构包括：
形成第一金属层；和
在所述第一金属层之上形成第二金属层，其中所述第一金属层形成为在所述接合区域没有金属。
17.如权利要求16所述的方法，其中所述第一金属层由铜形成。
18.如权利要求16所述的方法，其中所述第一金属层由铝形成。
19.如权利要求16所述的方法，还包括在所述第一金属层与所述第二金属层之间形成阻挡金属层。
20.如权利要求19所述的方法，其中所述阻挡金属层包括Ta、TaN、TiN和WN中的至少一种。
21.如权利要求16所述的方法，其中所述第二金属层由铝形成。
22.如权利要求16所述的方法，其中所述第二金属层由铜形成。
23.如权利要求22所述的方法，还包括在所述第二金属层上形成镀层。
24.如权利要求23所述的方法，其中所述镀层包括镍、铅和金中的至少一种。
25.如权利要求16所述的方法，其中所述第一金属层形成为具有电耦接到所述第二金属层的连续导电区域。
26.如权利要求16所述的方法，其中所述第一金属层形成为具有电耦接到所述第二金属层的多个导电引脚。
27.如权利要求16所述的方法，其中所述第二金属层形成为具有电耦接到所述第一金属层的接触插塞区域。
28.如权利要求27所述的方法，其中所述接触插塞区域包括电耦接到所述第一金属层的多个导电插塞。
29.如权利要求27所述的方法，其中所述接触插塞区域包括电耦接到所述第一金属层的连续导电区域。
30.如权利要求16所述的方法，还包括在所述第一金属层之下形成保护层。
31.一种焊垫结构，包括：
第一金属层，和
在所述第一金属层之上的第二金属层，其中，在所述第一金属层中，在所述接合区域没有金属。
32.如权利要求31所述的焊垫结构，其中所述第一金属层包括铜。
33.如权利要求31所述的焊垫结构，其中所述第一金属层包括铝。
34.如权利要求31所述的焊垫结构，还包括在所述第一金属层与所述第二金属层之间的阻挡金属层。
35.如权利要求34所述的焊垫结构，其中所述阻挡金属层包括Ta、TaN、TiN和WN中的至少一种。
36.如权利要求31所述的焊垫结构，其中所述第二金属层包括铝。
37.如权利要求31所述的焊垫结构，其中所述第二金属层包括铜。
38.如权利要求37所述的焊垫结构，还包括形成在所述第二金属层上的镀层。
39.如权利要求38所述的焊垫结构，其中所述镀层包括镍、铅和金中的至少一种。
40.如权利要求31所述的焊垫结构，其中所述第一金属层包括电耦接到所述第二金属层的连续导电区域。
41.如权利要求31所述的焊垫结构，其中所述第一金属层包括电耦接到所述第二金属层的多个导电引脚。
42.如权利要求31所述的焊垫结构，其中所述第二金属层包括电耦接到所述第一金属层的接触插塞区域。
43.如权利要求42所述的焊垫结构，其中所述接触插塞区域包括电耦接到所述第一金属层的多个导电插塞。
44.如权利要求42所述的焊垫结构，其中所述接触插塞区域包括电耦接到所述第一金属层的连续导电区域。
45.如权利要求31所述的焊垫结构，还包括在所述第一金属层之下的保护层。
46.一种制造焊垫结构的方法，包括：
形成第一金属层；和
在所述第一金属层之上形成第二金属层，其中形成所述第一金属层以使在所述第一金属层中在所述接合区域没有金属。
47.如权利要求46所述的方法，其中所述第一金属层由铜形成。
48.如权利要求46所述的方法，其中所述第一金属层由铝形成。
49.如权利要求46所述的方法，还包括在所述第一金属层与所述第二金属层之间形成阻挡金属层。
50.如权利要求49所述的方法，其中所述阻挡金属层包括Ta、TaN、TiN和WN中的至少一种。
51.如权利要求46所述的方法，其中所述第二金属层由铝形成。
52.如权利要求46所述的方法，其中所述第二金属层由铜形成。
53.如权利要求52所述的方法，还包括在所述第二金属层上形成镀层。
54.如权利要求53所述的方法，其中所述镀层包括镍、铅和金中的至少一种。
55.如权利要求46所述的方法，其中所述第一金属层形成为具有电耦接到所述第二金属层的连续导电区域。
56.如权利要求46所述的方法，其中所述第一金属层形成为具有电耦接到所述第二金属层的多个导电引脚。
57.如权利要求46所述的方法，其中所述第二金属层形成为具有电耦接到所述第一金属层的接触插塞区域。
58.如权利要求57所述的方法，其中所述接触插塞区域包括电耦接到所述第一金属层的多个导电插塞。
59.如权利要求57所述的方法，其中所述接触插塞区域包括电耦接到所述第一金属层的连续导电区域。
60.如权利要求46所述的方法，还包括在所述第一金属层之下形成保护层。
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Publication number Priority date Publication date Assignee Title
TWI399839B (zh) * 2009-09-28 2013-06-21 Powertech Technology Inc 內置於半導體封裝構造之中介連接器
TWI428608B (zh) 2011-09-16 2014-03-01 Mpi Corp 探針測試裝置與其製造方法
KR101933015B1 (ko) * 2012-04-19 2018-12-27 삼성전자주식회사 반도체 장치의 패드 구조물, 그의 제조 방법 및 패드 구조물을 포함하는 반도체 패키지
US10910330B2 (en) * 2017-03-13 2021-02-02 Mediatek Inc. Pad structure and integrated circuit die using the same
KR20240015188A (ko) 2022-07-26 2024-02-05 주식회사 메디포 소양증 완화 및 피부장벽 회복용 조성물

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213422A (ja) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp 半導体装置およびそのボンディングパッド構造
US7265045B2 (en) * 2002-10-24 2007-09-04 Megica Corporation Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
US7148574B2 (en) * 2004-04-14 2006-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding pad structure and method of forming the same
US7646097B2 (en) * 2005-10-11 2010-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pads and methods for fabricating the same
US7656045B2 (en) * 2006-02-23 2010-02-02 Freescale Semiconductor, Inc. Cap layer for an aluminum copper bond pad

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543717A (zh) * 2012-01-13 2012-07-04 杭州矽力杰半导体技术有限公司 一种半导体器件的金属层结构、制造方法及其应用其的一种半导体器件
CN102543717B (zh) * 2012-01-13 2014-03-12 矽力杰半导体技术(杭州)有限公司 一种半导体器件
CN109698158A (zh) * 2017-10-20 2019-04-30 三星电子株式会社 包括通孔阵列的集成电路及其制造方法
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