CN101471312A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN101471312A
CN101471312A CNA2008101906342A CN200810190634A CN101471312A CN 101471312 A CN101471312 A CN 101471312A CN A2008101906342 A CNA2008101906342 A CN A2008101906342A CN 200810190634 A CN200810190634 A CN 200810190634A CN 101471312 A CN101471312 A CN 101471312A
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reflection coating
semiconductor device
dielectric film
doping
layer
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昔壮衒
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DB HiTek Co Ltd
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Dongbu Electronics Co Ltd
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Abstract

本发明公开一种半导体器件及其制造方法。该半导体器件包括：层间介电膜，位于衬底上；插塞，位于层间介电膜中；金属层，位于插塞上；以及掺杂抗反射涂覆(ARC)层，位于金属层上。本发明可通过使用等离子体增强PEUSG工艺，改善介于层间介电膜与金属线之间的界面表面的特性，在张应力方面增强介电膜－金属膜的界面特性。因此，能最小化烧结工艺之前/之后的应力变化，并能有效减少或防止由金属提升和IMD裂缝而引起的半导体器件的焊盘孔隙效应。另外，能够防止由焊盘孔隙效应而引起的产品外部的缺陷，改善产品的可靠性。在形成金属线时，通过原位工艺形成掺杂ARC层，可使得热应力变化最小化。

Description

半导体器件及其制造方法
技术领域
本发明的实施例涉及一种半导体器件及其制造方法。
背景技术
在半导体器件中，金属化(metallization process)工艺是通过导通插塞(via plug)工艺与金属线工艺来执行的。另外，抗反射涂覆(ARC)层可能会在金属线上形成。
与此同时，在执行金属化工艺之后，为了改善半导体器件的性能，可执行基于热处理的烧结工艺(sintering process)。
然而，在现有的制造工艺中，烧结工艺可以产生热应力，并且金属线与层间介电膜的热膨胀系数之间的不同可能导致缺陷或问题。例如，由于金属线与抗反射涂覆层之间的界面(interfacial)反应，金属提升(lifting)与金属电介质间(IMD)裂缝(crack)可能变得越来越严重。因此，可能产生焊盘孔隙(pad hole)现象，这种现象将金属层与金属焊盘的预设区(导通阵列区)分离。这可能导致器件外部的缺陷，并且可能降低器件的可靠性。
另外，在现有的工艺期间，由于热应力，可能在金属线与抗反射涂覆层之间产生金属空隙(void)。
发明内容
本发明的实施例提供一种半导体器件及其制造方法。此处描述的器件和方法通过改善层间介电膜和金属线之间的界面表面(interfacial surface)的特性，能够最小化或防止与热应力有关的问题。
本发明的实施例也提供一种半导体器件及其制造方法，通过改善层间介电膜和金属线之间的界面表面的特性，能够防止在执行烧结工艺时由于热应力而产生金属空隙。
根据本发明的实施例，一种半导体器件包括：层间介电膜，位于衬底上；插塞，位于层间介电膜中；金属层，位于插塞上；以及掺杂抗反射涂覆(ARC)层，位于金属层上。
根据本发明的其他实施例，一种半导体器件的制造方法包括如下步骤：在衬底上形成层间介电膜；在所述层间介电膜中形成插塞；在所述插塞上形成金属层；在所述金属层上形成掺杂抗反射涂覆(ARC)层；通过选择性地蚀刻所述金属层和所述掺杂ARC层，形成金属线；以及烧结所述金属线。
在本发明的半导体器件及其制造方法中，可通过使用等离子体增强无掺杂硅酸盐玻璃(PE USG)工艺，改善介于层间介电膜与金属线之间的界面表面的特性，在张应力方面增强介电膜-金属膜的界面特性。因此，能最小化烧结工艺之前/之后的应力变化，并能有效减少或防止由金属提升和IMD裂缝而引起的半导体器件(例如CMOS图像传感器(CIS))的焊盘孔隙效应。另外，根据本发明的实施例，能够防止由焊盘孔隙效应而引起的产品外部的缺陷，使得改善产品的可靠性。
另外，在形成金属线时，通过原位工艺(in-situ process)形成掺杂ARC层，可使得根据烧结工艺的热应力变化最小化。因此，可有效防止图像传感器的金属空隙。另外，能够改善应力迁移(SM)特性。因此，可确保金属化工艺的裕度，并且能够改善半导体器件(例如CMOS图像传感器)的可靠性。
附图说明
图1是示出根据本发明实施例的半导体器件的示例性金属线的剖视图；以及
图2和图3是示出根据本发明实施例的半导体器件的示例性金属线由于在多种温度下的热处理而引起的应力变化的图表。
具体实施方式
在下文中，将参照附图详细地描述根据本发明实施例的半导体器件及其制造方法。
在下述多种实施例的描述中，应当理解，当涉及层(或膜)位于另一层“上”或“下”时，该层可以直接位于另一层上或下，或者也可以存在中间层。
此外，本发明并不限于图像传感器，而是可以应用到所有使用抗反射涂覆(ARC)层和烧结工艺的半导体器件中。
实施例
图1是示出根据本发明实施例的半导体器件的示例性金属线的剖视图。
通常，半导体器件包括形成在衬底(未示出)上的层间介电膜110，形成在层间介电膜110中的插塞123，形成在插塞123上的金属层240，以及形成在金属层240上的掺杂抗反射涂覆(ARC)层250。
在优选实施例中，可通过使用等离子体增强无掺杂硅酸盐玻璃(PE USG)形成层间介电膜110，但不限于此。在其它实施例中，层间介电层可包括氮化硅、富硅氧化硅(SRO)、TEOS(例如通过CVD由正硅酸乙酯(tetraethylorthosilicate)和氧形成的氧化硅)、体电介质(例如，一层或多层掺杂氟或硼和/或磷的氧化硅层(FSG，BSG，PSG和/或BPSG))、二氧化硅或上述的组合。在其它变化中，层间介电膜可包括金属沉积前(pre-metal)电介质(PMD)或金属层间电介质(IMD)。
此外，在一些实施例中，在形成插塞123之前，可在导通孔中形成扩散阻挡层121，该扩散阻挡层121位于层间介电膜110和下部金属的表面上。在一些实施例中，扩散阻挡层121可包括Ti、TiN、WN、TiW合金或上述的组合，例如Ti上TiN双分子层或Ti上TiW双分子层。
掺杂ARC层250可为掺杂TiNx层，在优选实施例中，x小于1。在其它实施例中，掺杂ARC层250可为包括Ti和TiN的层。在一些变化中，掺杂ARC层可包括富Ti的TiN或非当量(non-stoichiometric)的TiN(例如TixNy，其中x：y为从1.1：1到1.5：1或从1.1：1到2：1，或上述范围之间的任意范围的值)。掺杂ARC层250的厚度范围可为
Figure A200810190634D00061
到
Figure A200810190634D00062
但不限于此。
仍然参见图1，在一些实施例中，金属线200可进一步包括形成在金属层240之下的衬垫层(liner layer)230。金属层240可包括铝或含有铜、钛、硅等的铝合金，或本领域公知的任意其它适合的金属。在替代实施例中，金属层240可包括铜镶嵌金属或双镶嵌金属。此外，衬垫层230可包括第一衬垫层231和第二衬垫层232。在一些实施例中，第一衬垫层231包括Ti或Ta，第二衬垫层232包括TiN、TaN或TiW。
图2和图3是示出根据对本发明的金属线进行多种热/温度处理的应力变化的图表。
具体地，图2是显示由于在不同温度下加热上面具有金属线的器件而引起的热应力变化的图表。在现有技术中(“POR”图表)，热应力根据温度非常迅速地变化。
相反，如图2所示，根据本发明(“PE-USG/原位ARC”)实施例的半导体器件在层间介电膜110和金属线200之间具有张应力特性。另外，在热处理(例如450℃烧结工艺)之前/之后的应力变化小于现有的IMD/金属的应力变化，可使得因热移动(thermal budge)而引起的影响最小化。这种界面应力的减小被认为是归因于制造金属线时的PE USG/原位ARC工艺。
根据本发明的实施例，PE USG/原位ARC工艺(I)提供对抗热应力的足够的和/或额外的裕度，从而可有效地减少或防止由于450℃的烧结工艺引起的金属提升和IMD裂缝(cracking)而产生的焊盘孔隙效应。
如图3所示，在现有技术中，由于烧结工艺，产生大约为106MPa的非常迅速的应力变化。相反，在本发明中，示出了由于PE USG/原位ARC工艺(I)而产生的大约为8.7MPa的张应力特性。
换句话说，在根据本发明实施例的半导体器件中，使用PE-USG形成层间介电膜110，并且掺杂ARC层250通过原位工艺沉积在金属层240上，可使得因烧结工艺而引起的热应力变化最小化。因此，可有效限制图像传感器或其它半导体产品的焊盘孔隙效应或金属空隙。
在下文中，将参照图1描述根据本发明的半导体器件的制造方法。
层间介电膜110形成在衬底(未示出)上。在多种实施例中，层间介电膜110可包括金属沉积前电介质(PMD)或金属层间电介质(IMD)。
层间介电膜110可包括PE USG(例如作为顶层或倒数第二层)，但不限于此。在一些实施例中，可在温度约为400±40℃时执行PE USG工艺，但不限于此。
在下文中，将描述包括PE USG的层间介电膜110的特性。如现有工艺中所示，随着层间介电膜110变得更加紧致(compressive)，或随着温度增加，热膨胀系数在金属中会有较大的差别。更进一步，来自金属层240的下拉力(push-down force)可能增加，从而很容易产生金属空隙。
与此同时，当与使用PE CVD的IMD工艺相比时，使用HDP CVD的IMD工艺通常会导致衬底更大的温度变化。因此，由于热应力，可能产生金属层的金属提升、金属空隙以及电阻率(Rs)漂移。为解决上述问题，根据本发明的实施例，沉积PE USG以代替更加紧致的HDP USG，可防止金属空隙。
在沉积层110之后而沉积层200之前，通过图案化和蚀刻(例如使用光致抗蚀剂)层间介电膜110形成导通孔，并可在导通孔中形成插塞123。插塞123可以是接触插塞或导通插塞。
在一些实施例中，可通过CVD或溅射，在插塞123和层间介电膜110之间进一步形成扩散阻挡层121。
在形成导通孔之前，可使用硅烷(SiH4)和氧源(例如O2)，通过等离子体辅助CVD在层间介电膜110上进一步形成覆盖层(cap layer)。
在各种实施例中，可在层间介电膜110和插塞123上进一步形成衬垫层230。衬垫层230可包括第一衬垫层231，以及形成在第一衬垫层231上的第二衬垫层232。例如，衬垫层230可包括Ti衬垫层231和TiN衬垫层232，但不限于此。
之后，在衬垫层230上形成金属层240。例如，金属层240可包括AlCu，但不限于此。
然后，在金属层240上形成掺杂ARC层250。形成掺杂ARC层250的步骤可包括形成第一ARC层(未示出)以及通过原位工艺在第一ARC层上形成第二ARC层(未示出)。
例如，第一ARC层可包括Ti层。第二ARC层可包括TiN层并通过原位工艺形成。但是，本发明不局限于此。
可选择地，掺杂ARC层250可包括掺杂TiNx层，在Ti层形成之后，该掺杂ARC层通过原位工艺形成TiN层来形成，使得TiAl3(TiAl3由Ti层和来自AlCu层240的铝之间的界面反应而产生)最小化。因此，可有效防止因烧结工艺引起的金属空隙。
在下文中，将更详细地描述形成掺杂ARC层250的工艺。
根据示例性实施例，在形成掺杂ARC层250时，第一ARC层的厚度是第二ARC层厚度的20％至50％。
例如，掺杂ARC层250的两层总厚度的范围约为300
Figure A200810190634D0009133659QIETU
至375
Figure A200810190634D0009133659QIETU
。随着掺杂ARC层250厚度的增加，可有效防止由TiAl3引起的金属线的体积收缩，从而改善表面形态(surface morphology)和Rs漂流(drift)特性。另一方面，可改善金属的电迁移(EM)和/或应力迁移(SM)特性。
然而，由于氢(H)陷阱会因Ti而增加，所以可降低金属层240和/或掺杂ARC层250的暗特性。因此，第一ARC层(例如Ti层)的厚度为50
Figure A200810190634D0009133659QIETU
至125
Figure A200810190634D0009133659QIETU
。另外，当TiN层的厚度大约为250
Figure A200810190634D0009133659QIETU
时，在光刻工艺中可保证足够的裕度。
在示例性实施例中，可使用范围约为5kW至10kW功率形成掺杂ARC层250。
此外，第一ARC层的沉积率(D/R)可高于第二ARC层的D/R。例如，ARC Ti层的D/R可增加(例如增加到至少1000
Figure A200810190634D0009133659QIETU
/分钟或大于该最小值的任意值，例如至少2000
Figure A200810190634D0009133659QIETU
分钟、4000
Figure A200810190634D0009133659QIETU
/分钟或6000
Figure A200810190634D0009133659QIETU
/分钟)以最小化TiAl3。相反，TiN层的D/R可减少(例如减少到至多2000
Figure A200810190634D0009133659QIETU
/分钟或大于该最小值的任意值，例如至多1500
Figure A200810190634D0009133659QIETU
/分钟、1000
Figure A200810190634D0009133659QIETU
/分钟或500
Figure A200810190634D0009133659QIETU
/分钟)以形成致密膜(dense film)。这样可在光刻工艺中使用显影(developer)来防止对铝(Al)的侵袭。
可在约为50℃或更低的温度下执行形成掺杂ARC层250的工艺。换句话说，可在温度约为50℃或更低的温度下沉积Ti层和TiN层。
在一些实例中，由于长时间保持在腔室(例如在200℃的温度下)中而引起Cu偏析(segregation)(形成θ相位)，可使金属线短路(shorten)，此时会出现问题。因此，可导致成品率降低。因此，为了防止上述问题，优选的是在50℃或更低的温度下执行形成掺杂ARC层的原位ARC工艺。
在一些实施例中，可在应用流率为60sccm到100sccm的氩(Ar)气的气氛中形成第一ARC层，并在应用流率为40sccm到60sccm的Ar气的气氛和应用流率为80sccm到120sccm的氮(N2)气的气氛中形成第二ARC层。
例如，在一个示例性实施例中，为了形成致密掺杂TiNX膜结构，原位ARC工艺可分别使用80sccm的Ar(例如在Ti沉积期间)和50/100sccm的Ar/N2(例如在TiN沉积期间)的工艺气体。以期在随后的光刻工艺中通过显影来防止Al的侵袭。
之后，选择性地蚀刻金属层240和掺杂ARC层250，以形成金属线200。
随后，可针对(with respect to)包括金属线200的衬底执行烧结工艺。
在此处描述的根据各种实施例的半导体器件及其制造方法中，由于IMD/金属膜在张应力方面增强的特性，所以通过PE USG工艺可改善介于层间介电膜与金属线之间的界面表面的特性。因此，能最小化烧结工艺之前/之后的应力变化，并能有效限制由金属提升和IMD裂缝而引起的半导体器件(例如，CMOS图像传感器(CIS))的焊盘孔隙效应。另外，根据本发明的实施例，能够防止由焊盘孔隙效应而引起的产品外部的缺陷，使得改善产品的可靠性。
另外，根据此处描述的示例性实施例，在金属线形成时，可通过原位工艺形成掺杂ARC层，使得最小化因烧结工艺而引起的热应力变化。因此，可有效防止图像传感器的金属空隙。另外，由于改善SM特性，所以可确保金属化工艺的裕度，并能够改善图像传感器的可靠性。
本发明不应该局限于这些示例性实施例，而可由本领域普通技术人员在以下所附的本发明的权利要求的精神和范围之内对本发明进行多种改变和改进。
在本说明书中，对于“一个实施例”、“一实施例”、“示例性实施例”等的任意引用表示结合所述实施例所描述的特定特征、结构或特性被包括在本发明的至少一个实施例中。在说明书中各处的这类短语的出现不必都涉及相同的实施例。此外，当结合任意实施例描述特定特征、结构或特性时，可认为在本领域普通技术人员所属范围内，可结合其它实施例实现这种特征、结构或特性。
尽管对实施例的描述中结合了其中多个示例性实施例，但可以理解的是本领域技术人员完全可以推导出许多其它变化和实施例，并落入本公开内容的原理的精神和范围之内。特别是，可以在所述公开、附图和所附权利要求的范围内对组件和/或附件组合设置中的排列进行多种变化和改进。除组件和/或排列的变化和改进之外，其他可选择的应用对于本领域技术人员而言也是显而易见的。

Claims (20)

1.一种半导体器件，包括：
介电膜，位于衬底上；
插塞，位于所述介电膜中；
金属层，位于所述插塞上；以及
掺杂抗反射涂覆层，位于所述金属层上。
2.如权利要求1所述的半导体器件，其中所述介电膜包括等离子体增强无掺杂硅酸盐玻璃。
3.如权利要求1所述的半导体器件，其中所述掺杂抗反射涂覆层包括掺杂TiNx层。
4.如权利要求1所述的半导体器件，还包括扩散阻挡层，位于所述插塞和所述介电膜之间。
5.如权利要求1所述的半导体器件，其中所述掺杂抗反射涂覆层包括TiNx，其中x小于1。
6.如权利要求1所述的半导体器件，其中所述掺杂抗反射涂覆层的厚度为300
Figure A200810190634C0002142001QIETU
至375
Figure A200810190634C0002142001QIETU
。
7.如权利要求1所述的半导体器件，其中所述掺杂抗反射涂覆层包括第一Ti抗反射涂覆层和第二TiN抗反射涂覆层。
8.如权利要求1所述的半导体器件，还包括衬垫层，位于所述金属层之下。
9.如权利要8所述的半导体器件，其中所述衬垫层包括第一Ti衬垫层和第二TiN衬垫层。
10.一种半导体器件的制造方法，该方法包括如下步骤：
在衬底上形成介电膜；
在所述介电膜中形成插塞；
在所述插塞上形成金属层；
在所述金属层上形成掺杂抗反射涂覆层；
通过选择性地蚀刻所述金属层和所述掺杂抗反射涂覆层，形成金属线；以及
烧结所述金属线。
11.如权利要求10所述的方法，其中形成所述介电膜的步骤包括等离子体增强CVD。
12.如权利要求10所述的方法，其中所述介电膜包括无掺杂硅酸盐玻璃。
13.如权利要求10所述的方法，其中形成所述掺杂抗反射涂覆层的步骤包括：
形成第一抗反射涂覆层；以及
在所述第一抗反射涂覆层上原位形成第二抗反射涂覆层。
14.如权利要求13所述的方法，其中所述第一抗反射涂覆层包括Ti，并且所述第二抗反射涂覆层包括TiN。
15.如权利要求14所述的方法，其中所述掺杂抗反射涂覆层包括掺杂TiNx。
16.如权利要求13所述的方法，其中所述第一抗反射涂覆层的厚度是所述第二抗反射涂覆层厚度的20％至50％。
17.如权利要求13所述的方法，其中所述第一抗反射涂覆层的沉积率高于所述第二抗反射涂覆层的沉积率。
18.如权利要求10所述的方法，其中所述掺杂抗反射涂覆层在50℃或更低的温度下形成。
19.如权利要求10所述的方法，还包括在所述插塞和所述介电膜之间形成扩散阻挡层。
20.如权利要求10所述的方法，还包括在所述介电膜上形成衬垫层。
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