CN101449256A - 对载明并行和依赖运算的指令矩阵进行处理的装置和方法 - Google Patents

对载明并行和依赖运算的指令矩阵进行处理的装置和方法 Download PDF

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CN101449256A
CN101449256A CNA2007800173174A CN200780017317A CN101449256A CN 101449256 A CN101449256 A CN 101449256A CN A2007800173174 A CNA2007800173174 A CN A2007800173174A CN 200780017317 A CN200780017317 A CN 200780017317A CN 101449256 A CN101449256 A CN 101449256A
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matrix
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CN101449256B (zh
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M·A·阿卜杜拉
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Intel Corp
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Soft Machines Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products

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Abstract

执行块的矩阵形成多行和多列。多行支持指令的并行执行，多列支持依赖指令的执行。执行块矩阵处理载明并行指令和依赖指令的单个指令块。

Description

对载明并行和依赖运算的指令矩阵进行处理的装置和方法
技术领域
[0001]本发明主要涉及计算机体系结构。更具体地，本发明涉及一种用于处理指定并行运算和依赖运算的矩阵指令的计算机体系结构。
背景技术
[0002]改善计算机体系结构性能是一个很困难的任务。已经通过频率变标(frequency scaling)、单指令多数据(SIMD)、超长指令字(VLIW)、多线程和多处理器技术来寻求上述的性能改善。这些方法着重于改善程序执行的吞吐量。上述技术中的很大一部分要求软件显式(explicitly)地呈现出并行性。与此不同的是，频率变标在改善吞吐量和延迟的同时无需软件显式地标记并行性。近来，频率变标面临着功耗壁垒(power wall)问题，所以很难通过频率变标进行改进。因此，除非表示出大规模的显式软件并行(explicitsoftware parallelization)，否则很难增加吞吐量。
[0003]鉴于上述问题，人们期望在不依赖于频率变标和大规模的显式软件并行的前提下改善计算机体系结构的性能。
发明内容
[0004]执行块矩阵形成多行和多列。多行支持指令的并行执行，而多列支持依赖指令的执行。执行块矩阵处理载明并行指令和依赖指令的单个指令矩阵。
附图说明
[0005]参考详细说明并结合附图，本发明将得到更完整地阐释，在附图中：
[0006]图1表示按照本发明实施例的支持执行并行指令和依赖指令的体系结构；
[0007]图2A表示映射串行指令以在本发明的执行矩阵中产生并行和依赖运算；
[0008]图2B表示对本发明执行矩阵进行的运算映射；
[0009]图3表示按照本发明实施例可能用到的一行执行块；
[0010]图4A表示按照本发明实施例可能用到的执行块和支持寄存器文件及缓冲器；
[0011]图4B表示按照本发明实施例配置的寄存器文件；
[0012]图5表示可用于本发明缓冲器的各种数据结构；
[0013]图6表示按照本发明实施例可使用的流水线；
[0014]图7表示按照本发明实施例的矩阵指令处理；
[0015]图8表示对本发明执行块进行运算映射；
[0016]图9表示按照本发明实施例使用的矩阵缓冲器；
[0017]图10A表示实现本发明运算的通用单元；
[0018]图10B表示用于图10A中4位加法器的超前进位加法器的1个位单元；
[0019]图11表示按照本发明实施例配置的延时切片体系结构(TLSA)单元；
[0020]图12表示按照本发明实施例的交错结构中的多个TLSA单元；
[0021]图13表示现有的乘法运算技术；
[0022]图14表示按照本发明实施例采用的延时乘法运算技术；
[0023]图15表示现有的布斯编码乘法；
[0024]图16表示实现图15的布斯编码乘法的逻辑；
[0025]图17表示按照本发明实施例的布斯编码乘法；
[0026]图18表示实现图17的布斯编码乘法的逻辑；
[0027]图19表示按照本发明实施例配置的存储器/寄存器文件数据块；
[0028]图20表示按照本发明实施例配置的时间切片存储器；
[0029]图21表示按照本发明实施例配置带有转置/移位单元的TLSA体系结构；
[0030]图22表示按照本发明实施例配置的浮点乘累加单元。
在所有附图中，相似的附图标记指代对应的部分。
具体实施方式
[0031]允许非显式并行软件在单处理器硬件上执行是非常有益处的，这种单处理器硬件能够在短的延迟流水线(latency pipeline)中处理大量指令。当前解决方案的现有观点为；超标量处理器可以在峰值瞬间的一个周期内实际处理4-5条指令，这类似于好的VLIW编译器在峰值瞬间实现的处理量。人们已经认识到实际上无法实现超标量处理器在单个周期/瞬间内调度10条指令。类似地，如果编译器尝试并行处理用于带有10个时隙的VLIW体系结构的通用程序，则会导致留下大量未填充的时隙。
[0032]本发明提供的体系结构和处理器实现了在短的流水线中高度并行地读数、调度、解码和执行多条指令，极大地改善了执行吞吐量，同时保持了单处理器流水线运算的更优化的延迟，并具有高效的分时、功率、面积和路径。
[0033]在这个被称为超大指令矩阵(Ultra Large Instruction Matrix，ULIM)的新体系结构中，固定大小的指令矩阵模板被调度为作为并行和依赖指令组的矩阵在硬件中执行。与使用超长指令宽度模板仅对并行指令进行调度的VLIW不同，ULIM体系结构的模板封装了并行指令和依赖指令的指令组。这可以被看作二维模板矩阵，其中横向分配并行指令，同时仅纵向分配依赖指令。这个模板以一个指令矩阵的形式被发送到执行硬件，其中各个执行块处理一个指令矩阵。
[0034]图1表示这种模板，其中，如果将一个指令放入时隙101，那么另一个可与其并行执行的指令可放入与其处于同一行的并行时隙1到N中的任何一个中。然而，与设置在时隙101中的指令相依赖的指令不能被放入相同的行，而是必须放入随后的行102(例如，串行时隙1的并行时隙0)。标记为102的时隙接收101产生的结果、或外部输入操作数、或这二者的结合作为输入。这种指令模板的执行模型是任意行的指令都在下一行的指令执行之前执行。
[0035]ULIM指令组可由ULIM编译器静态调度，或者由ULIM硬件组成单元动态调度。如果与传统体系结构进行比较，那么这种体系结构的意义则非常明显。在传统体系结构中，单行N1并行指令可放进一个例如VLIW或SIMD模板的模板中。这意味着每个周期都可以执行N1个指令(全部指令都必须保证是并行的，这对于很大的N而言是非常严格的约束)。另一方面，通过在每个行边界的流水线执行，ULIM体系结构在每个周期可执行N1*N2个指令。尽管每个中周期执行N1*N2个指令，ULIM体系结构仅有如下的相同约束：确保并行执行N1个指令。
[0036]指令矩阵模板可由编程器或编译器/硬件格式程序构建，其中二者都不需要被限制成仅找到并行指令以调度每个周期。有效的并行指令可以被提取出来并且按行横向设置。通过在后续行中设置依赖指令，可以增加并行指令。矩阵可以在单个或多个周期内执行。矩阵可以本地化存储接近执行硬件的操作数，从而优化相互关联的复杂度、面积、速度和功率。
[0037]参考图2A的实例，本发明得到更完整的说明。图2A表示由单个串行程序流表示的指令序列200的实例。该图也表示如何对指令分组，从而形成在矩阵模板中采用的兼有串行时隙和并行时隙的单指令矩阵。矩阵模板被用于执行块201。执行块201包括乘法单元202、浮点加法单元204、加载单元206、乘累加(multiple accumulate，MAC)单元208、逻辑单元(例如ALU)210和另一个逻辑单元212。
[0038]因此，指令矩阵引用是指并行和串行指令的指令组模板。执行块是指执行指令矩阵的执行单元组。执行单元是执行块内部单独的计算单元(例如，复杂单元和简单单元两者)。
[0039]诸如214之类的直线箭头指出指令之间的依赖性。这种映射可由编译器、前端硬件或运行时环境实现。图2A还表示了格式化运算图，其显示出当矩阵中的指令将在带有并行和串行依赖性指示器的对应硬件位置处被执行时，这些指令在矩阵中的相对物理位置。
[0040]如图2A所示，单数据流程序再形成为静态确定串行执行的指令以及指令并行的指令矩阵。例如，在图2A的串行单一程序流中，最后一个指令采用R3作为源，同时第四个指令将R3写作结果。通过将最后一条指令放置在紧接着第四条指令所在那行之后的一行中，这就映射在矩阵模板中。线214表示这种依赖性。
[0041]图2B中解释了编码指令及其用于图2A所示模板的源和目的地，其中指令矩阵模板包括用于指令的操作码，并指定操作数和结果寄存器。源和目的地与操作码分离。这样简化了解码阶段、依赖性解析阶段和寄存器/存储器读取阶段。
[0042]如图3所示，可以同时发出几个指令矩阵。图3表示201的指令矩阵运算图，在此表示为301，以及可选配置的指令矩阵运算图300、302和304。可采用下列模型之一来实现同时的发出：
1-MIMD或SIMD：软件/编译器将多个矩阵合并为一个超级矩阵。
2-线程模型：每个矩阵属于分离的软件或硬件线程。
3-动态执行：如果在来自单个流的多个矩阵之间没有依赖性，则可由硬件动态发出矩阵。
[0043]图3中由运算图表示的指令矩阵模板在将这些指令时隙一一对应地映射到执行单元(执行块内部)的硬件上执行。矩阵粒度允许形成基线矩阵并将那些矩阵合并为一个超级矩阵。这在图4A中表示，其中4基线指令矩阵在四个执行块301、300、302和304上并行执行。每个执行程序由两行复杂单元组成。第一行具有3个复杂单元(例如402、404和406)，而另一行具有3个复杂单元(例如408、410和412)。每个复杂单元可操作地进行复杂运算，比如乘法运算、浮点加法运算或者乘-累加运算。因此，比如复杂单元402可以对应于图2的202，复杂单元404可以对应于图2的204等等。
[0044]复杂单元可操作地进行至多4个简单运算，比如ALU运算。因此，这种复杂单元被显示为具有多个操作数和多个输出。这些单元可设置成计算并行运算或者顺序地执行依赖运算。每个基线指令矩阵在线程模式下可以独立于其他矩阵运行，或者多个基线指令矩阵合并成在同一周期内运行的组，作为组成MIMD体系结构的超级指令矩阵。整体矩阵可以在一个周期内执行，或者可在多个周期内按照流水线方式执行。
[0045]作为操作图4A所示的执行引擎来执行图3所示ULIM指令模板的实例，在复杂单元408中执行指令MAC 208，同时在一对408的单元中执行简单逻辑和ALU运算对210。图4A表示与VLIW体系结构的异同。如果在图4A中采用上部3个时隙(402、404、406)执行3个并行指令，那么ULIM模板中的这3个时隙将类似于等效的VLIW指令。利用简单单元(408、410、412)下一行执行3个或更多的并行指令，将意味着正在执行依赖于先前指令的另一个等效VLIW。这样，ULIM体系结构可以被看成在空间中执行，并具有固定延迟、固定数量的多个相互依赖的VLIW指令。另外，该体系结构允许在一个简单时隙中执行单个复杂指令或多个简单指令，而这在VLIW模板中是不允许的。
[0046]图3中的运算图301、300、302和304表示的4个ULIM矩阵可在图4A的硬件上执行。这可以按照3种执行模式之一来实现：要么通过编译器/编程器将这些矩阵集合起来形成MIMD超级指令矩阵，要么每个矩阵可以独立地以线程模式执行，线程模式中分离的线程同时在四个硬件分段(301、300、302和304)上的每个硬件分段上执行。最后一种执行模式可能是利用硬件依赖性检查来确保同时在图4A中的四个不同硬件分段上执行的不同矩阵之间不具有依赖性，从而能够动态地在单个线程中执行4个不同的指令矩阵。
[0047]图4A中的寄存器文件420可选地根据执行模式进行配置。在一种模式下，寄存器文件要么被看作提供4段MIMD宽度的MIMD分段寄存器文件，要么用作4个独立的寄存器文件，每个寄存器文件提供一个分离的线程。寄存器文件还可以支持动态执行模式，其中4段是一个合一的寄存器文件，其中写入一个指定分段中任何寄存器的数据都可由其他分段中的全部单元进行访问。因为不同的执行模式可以在独立线程基线指令矩阵和MIMD超级指令矩阵线程之间转换，所以那些模式之间的转换可以是无缝的。
[0048]每个单指令矩阵是并行指令和依赖指令的混合。此外，每个独立指令可以是标量或SIMD指令。在最细的粒度下，该指令可以类似于对多个字节/字或单个标量实体进行的可变数据宽度SIMD运算。
[0049]在多线程执行模式下，每个寄存器文件及其执行线程的执行单元完全独立于其他寄存器文件及其线程。这类似于每个线程都具有其自己的寄存器状态。然而，可以指定这些线程之间的依赖性。属于一个线程的每个矩阵将在该线程的寄存器文件的执行单元中执行。如果只有一个线程或非线程化单一程序在图4A中的硬件上执行，那么采用下列方法允许属于单个线程/程序的并行矩阵能够访问已写入其他分段内的寄存器中的结果。实现这点的方法是允许任何矩阵将结果写入到4个寄存器文件的任何一个，从而产生其他寄存器文件分段中那些寄存器的拷贝。这在物理上是通过将每个分段的写端口延伸到剩余分段中实现的。然而，因为不能建立有效率的寄存器文件，使得每个存储单元具有的写端口的数量是一个分段单独所需写端口数量的4倍，所以这不是可伸缩的。现在提供一种机制，其中使得寄存器文件的建立不受这种单线程寄存器广播扩展的影响。这种机制如图4B所示。
[0050]图4B显示由24个寄存器组成的寄存器文件的一段，其中属于单个线程的矩阵正在保存位于该分段的24个条目寄存器文件中的执行结果。同时，3个其他的并行矩阵正在图4A中其他3个分段上执行，并且它们的执行结果被广播到这个寄存器文件分段。
[0051]通过将每个矩阵的结果限制到不相重叠的6个寄存器组，将写端口配置成启动单个线程寄存器广播。通过分段写端口实现了这种方法，其中每个写端口写入到寄存器430的分离的组中。来自其他分段的写端口440将写入到不同的不相重叠的寄存器组中。
[0052]如果这是线程模式或MIMD模式，那么由该分段的结果使用那些进入不重叠组的全部写端口，从而利用并写入全部24个条目寄存器文件，并且因为其他分段具有使用独立寄存器的独立代码(意味着本地分段寄存器将需要使用全部寄存器)，所以不进行广播。另一方面，如果使用单线程，那么全部分段协作起来为这个单线程工作。在这种情况下的寄存器总数仅仅为24，因此跨过剩余分段(24条目*3分段)的寄存器可用于互相保存拷贝。通过编译器进行分析以判断矩阵是否可以并行化并对那些有机会并行执行不重叠寄存器组的矩阵进行分配，可以分配这个寄存器组。
[0053]尽管根据全部4个分段写入结果，寄存器文件中的每个存储单元仅仅具有支持一个分段的端口。在传统的寄存器文件中必需支持4个分段，在下面所示的实例中进行了4折(fold)的增加。
[0054]在ULIM基线格式之上，这些体系结构中实现了ULIM中的数据并行性。这是通过允许ULIM模板中的每个指令都是SIMD/MIMD指令来实现的。在前述附图中，每个并行时隙可以支持内部复制的SIMD结构，同时由不同的并行/串行时隙支持MIMD。
[0055]依赖于不同的预期访问性质，能够看到存储器/寄存器或矩阵缓冲器可由指令访问。例如，数据矩阵可以被看作宽数据元(element)的MIMD，小数据元的SIMD，或混合数据宽度SIMD指令的MIMD。
[0056]在图5中，显示了数据的存储器/寄存器矩阵缓冲器布置的2个视图。右侧视图表示每行和每列中的相互垂直的数据元。这样支持不同的MIMD/SIMD数据的组合。左侧视图表示任意行中每个位置的不同元，但是列表示更大数据量元的剩余位数。例如，右侧视图可以表示4条MIMD指令，每条指令对4个不同的SIMD字节进行运算，每条指令是一个字节的并行数据元。同时左侧表示4条MIMD指令，每条指令对纵向布置的32位元进行运算(实际的物理布置不同于所示的逻辑表示)。此外，如果视图是MIMD视图，那么全都属于4分段的一个单独的MIMD寄存器，但是如果该视图不是MIMD视图，那么那些寄存器是4个纵向布置的独立寄存器。
[0057]这个存储器和寄存器文件视图及其对应的执行模式的意义在于，它启动执行单元变形(morph)来执行宽MIMD/SIMD指令(将全部寄存器分段合并成4路MIMD/SIMD)，但是同时4个寄存器文件分段和附加的对应执行单元能作为4个独立单元对4个不同的标量寄存器进行运算，允许以最小粒度级别在执行单元内部以单线程和多线程执行。
[0058]ULIM体系结构具有类似于VLIW或MIMD模板的固定大小的指令模板。与VLIW或MIMD模板不同，ULIM模板允许指定并行指令以及依赖指令两者。写入寄存器以及在通过寄存器名称传达依赖性的矩阵内部的指令依赖性都遵循相同的冯诺依曼指令体系结构。ULIM体系结构另一个值得注意的方面在于，矩阵中每个指令在矩阵中具有固定的预定位置，并且以相对于矩阵中其他指令的固定分时进行执行。ULIM矩阵宽度类似于对应的VLIW模板的宽度。事实上，通过在ULIM模板一个横向行中放置一条VLIW指令，可以将依赖VLIW指令以串行流转换到ULIM模板中。不可能相似于利用VLIW指令流的全部可能的ULIM模板，因为ULIM模板可以包括在一个时隙中处于同一行的一条复杂指令以及在横向相邻时隙中的多条简单指令。
[0059]与执行单独指令的传统体系结构不同，使用组成指令矩阵的矩阵体系结构的优点很多。下面的论述示出了启动和利用本发明指令矩阵和执行块体系结构的机制建立和实现大规模并行单处理器流水线。
[0060]图6表示可以实现的利用ULIM体系结构的处理器流水线。本发明利用一种机制来简化提取(fetch)阶段600、分支(branch)分析和解码阶段608。提取单元600基于指令矩阵而不是基于指令取得代码。通过矩阵大小而不是指令大小来增加这种体系结构的程序计数器。这样意味着在每个周期提取大量指令。为了能够实现上述目的，ULIM矩阵不允许在ULIM矩阵内部存在分支，但可以在ULIM矩阵之间存在分支。分支分析在两种级别上进行。在ULIM矩阵内部，分支被替换为条件执行、条件移动和预测。在矩阵之间，通过路径预计和分支着色对分支进行处理。这样允许分组到矩阵中的大量指令前进通过流水线提取阶段和分支分析阶段。
[0061]在单个矩阵内部沿着侧面并行指令执行依赖指令解除了由编译器构造全部并行指令时隙代码的困难。它也简化了在分数板硬件(score boardhardware)602、分派单元604或硬件调度单元中的数据依赖性检查。这是通过利用矩阵数目作为工具执行矩阵之间的分数板和依赖性保持、而不是利用单独的寄存器或单独的指令实现的。在图7的实例中，分数板仅通过参考矩阵数目2、4和5归纳矩阵8的依赖性优先级，这意味着矩阵8需要从那些矩阵中读出数据结果。分数板依赖性检查不需要参考(reference)单独寄存器或指令信息以维持依赖性分数板。矩阵数目携带这种信息并且足以保持依赖性检查的正确性。依赖于其他矩阵的矩阵内部指令可以在那些矩阵已被执行之后发出。当矩阵依赖于延迟(例如，因为高速缓存未中)时，阻止整个矩阵被分派。在ULIM流水线实现的一个实施例中，延迟解码阶段608，直到该阶段正好在执行阶段之前为止，并且该阶段与寄存器读阶段606并行执行。
[0062]图8表示对ULIM体系结构指令模板进行编码的一个实施例。其关键在于编码和操作数的结构(结果寄存器和源寄存器)。在ULIM模板分离分段中指定指令结果和源操作数的寄存器，而不管指令的操作码并且不管这些指令是复杂运算或简单指令对。这种矩阵格式以明确的矩阵分段的方式列出源和目的地，使得获取源寄存器和目的地寄存器与矩阵内部指令解码无关。这样能实现延迟解码阶段，其中单独指令操作数的实际解码被延迟，直到仅仅先于执行阶段为止，并且这种解码和读取寄存器来启动下一个周期执行并行进行。这样也简化了依赖性分析和分数板实现。
[0063]如果时隙包括复杂指令，比如“乘累加(MAC)”，那么需要4个源并且写回2个结果。如果同一时隙包括两个简单指令，比如Logic和ALU，那么每个指令需要两个源并写回一个结果，其中两者合起来需要4个源并产生两个结果。这使得源和结果的数量与运算类型无关。
[0064]如图4A所示的处理器执行硬件包括寄存器读写机制，其中矩阵操作数缓冲器能够基于每个源在相应的矩阵硬件元上执行的物理位置，汇集所需寄存器源和目的地。这样减少了读写端口数目以及寄存器文件的带宽要求。利用这种矩阵体系结构的特点，在矩阵缓冲器中对源和/或目的地进行缓冲的旁路机制得以简化，其中由每个执行单元关闭或附着到矩阵缓冲器能够比传统的寄存器文件(特别在需要支持如此多的单个执行单元的大型寄存器文件的情况下)提供更短的访问时间以及更大的源和结果端口带宽。
[0065]图9表示本发明的矩阵缓冲器的原理。该图显示指令矩阵操作数缓冲器900连接到执行单元902。在这个实例中，指令矩阵操作数缓冲器900为3个不同的矩阵缓冲源和目的地。尤其重要的是写端口904设置成每个写端口向不同的存储器单元写入。这意味着即使同时写入6个结果，矩阵操作数缓冲器存储器单元仍是单个端口的，所述6个结果相当于传统的6路端口的寄存器文件。此外，每个写端口的扇出(需要驱动的单元)等于矩阵缓冲器中的矩阵数目(在这个实例中仅为3)。这些特征在面积、功率和访问速度方面具有很多的优点，使得这种缓冲器结构具有很好的可伸缩性，并且对于作为高带宽高速寄存器文件的备选非常具有吸引力。
[0066]下列方法描述如何从矩阵操作数缓冲器对寄存器进行写入和访问。每个矩阵正好在或略先于矩阵准备好执行而被分配到矩阵缓冲器中任何可用的矩阵空间中。矩阵需要能够开始执行的远端源(例如不在这个矩阵缓冲器内部的其他矩阵存储器中的源)可以暂时在这个矩阵存储器中分级。
[0067]在执行矩阵之后，结果写入为这个矩阵存储器分配的区域中(图9的矩阵缓冲器内的3个矩阵位置之一)。每个结果被写入到由结果写端口访问的对应位置，而与结果寄存器数目无关。与矩阵位置一起的这个位置被传输到类似于图7所示的分数板机制的消耗矩阵中，使得依赖于该矩阵的每个矩阵将用那些源来自的矩阵位置以及矩阵内部每个源的位置来标记它的寄存器源。矩阵内部的结果位置能够在执行时间由执行硬件传递，或者因为矩阵模板在编译时固定，所以矩阵内部结果位置能伴随着源寄存器数目被软件嵌入矩阵指令模板中。
[0068]基本思想是建立起可伸缩的伴随着寄存器文件的源和结果缓冲器结构，其中那些缓冲器连接到执行单元，从而通过在常规寄存器文件和执行单元之间建立起中间介质的标识方法，在基于位置的矩阵中临时保持数据，以允许更高带宽和速度。可利用矩阵位置和矩阵内部源位置访问那些矩阵缓冲器中的值。例如，通过记录在矩阵缓冲器何处分配该矩阵，以及通过在矩阵内部物理占用的寄存器5的结果的条目编号来索引该矩阵本身的存储器，能够访问通过矩阵20写入的寄存器5。然而，在矩阵被从矩阵缓冲器中解除分配之后，那么矩阵内部的全部条目保持寄存器值将写回实际的寄存器文件并且通过从该时刻往前的寄存器编号来访问。用于寄存器文件的利用矩阵数据缓冲器的基于位置的前述相同标识和访问方法可被用于使用存储缓冲器高速缓冲的存储器访问。
[0069]如果下层硬件是统一的并且是重复的，那么可以容易地通过编译器构造该矩阵的体系结构。它也允许更有效率地使用功率和硅面积。在此，我们引入通用单元的概念，所述通用单元是根据诸如小加法器、逻辑门、复用器(multiplexer)和布斯(booth)单元之类的基础建立元而构成的。
[0070]通用单元的体系结构允许它在每一个通用单元的内部执行全部功能/运算。这意味着每个单元都能够进行加法、乘法、移位、转置(permute)等。这种方法能执行这种通用功能的方式在于它的组成脱离了用于执行简单ALU运算的基础建立元。另一方面，这些简单元级联地执行复杂运算。它也可以处理浮点和整数数据。上述思想有利于理解通用单元的概念，但是它通过简化调度并将机器吞吐量利用到极限，从而获得了显著的优点。在常规的体系结构中，采用分离的单元执行每个运算或功能。它们共享相同的执行端口。这样，当使用一个单元时，没有使用其他单元。此外，传统体系结构中的延迟在它们之间发生变化，使得调度器难于调度它们。相反，在这个通用单元中，对于整个单元统一了延迟，并且调度器可以看到通用单元的对称例化。
[0071]图10A显示这个通用单元的一部分。每个通用单元可以执行不同的执行单元功能，比如乘法器、加法器、移位器、转置器等等。这个实施例显示进位保留加法器和/或普通加法器1000的结构。该单元由基础要件组成，每个要件具有4行(可以是更多或更少的加法器)能并行加8个输入(4个并行/串行的加运算)的加法器。这些加法器然后被构造成组。一行中的每个加法器要么连接到下面一行相同位置地址加法器(以执行串行ALU运算)，要么被连接到下面一行它右侧的加法器以执行乘法运算。该运算可以是C*B+A或A OP B，在每行中形成4个并行/串行ALU运算。另外，这些加法器组有可能具有不同的数据大小。加法器的这种结构允许树执行多操作数加法、乘法、乘累积、差分求和、移位及循环。另外，复用器(未在图中显示)将对齐/转置/移位输入或中间输出，从而获得所需的运算，包括移位和转置运算。布斯单元/位乘单元1002被加到加法器，从而实现乘法。增加其他具体的逻辑、状态、存储器或LUT元，从而提供扩展功能。
[0072]通用单元允许利用与执行乘法运算相同的结构或与用于执行浮点加或浮点乘累积相同的结构实现转置/移位单元。其优点在于允许较少的路径/面积来实现转置/移位逻辑。通过执行2x乘，利用乘结构执行移位或循环(rotate)，其中x是移位计数值。通过分别选择乘积结果的上部分或者下半部，或者在乘积结果的上部分和下部分之间执行＂或＂函数，来实现左移、右移或循环。
[0073]利用基础的2-输入加法器结构，每个元组成一组位。进位保存加法器还可以利用逻辑和MUX(多路复用器)来实现。例如，为了建立32*32元，基组可以由8位或4位基础加法器和MUXES构建，并且能利用修改过的超前进位加法器单元内部逻辑门执行逻辑函数。
[0074]图10B显示用于图10A中4位加法器的修改后的超前进位加法器的基础一位单元，从而要么产生加法器输出，要么产生选择的逻辑输出。通过不在加法器的关键路径中的连接1010和两个4:1复用器1012显示出这种修改。原来的加法器位结构(标记为1014)包括超前进位和求和逻辑。这些图是逻辑表示，其实际电路可能不同。
[0075]4位(或8位)组便于执行各种大小的SIMD宽度以及进行16位运算。通过相同的原理，那些16位的片(tiles)可以级联起来用于更大宽度的数据运算，比如64位运算，同时仍然便于加法和多操作数加法、移位、循环和乘法的8位、16位和32位SIMD运算。
[0076]这种结构背后的基本原理在于能在同一结构上执行并行和串行指令的组合。例如，第一行结构可以执行单个32位ALU，该ALU可以在第二行继之以依赖ALU或者无关ALU等等。4行一起可以执行至多四个32位ALU串行/平行运算，或者单个32位乘法运算。它还可以对子矩阵执行部分宽度SIMD运算。尤其在矩阵数据和指令分段中，在这个通用单元上调度的指令和操作数成为一个组。
[0077]因为在同一周期或在接下来的周期内，对待调度的依赖指令进行流水线处理依赖于所需频率，所以可以利用指令矩阵体系结构在一个周期内对指令进行流水线处理。存在多种方法来利用ULIM体系结构。该系统允许超大指令矩阵调度。并行指令以及依赖指令作为一个矩阵进行调度(这与VLIW中仅能调度并行指令形成对比)。这个矩阵中每个指令或依赖指令可以是标量或SIMD。
[0078]该发明可用很多种方法实现。例如，可以在时钟周期内部分级多个依赖指令。在本发明的这个具体实施例中，可以在一个时钟周期内部分级多个依赖和并行指令。可以在一个周期内开始多个依赖指令；这样减少了程序执行的最优关键路径。将一个单元内的每种基本运算从随后的运算中分离，利用状态元可以对多个依赖指令进行流水线处理。这样增加了流水线执行率。然而，因为时钟速度和额外的状态元，这种结构的功率将增加。状态元可以保持定值，但是利用波(wave)流水线提高了通过该结构提取的数据率。
[0079]该发明也包括延时切片体系结构(Time-Lag Sliced Architecture，TLSA)，其减少了依赖指令的等待时间。延时切片体系结构背后的基本思想在于一种运算通过数字切片产生其结果数字切片。每个切片早于下一个切片一个切片间的延时产生。一旦产生第一个切片，可以开始执行下一个计算，然后产生其自己的切片。在此描述的切片结构是总体结构，适用于计算单元以及寄存器文件和存储器。该体系结构应用于全部算术、移位、整数和浮点运算。
[0080]TLSA用于实现整个系统总体结构，包括存储器和计算。数字切片不必等于固定大小的数字。该发明可以对数字切片方式到达的两个操作数进行运算。本发明可以实现布斯编码乘法器、变量移位器、转置引擎以及浮点加法器和乘法器。
[0081]在设计的执行单元中，普通方法是将算术/逻辑或移位器单元的输出结果的数字或数字位作为一个单输出结果进行同步。该结果要么锁定到存储元或者同时作为一个块分级到接收元中。然而，在这种体系结构中，细粒执行提供或不提供粗粒同步执行。基本思想是在时间和/或空间上分级的延时逻辑切片结构中用公式表示算术或转置/移位运算。执行硬件以延时流连接，其中先前切片执行得更快并且更快产生输出结果的切片，同时后面的切片就需要更多时间来执行并以相对于先前切片延迟产生结果。值得注意的是，即使在单个执行单元内部，比如加法器或转置器内部，也以位/数字的细粒度进行切片。这个体系结构可以利用这种数字/位逻辑电路切片结构来优化逻辑分时关键路径和/或信号路由路径编号和/或执行算术、转置、移位等用于整数和/或浮点运算的面积。该切片可以具有相等的位/数字或不同数目的位/数字。这种体系结构的一个特别的优点在于能够在最后确定全部源指令的输出结果切片之前，开始执行依赖指令。
[0082]图11表示TLSA单元1100，其中数据流入流出切片1102A-1102C。每个切片输出具有相对于前一个切片的延时延迟(d)。这种延时特征允许对该单元进行流水线处理，以便于不同切片的状态元不同步到一个时间，这典型地用于行/分级触发器。
[0083]图11的体系结构包括基础加法器阶段结构，用于计算基础计算任务，诸如多操作数加法或子块乘法等。利用不作为基础任务关键路径的一部分的分级元1104A-1104C，上述计算被级联起来。依赖于被切片的基础计算任务，分级元可以是加法器、复用器或逻辑门。这些分级元1104的延迟最小化并等于时间＂d＂，＂d＂就是每个切片输出和下一个切片输出之间的延迟。
[0084]分级元被选作具有最小的延迟可能，因为它也建立起切片之间的输入操作数切片的延迟。图11中的基础计算任务可采用任意加法器级。那些加法器可以是任何类型，比如是二进位的或进位保留加法器(CSA)。图11的体系结构的优点在于：产生结果的第一切片早于最终结果。第一切片被送到后续运算。
[0085]图12表示本发明的一个实施例，其中多个延时切片单元背对背的交错。在这个实施例中，每个对角线切片表示被分成切片的一个指令计算单元。在此，相对于前一切片的延时处开始执行每个切片。每个单元反馈一个后续的单元。这个实施例显示背对背的四个单元。标记SU1_0引用单元号1的切片号0。SU4_7引用单元号4的切片号7。
[0086]图12所示体系结构允许(如有必要)多个TLSA单元在单个周期内(或者在多个周期)内处理数据。第一单元的下切片反馈第二单元的下切片，并且继而第二单元反馈第三单元，然后第三单元反馈第四单元等。还应当注意到，除第一单元的第一切片反馈第二单元的第一切片之外，它也反馈它自身单元(第一单元)的第二切片。图12表示下列原理：
1-TLSA中的子周期/多周期执行
TLSA允许在一个周期内部执行算术/移位/逻辑运算。图12表示4个单元在一个周期执行，其中每个切片具有延迟的时钟周期。通过同样的方式，在每个单元切片的输出(而不是4的输出)处执行流水线，从而增加多个周期中的吞吐量并在多个周期中进行。
2-异步/同步/波TLSA拓扑
TLSA可以设计成至少3个不同的拓扑或这些拓扑的组合：
A-异步：其中无需同步状态元(例如，触发)，切片输入/输出在周期时间内相互通信。这样允许去除内部流水线状态元，并且启动电源放缓时钟域。
B-同步：每个切片计时成状态元(触发/锁定/多米诺(domino)等等)。这样允许更高的时钟吞吐量和流水线速率。
C-波：在这种拓扑里，一片一片地将数据馈入到单元中，接下来输入的数据快于正常的流水线速率。正常流水线速率依赖于两个状态元之间的逻辑路径的最大时间。波流水线速率依赖于两个状态元之间的逻辑路径的最小时间。
一种有趣的拓扑组合是细粒异步粗粒同步(FGA-CGS)。在这种模式中，利用异步连接的延时切片实现TLSA，其中细粒异步执行提供或不提供粗粒同步执行。基本思想是以这种切片分级处理结构来用公式表示算术或转置/移位运算，其中执行硬件的不同切片的执行在一个延迟流中异步连接，其中的早期的切片具有较少的输入并且更快地执行，然后更快地产生其输出结果。后面的切片具有更多的输入，因此需要更多的时间以相对于早期切片的延迟执行并产生结果。然后每个切片以相对于前面的切片具有延时的同步(或异步)元进行计时。
[0087]图12表示在一个周期内交错的多个TLSA单元(在1个时钟内4个背对背加倍计数器单元)，同时该实现表示单元切片以异步方式(细粒同步)相互通信的FGA-CGS实现，同时在输出到状态元时钟时同步每个切片或背对背切片。每个切片的输出可以同步到不同的时钟(延迟版本)。
[0088]TLSA体系结构支持超大指令矩阵(ULIM)体系结构。在这个TLSA实施例中，整个指令组被调度，其中在上述TLSA簇的实例上调度多个并行指令和依赖指令。每个单元还可以支持SIMD数据，其中数据切片副本被实例化，但是受到相同的指令激励的控制。另外，多个SIMD通用单元的这种组合结构可以被横向地实例化，从而在单个单元上实现MIMD体系结构。这种方法在一个周期内调度包含SIMD指令和依赖指令的并行变化两者的整个指令模板。
[0089]图13表示传统的乘法技术。具体而言，每个B数字乘以A数字的集合，在乘法开始时每个数字必须在乘法执行单元处可用。然后对结果求和。相反，利用本发明，如图14所示，操作数一个数字一个数字地到达。可见图14每行表示乘法运算的部分乘积，但是相对于数字切片到达时间，仅仅包括当前到达和先前到达的数字。
[0090]为了显示如何建立使用布斯编码乘法的逻辑结构来执行延时切片结构，图15显示了传统的布斯编码32位常规乘法器。布斯编码器组顺序将多位相加以产生数字。这种分组可以减少最大数字值，所述最大数字值是通过编号上连续的两个数字的标记组合来表示这些位的。例如，3位数字的最大值为7，但是通过在该数字值左侧加1，则数字7现在变为了-1。利用已标记的数字表示，允许那些已编码数字值达到原始数字值的1/2的最大值。
[0091]图16实现了图15所示利用根值4数字进行常规布斯乘法的传统逻辑结构。选择器1600A、1600B选择被乘数的哪一个倍数来用完可能的已标记值(0，1，-1，2，-2)；通过该乘法器位的布斯编码来确定这种选择。[0092]图17和18显示新的布斯编码方案以及实现这种方案的新的TLSA逻辑结构。注意，传统的乘法器具有连续不断编码的位流，同时TLSA布斯编码器在数字切片边界处在位流中插入O(在这个实例中是8位数字)。无论乘法的符号(最后2位表示符号)，插入的0都不变化。
[0093]图18显示出如何实现新修改的延时切片布斯编码32位乘法器。这种实现相似于图11所示的通用TLSA结构。图18实现如图14和17所示的子乘法运算。
[0094]在ULIM基线格式之上，这些体系结构中实现了TLSA中的数据并行。通过允许SIMD/MIMD的TLSA数据格式中的每个指令按照正交维数组织到TLSA切片中实现了这种方法。图19显示由能够根据计划访问的性质不同而看到的指令访问存储器/寄存器文件数据块的结构。例如，数据块可以看作宽数据元的MIMD、小数据元的SIMD、混合数据宽度SIMD指令的MIMD等等。图19显示执行这种组合的体系结构。单元内的切片可以独立地运算，从而执行子运算。例如，每个8位切片可以执行独立的8位乘法，同时构造一个32位乘法器单元的切片组还可以作为4路SIMD字节乘法器运算。另一方面，单元组可以作为MIMD乘法器。
[0095]图20表示以切片方式访问的存储器。在传统的存储器体系结构中，单个操作数(例如64位整数或浮点操作数)作为整体被提取。在完成地址解码之后，通过读端口读取全部位，读端口必需缓存，从而在存储器中操作数大小的整个宽范围内缓冲使能读出。在TLSA体系结构中，在发生地址解码之后，在与前一个切片之间具有延时的跟随切片的延时模型上发生数据读出和/或写入。这个模型的优点在于，当无需立即解码并驱动整个数据宽度时，该模型能够快速响应存储器。
[0096]图21表示利用数据切片之间延时的具有转置/移位单元的TLSA体系结构。这个优点允许更短的时间来产生早期结果切片和/或更少的路由/面积来实现转置/移位逻辑。在图21中，构造右移移位器来获得以8位数字切片的32位操作数的延时到达。32位输入的第一切片(数字)在时间T0到达，而上一次切片在时间T0+3d到达，其中d是一个MUX延迟。纵向显示在右边的位(0到5)表示移位次数(最大32，任何大于32的值产生零输出，基本上全部数据被移出)。从来自移位器右侧的第一低位数字到达开始执行。然后该单元等待下一个输入数字到达。依赖于移位计数值的位3的值，将数字中的一个数字选到更低的数字位置，这样将判断该数目将右移8位。然后，下一个最高有效位到达，并且选择该新数字，或者利用移位计数值中的下一位，传递在上面的复用器级中选择的数据等等。任何移位计数值零移出的复用器位置将对其输出实现零负载。当最后一个数字到达时，它通过最小数量的复用器级，这样将相对于前一个数字具有最小延迟“d”，从而启动上一个数字对输出的快速传播。
[0097]左移移位器可用关于垂线对称的图21的结构来构造，其中左切片具有较多复用器栈，右切片具有较少的复用器栈。最高有效数字经过最小数目的复用器级。
[0098]切片结构通用单元可以是类似于图10A-10B所述的一个通用单元。它采用相同的切片体系结构技术(TLSA)和/或细粒异步原理。它在每一个通用单元内部执行全部功能/运算。这意味着每个通用单元能够执行加法、乘法、移位、转置等。执行这种通用功能具有低延迟，其方法是以延迟方式每次处理一个单独的切片。它也可以处理浮点和整型数据。通用单元原理通过上述思想变得更为清晰，但是它通过简化调度并将机器吞吐量利用到极限从而实现了重要的优点。在常规的体系结构中，分离的单元用于执行每个运算或功能。它们共享相同的执行端口。因此，当一个单元被使用时，其他单元没有被使用。此外，传统体系结构中的延时是变化的，使得调度器调度它们很难。与此形成对比的是，在这个通用单元中，对于整个单元延迟被统一，并且调度器可看见通用单元的对称实例。
[0099]每个通用单元可以执行不同的执行单元功能，比如乘法器、加法器、移位器等等。另外，这些切片有可能具有不同的数据大小。在这个特定示例中，每个切片的数据宽度大于前一个切片的数据宽度。这种加法器结构允许切片树执行多操作数加法、乘法、乘累积、差分求和等。复用器(未在图中显示)对齐/转置/移位输入或中间输出，从而利用加法器/复用器的通用结构获得所需的运算，包括移位和转置运算。布斯单元/位乘单元1002被加到加法器，从而启用乘法。增加其他具体的逻辑、状态、存储器或LUT元来提供扩展功能。
[0100]ULIM体系结构可以利用已披露的TLSA技术进行时间切片。构建通用单元的其他方法是将其配置为浮点乘累积单元(MAC)。用于建立这个单元的功能模块是乘法器、右移移位器、加法器和左移移位器。这种结构在图22中公开。通用单元可以利用这种结构来执行构造FP-MAC的这些功能中任一功能或这些功能的组合。
[0101]已在上文中描述了上述功能中的每一个，因此可以分别作为TLSA结构实现，然后合并起来作为浮点乘累加TLSA结构。这种结构还可以作为连续切片的ALU或后面乘以ALU或移位等。
[0102]本发明的一个实施例涉及具有计算机可读介质的计算机存储产品，其上具有用于执行各种计算机实现的运算的计算机代码。这种介质和计算机代码可以是为本发明目的而专门设计和构建的，或者是计算机软件领域技术人员公知的并可以获得的。计算机可读介质的实例包括但不限于：诸如硬盘、软盘和磁带之类的磁介质；诸如CD-ROM、DVD和全息装置之类的光学介质；磁光介质；以及专门配置为存储和执行程序代码的硬件设备，比如专用集成电路(ASIC)、可编程逻辑器件(PLD)以及ROM及RAM设备。计算机代码的实例包括机器代码，诸如编译器产生的机器代码，以及由计算机利用解释器执行的包含高阶代码的文件。例如，本发明的一个实施例可利用Java、C++或其他的面向对象的程序设计语言和开发工具来实现。本发明的另一个实施例将以硬线电路代替机器执行软件指令来实现或以硬线电路结合机器执行软件指令来实现。
[0103]以上描述仅用于解释的目的，采用了特定的术语来提供对本发明的透彻理解。然而显而易见的是，对于本领域的技术人员而言，无需这些具体的细节也能够实现本发明。因此，本发明的上述具体实施例的描述仅是出于解释说明的目的。它们不意味着是详尽的，或者将本发明限制为已公开的精确形式；很明显，可以对上述教诲进行各种各样的修改和变更。为了最佳地解释本发明及其实际应用的原理才选择和描述了上述的实施例，因此它们使得本领域的其他技术人员能够最优地利用本发明并且具有各种修改的各种实施例适用于特定用途。本发明的范围由所附权利要求书及其等效内容来界定。

Claims (20)

1.一种装置，包括：
形成多行和多列的执行块矩阵，其中所述多行支持指令的并行执行，以及所述多列支持依赖指令的执行，其中所述执行块矩阵处理载明并行指令和依赖指令的单个指令块。
2.权利要求1的装置，其中所述执行块矩阵形成单处理器流水线的一部分。
3.权利要求2的装置，其中所述单处理器流水线包括提取阶段、分支处理阶段、解码阶段、调度阶段、执行阶段和提交阶段。
4.权利要求3的装置，其中所述提取阶段提取所述单个指令块，并且根据所述指令块的大小增加程序计数器的计数值。
5.权利要求4的装置，其中所述分支处理阶段支持其他指令块的分支。
6.权利要求3的装置，其中所述调度阶段使用块寄存器参考。
7.权利要求3的装置，还包括支持并行块写入的寄存器文件。
8.权利要求1的装置，其中所述执行块支持浮点运算、整数运算、单指令多数据(SIMD)运算和多指令多数据(MIMD)运算。
9.权利要求1的装置，其中所述执行块矩阵形成延时切片体系结构，从而在单个时钟周期内处理并行指令和依赖指令。
10.权利要求9的装置，其中所述延时切片体系结构在执行切片之间形成延时。
11.权利要求9的装置，其中所述执行块矩阵在单个时钟周期内启动多个依赖指令。
12.权利要求11的装置，其中利用分离执行切片的状态元对多个依赖指令进行流水线处理。
13.权利要求9的装置，其中所述延时切片体系结构每次产生一个数字。
14.权利要求13的装置，其中不同的数字具有不同的位宽。
15.权利要求9的装置，其中所述延时切片体系结构包括经修改的布斯编码。
16.权利要求15的装置，其中所述经修改的布斯编码在数字切片边界插入零。
17.权利要求9的装置，其中所述延时切片体系结构包括右移移位器，所述右移移位器使第一组切片数字应用于第一复用器栈，并使第二组切片数字应用于第二复用器栈，其中所述第一复用器栈大于所述第二复用器栈。
18.权利要求9的装置，其中所述延时切片体系结构包括左移移位器，所述左移移位器使第一组切片数字应用于第一复用器栈，并使第二组切片数字应用于第二复用器栈，其中所述第二复用器栈大于所述第一复用器栈。
19.权利要求9的装置，还包括具有延时结构的存储器，以产生第一数据切片，所述第一数据切片后面跟随有延时的第二数据切片。
20.权利要求9的装置，还包括浮点乘累加单元，所述浮点乘累加单元实现乘法运算、加法运算、右移运算、左移运算和混合运算。
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