CN101431021B - Processing method of thin silicon monocrystal polished section - Google Patents
Processing method of thin silicon monocrystal polished section Download PDFInfo
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- CN101431021B CN101431021B CN2008102044456A CN200810204445A CN101431021B CN 101431021 B CN101431021 B CN 101431021B CN 2008102044456 A CN2008102044456 A CN 2008102044456A CN 200810204445 A CN200810204445 A CN 200810204445A CN 101431021 B CN101431021 B CN 101431021B
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Abstract
The invention relates to a method for producing thin monocrystalline silicon polished wafer. The method comprises the following steps: Step 1, monocrystalline silicon is sliced up by adopting wire cutting; Step 2, a slotting double-face grinder which adopts a stainless steel planetary sheet with an internal circle inlaid with a soft rubber ring is adopted to carry out double-surface grinding on the sliced monocrystalline silicon; Step 3, a technique of acid corrosion thinning is adopted, wherein, the removal amount resulted from acid corrosion is 10 micrometers to 60 micrometers; Step 4, a nanometer grinding technique is adopted, wherein, the removal amount resulted from nanometer grinding is 1 micrometer to 25 micrometers; and Step 5, a wax polishing technique is adopted, wherein, the removal amount resulted from wax polishing is 5 micrometers to 30 micrometers. By adopting a new technical route and a new technical procedure for producing new thin monocrystalline silicon polished wafer, the invention effectively improves TTV level, WARP level, TIR level, STIR level and other levels as well as the finished product rate of the thin monocrystalline silicon polished wafer.
Description
Technical field
The present invention relates to semi-conducting material process technology and flow scheme design, the especially IC design of thin silicon monocrystal polished silicon wafer process technology route and technological process.
Background technology
According to conventional art route and technological process, because interior circular knife slimming is subjected to the restriction of Material Strength, so the loss of not only cutting into slices can not be fallen, piece rate can't improve, and angularity (Warp) is big; Because the two-sided lapping hard collision of stainless steel planet sheet and silicon chip, the silicon chip edge breakage rate is higher; Because two-sided lapping damage layer depth, the amount of skimming that direct polishing needs after the caustic corrosion is big, polished silicon wafer total thickness variations (TTV) and evenness (TIR, STIR) level error.Summary is got up, and has three big problems according to the thin polished silicon wafer of conventional art route and technological process processing, that is: 1) and the fragment rate height; 2) piece rate is low; 3) TTV (total thickness variations), Warp (angularity), TIR (total evenness), STIR (local evenness) level are low.
Please refer to shown in Figure 1ly according to conventional art route and technological process, because interior circular knife slimming is subjected to the restriction of Material Strength, so the loss of not only cutting into slices can not be fallen, piece rate can't improve, and angularity (Warp) is big; Because the two-sided lapping hard collision of stainless steel planet sheet and silicon chip, the silicon chip edge breakage rate is higher; Because two-sided lapping damage layer depth, the amount of skimming that direct polishing needs after the caustic corrosion is big, polished silicon wafer total thickness variations (TTV) and evenness (TIR, STIR) level error.Summary is got up, and has three big problems according to the thin polished silicon wafer of conventional art route and technological process processing, that is: 1) and the fragment rate height; 2) piece rate is low; 3) TTV (total thickness variations), Warp (angularity), TIR (total evenness), STIR (local evenness) level are low.Can not satisfy customer requirements.The existence of these problems makes thin polished silicon wafer can't enter suitability for industrialized production at all.
Not only piece rate is low for this existing technology polished silicon slice, and the geometric parameter of polished silicon wafer is bad, and IC client earlier processes device in thick polished silicon wafer, increases the attenuate operation then one, passes through packaging and testing again, and operation is comparatively complicated.
Given this, be necessary to provide a kind of new technology path and technological process in fact, be used to improve the productivity ratio and the quality of IC with the thin silicon monocrystal polished silicon wafer.
Summary of the invention
Technology path that the technical problem to be solved in the present invention is to provide new and technological process improve the Warp level to improve piece rate; Reduce fragment and improve the silicon chip evenness; Can reduce the amount of skimming, thereby improve silicon chip evenness level.
For solving the problems of the technologies described above, the present invention adopts following technical scheme: a kind of processing method of thin silicon monocrystal polished section, and it may further comprise the steps:
Step 1 adopts line cutting section to silicon single crystal;
Step 2, the twin grinder that adopts the fluting mill to grind, stainless steel planet sheet of use liner rubber carries out two-sided lapping to the silicon single crystal after the section on it;
Step 3 adopts the acid corrosion reduction process, and the acid corrosion removal amount is at 10～60 microns;
Step 4 adopts nano-milled technology, and nano-milled removal amount is at 1～25 micron;
Step 5, adopting has wax polishing technology, the wax polishing removal amount is arranged at 5～30 microns; Acid corrosion reduction process in the described step 3 comprises the preparation of mixed acid solution, and described mixed acid solution is that nitric acid, hydrofluoric acid and resiliency acid volume proportion are 2: 1: 1.
As one of preferred version of the present invention, described resiliency acid refers to phosphoric acid or glacial acetic acid.
As one of preferred version of the present invention, in the acid corrosion reduction process in the described step 3,40 ℃ of corrosion temperatures, etching time 30 seconds, 33 microns of acid corrosion removal amounts; Weak base detergent concentration 4%, 60 ℃ of cleaning temperatures, ultrasonic time 5 minutes, 5 minutes rinsing time.
As one of preferred version of the present invention, in the acid corrosion reduction process in the described step 3,35 ℃ of corrosion temperatures, etching time 26 seconds, 30 microns of acid corrosion removal amounts, weak base detergent concentration 4%; 60 ℃ of cleaning temperatures, ultrasonic time 5 minutes, 5 minutes rinsing time.
The present invention effectively improves quality and rate of finished productss such as thin silicon monocrystal polished silicon wafer TTV, WARP, TIR, STIR by adopting a kind of IC of raising with the productivity ratio of thin silicon monocrystal polished silicon wafer and the new technology path and the technological process of quality.
Description of drawings
Fig. 1 is the flow chart that the thin silicon monocrystal polished silicon wafer is made conventional art route and technological process;
Fig. 2 is the flow chart that thin silicon monocrystal polished silicon wafer of the present invention is made new technology path and technological process.
Embodiment
Content of the present invention, advantage and purpose will be set forth in the following description of the embodiments.
This patent embodiment one processes 6 cun heavily doped arsenic N type＜111〉polished silicon slice.
In acid corrosion attenuate operation, mixed acid solution (nitric acid, hydrofluoric acid and resiliency acid are as phosphoric acid, glacial acetic acid etc.) volume proportion is 2: 1: 1,40 ℃ of corrosion temperatures, etching time 30 seconds, 33 microns of acid corrosion removal amounts; Weak base detergent concentration 4%, 60 ℃ of cleaning temperatures, ultrasonic time 5 minutes, 5 minutes rinsing time.In nano-milled operation, nano-milled machine main axis rotation speed 4800rpm, axis feeding speed is 0.8 little meter per second, and the ceramic disk rotating speed is 20rpm, and nano-milled removal amount is 6 microns.At polishing process, the polished silicon wafer number is 6 cun 20, and the thick pH value of throwing is 10, and thick rubbing paste rate of flow is 0.4 liter/minute, 50 ℃ of rough polishing temperature, rough polishing pressure 0.9Mpa, 65 rev/mins of thick ramming head rotating speeds; The middle pH value of throwing is 10, and middle rubbing paste rate of flow is 0.4 liter/minute, 38 ℃ of middle polish temperatures, middle polish pressure 0.35Mpa, 65 rev/mins of middle ramming head rotating speeds; The smart pH value of throwing is 9, and smart rubbing paste rate of flow is 0.45 liter/minute, 39 ℃ of finishing polish temperature, finishing polish pressure 0.7Mpa, 60 rev/mins of smart ramming head rotating speeds.Always the amount of skimming is 11 microns.
This patent embodiment two: process 6 cun heavily doped arsenic N type＜111〉polished silicon slice.
In acid corrosion attenuate operation, mixed acid solution (nitric acid, hydrofluoric acid and resiliency acid are as phosphoric acid, glacial acetic acid etc.) volume proportion is 2: 1: 1,35 ℃ of corrosion temperatures, etching time 26 seconds, 30 microns of acid corrosion removal amounts, weak base detergent concentration 4%; 60 ℃ of cleaning temperatures, ultrasonic time 5 minutes, 5 minutes rinsing time.In nano-milled operation, nano-milled machine main axis rotation speed 4800rpm, axis feeding speed is 0.6 little meter per second, ceramic disk rotating speed 20 rpm, 7 microns of nano-milled removal amounts.At polishing process, the polished silicon wafer number is 6 cun 20, the thick pH value of throwing 10, and thick rubbing paste rate of flow is 0.4 liter/minute, 45 ℃ of rough polishing temperature, rough polishing pressure 1.0Mpa, 55 rev/mins of thick ramming head rotating speeds; The middle pH value of throwing 10, middle rubbing paste rate of flow is 0.35 liter/minute, 37 ℃ of middle polish temperatures, middle rubbing paste rate of flow are 0.35 liter/minute, middle polish pressure 0.3Mpa, 55 rev/mins of middle ramming head rotating speeds; The smart pH value of throwing 9, smart rubbing paste rate of flow is 0.35 liter/minute, 39 ℃ of finishing polish temperature, finishing polish pressure 0.7Mpa, 55 rev/mins of smart ramming head rotating speeds.Always the amount of skimming is 6 microns.
This patent embodiment one, example two results such as following table.
This patent result of implementation
As follows according to the contents of a project and basic principle division that new technology path and technological process are determined:
A. circular knife is cut into the line cutting in changing.Because the wire diameter is littler many than blade substrate thickness, so line cutting loss is few, and unit slice amount is many; Improve and optimize the wire cutting technology technology, can process geometric parameter such as TTV, thin silicon sheet that the Warp level is good.
B. adopt the fluting twin grinder, make planet sheet liner plastic cement.Change the grinding of slotless mill and can reduce the grinding resistance for the fluting mill grinds; The planet sheet that changes no liner plastic cement is the planet sheet that the liner plastic cement is arranged, and has avoided the hard collision of silicon chip and planet sheet.Change fragment rate for these two and be reduced to 0.4% by 1.5%.
C. adopt acid corrosion to eliminate silicon chip affected layer technology.Changing caustic corrosion technology is acid corrosion technology, can improve silicon chip surface fineness, stains thereby reduce silicon chip surface particle.
D. conventional process flow is directly the acid corrosion silicon chip to be polished, and now changes into the nano precision abrasive sheet is polished.Nano-milled is the nano level fine gtinding of silicon chip on hard sucker, can be the decline of silicon chip TTV, TIR after the preceding working procedure acid corrosion and STIR level, the level that returns to; Can remove the corrosion pit of acid corrosion silicon chip surface, thereby can reduce the polishing removal amount, these 2 is the key that improves thin polished silicon wafer TTV, TIR and STIR level.
E. owing to wax polishing is arranged and have the no wax polishing paster mode of pad different, silicon chip can not move relative to the paster dish when wax polishing was arranged, and can solve the fragment problems of filling up no wax polishing generation and TTV, TIR, problem that the STIR level is low.
Thin polished silicon wafer Processing Technology Development trend is:
A. adopt more finer wire to carry out the line cutting, to cut out more silicon chip.
B. develop nano-milled, polishing all-in-one, omitted wax polishing, once finish nano-milled and polishing processing, can do like this more economize, geometric parameter is better.
Technical indicator
| Content | Unit | Standard | Performance |
| Silicon wafer thickness | μm | ≤ SEMI standard | φ4 280～520μm φ5 280～620μm φ6 405～650μm |
| Content | Unit | Standard | Performance |
| TTV (total thickness variations) | μm | ≤5 | φ4 mean 2.6μm φ5 mean 2.7μm φ6 mean 3.2μm |
| TIR (total evenness) | μm | ≤3 | φ4 mean 1.18μm φ5 mean 1.3μm φ6 mean 1.6μm |
| STIR (local evenness) | μm | ≤2 | φ4 mean 0.95μm φ5 mean 1.1μm φ6 mean 1.5μm |
| WARP (angularity) | μm | ≤20 | φ4 mean 15μm φ5 mean 8.1μm φ6 mean 10.3μm |
Silicon chip slice number is increased to 88 slices/kilogram by 74 slices/kilogram, and piece rate improves 20% (is 410 microns calculating by 4 cun slice thicknesses); The polished silicon slice thickness of this processes can drop to 290 microns polished silicon wafer by 525 microns, increases the attenuate operation again after avoiding the IC device to finish; STIR＜1.5 micron, TTV＜5 micron or the like.
New technology path and technological process use the line cutting to improve the silicon chip piece rate, and the fineness that acid corrosion guarantees silicon chip surface adopts nano-milled technology that geometric parameter such as TTV, the STIR etc. of thin silicon monocrystal polished silicon wafer are provided.New technology path and technological process can improve piece rate, reduce fragment, can make mass parameters such as TTV, Warp, TIR, STIR reach international most advanced level.
Newer and conventional art route and technological process, new technology path and technological process improve as follows: slicing process changes the wire cutting machine section into, the corrosion thinning operation changes acid corrosion into, polishing process has changed wax polishing into, has increased nano-milled operation between corrosion thinning operation and polishing process.This patent has adopted the stainless steel planet sheet of liner plastic cement.This patent also respectively to acid corrosion removal amount, nano-milled removal amount, have the wax polishing removal amount to make regulation.
Above-mentioned description to embodiment is can understand and apply the invention for ease of those skilled in the art.The person skilled in the art obviously can easily make various modifications to these embodiment, and needn't pass through performing creative labour being applied in the General Principle of this explanation among other embodiment.Therefore, the invention is not restricted to the embodiment here, those skilled in the art should be within protection scope of the present invention for improvement and modification that the present invention makes according to announcement of the present invention.
Claims (3)
1. processing method of thin silicon monocrystal polished section, it may further comprise the steps:
Step 1 adopts line cutting section to silicon single crystal;
Step 2, the twin grinder that adopts the fluting mill to grind, stainless steel planet sheet of use liner rubber carries out two-sided lapping to the silicon single crystal after the section on it;
Step 3 adopts the acid corrosion reduction process, and the acid corrosion removal amount is at 10～60 microns;
Step 4 adopts nano-milled technology, and nano-milled removal amount is at 1～25 micron;
Step 5, adopting has wax polishing technology, the wax polishing removal amount is arranged at 5～30 microns; Acid corrosion reduction process in the described step 3 comprises the preparation of mixed acid solution, and described mixed acid solution is that nitric acid, hydrofluoric acid and resiliency acid volume proportion are 2: 1: 1.
2. processing method of thin silicon monocrystal polished section as claimed in claim 1 is characterized in that: described resiliency acid refers to phosphoric acid or glacial acetic acid.
3. processing method of thin silicon monocrystal polished section as claimed in claim 1 is characterized in that: in the acid corrosion reduction process in the described step 3, and 40 ℃ of corrosion temperatures, etching time 30 seconds, 33 microns of acid corrosion removal amounts; Weak base detergent concentration 4%, 60 ℃ of cleaning temperatures, ultrasonic time 5 minutes, 5 minutes rinsing time.
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| CN101934492B (en) * | 2010-08-10 | 2011-07-13 | 天津中环领先材料技术有限公司 | Polishing process of high-smoothness float-zone silicon polished wafer |
| CN102241077B (en) * | 2011-06-15 | 2013-12-18 | 安阳市凤凰光伏科技有限公司 | Method for manufacturing similar mono-crystal silicon ingot seed crystal by adopting casting process |
| CN103144024B (en) * | 2011-12-06 | 2015-08-12 | 有研半导体材料有限公司 | Use the silicon polished manufacturing process of 300mm of high-temperature heat treatment |
| CN102490439B (en) * | 2011-12-15 | 2014-04-09 | 天津中环领先材料技术有限公司 | Waxy surface mount device process adopting zone-melt single crystal silicon double-side polished chip for IGBT (insulated gate bipolar transistor) |
| CN102773790A (en) * | 2012-07-30 | 2012-11-14 | 上海申和热磁电子有限公司 | Silicon wafer polishing manufacture procedure method |
| CN103567857A (en) * | 2013-11-04 | 2014-02-12 | 上海申和热磁电子有限公司 | Double-sided polishing process for silicon wafer |
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| CN106914815B (en) * | 2015-12-24 | 2020-06-26 | 上海超硅半导体有限公司 | Grinding method of semiconductor silicon wafer |
| CN110526201B (en) * | 2018-05-25 | 2022-11-01 | 浙江清华柔性电子技术研究院 | Preparation method of flexible silicon wafer |
| CN110526202B (en) * | 2018-05-25 | 2022-11-01 | 浙江清华柔性电子技术研究院 | Preparation method of flexible silicon wafer |
| CN110625835A (en) * | 2019-09-12 | 2019-12-31 | 西安奕斯伟硅片技术有限公司 | Silicon wafer forming processing method |
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| CN113211305B (en) * | 2020-01-19 | 2023-02-14 | 山东浪潮华光光电子股份有限公司 | Method and tool for polishing gallium arsenide LED chip after grinding |
| CN111230605A (en) * | 2020-02-17 | 2020-06-05 | 中环领先半导体材料有限公司 | Method for improving flatness of silicon polished wafer |
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Address after: 201617 no.558, changta Road, Shihudang Town, Songjiang District, Shanghai Patentee after: Shanghai crystal silicon material Co., Ltd Address before: 201617 No. 500 South noble Road, Shanghai, Songjiang District Patentee before: SHANGHAI WAFER WORKS Corp. |