CN101395699A - 将形成于衬底中的过孔平坦化的方法 - Google Patents

将形成于衬底中的过孔平坦化的方法 Download PDF

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Publication number
CN101395699A
CN101395699A CNA2007800074766A CN200780007476A CN101395699A CN 101395699 A CN101395699 A CN 101395699A CN A2007800074766 A CNA2007800074766 A CN A2007800074766A CN 200780007476 A CN200780007476 A CN 200780007476A CN 101395699 A CN101395699 A CN 101395699A
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China
Prior art keywords
protective layer
substrate
conductive via
grinding
absolute altitude
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Pending
Application number
CNA2007800074766A
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English (en)
Chinese (zh)
Inventor
C·阿姆里尼
O·费
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN101395699A publication Critical patent/CN101395699A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H05K2203/1383—Temporary protective insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
CNA2007800074766A 2006-03-08 2007-01-29 将形成于衬底中的过孔平坦化的方法 Pending CN101395699A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/371,658 US20070212865A1 (en) 2006-03-08 2006-03-08 Method for planarizing vias formed in a substrate
US11/371,658 2006-03-08

Publications (1)

Publication Number Publication Date
CN101395699A true CN101395699A (zh) 2009-03-25

Family

ID=38479482

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007800074766A Pending CN101395699A (zh) 2006-03-08 2007-01-29 将形成于衬底中的过孔平坦化的方法

Country Status (5)

Country Link
US (1) US20070212865A1 (enExample)
JP (1) JP2009529244A (enExample)
CN (1) CN101395699A (enExample)
TW (1) TW200802769A (enExample)
WO (1) WO2007120959A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111755384A (zh) * 2020-06-18 2020-10-09 通富微电子股份有限公司 半导体器件以及制备方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8951839B2 (en) * 2010-03-15 2015-02-10 Stats Chippac, Ltd. Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP
US8216918B2 (en) 2010-07-23 2012-07-10 Freescale Semiconductor, Inc. Method of forming a packaged semiconductor device
US20120282767A1 (en) * 2011-05-05 2012-11-08 Stmicroelectronics Pte Ltd. Method for producing a two-sided fan-out wafer level package with electrically conductive interconnects, and a corresponding semiconductor package
US8617935B2 (en) 2011-08-30 2013-12-31 Freescale Semiconductor, Inc. Back side alignment structure and manufacturing method for three-dimensional semiconductor device packages
US8916421B2 (en) 2011-08-31 2014-12-23 Freescale Semiconductor, Inc. Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits
US9142502B2 (en) 2011-08-31 2015-09-22 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits
US8597983B2 (en) 2011-11-18 2013-12-03 Freescale Semiconductor, Inc. Semiconductor device packaging having substrate with pre-encapsulation through via formation
US8685790B2 (en) 2012-02-15 2014-04-01 Freescale Semiconductor, Inc. Semiconductor device package having backside contact and method for manufacturing
US9847315B2 (en) * 2013-08-30 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Packages, packaging methods, and packaged semiconductor devices
MX392422B (es) 2016-06-21 2025-03-24 Orion Ophthalmology LLC Derivados de prolinamida heterociclica
JP7164521B2 (ja) 2016-06-21 2022-11-01 オリオン・オフサルモロジー・エルエルシー 炭素環式プロリンアミド誘導体

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US5110759A (en) * 1988-12-20 1992-05-05 Fujitsu Limited Conductive plug forming method using laser planarization
US5111759A (en) * 1989-12-19 1992-05-12 Juki Corporation Inconstant-thickness workpiece feeding apparatus
US5744285A (en) * 1996-07-18 1998-04-28 E. I. Du Pont De Nemours And Company Composition and process for filling vias
US6620731B1 (en) * 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6380078B1 (en) * 2000-05-11 2002-04-30 Conexant Systems, Inc. Method for fabrication of damascene interconnects and related structures
US6506332B2 (en) * 2000-05-31 2003-01-14 Honeywell International Inc. Filling method
ATE414711T1 (de) * 2001-06-28 2008-12-15 Mountain View Pharmaceuticals Polymerstabilisierte proteinasen
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Industrial Co Ltd Circuit component built-in module and method of manufacturing the same
JP2004079736A (ja) * 2002-08-15 2004-03-11 Sony Corp チップ内蔵基板装置及びその製造方法
JP2004179588A (ja) * 2002-11-29 2004-06-24 Sanyo Electric Co Ltd 半導体装置の製造方法
US20050048766A1 (en) * 2003-08-31 2005-03-03 Wen-Chieh Wu Method for fabricating a conductive plug in integrated circuit
US7208404B2 (en) * 2003-10-16 2007-04-24 Taiwan Semiconductor Manufacturing Company Method to reduce Rs pattern dependence effect
TWI228389B (en) * 2003-12-26 2005-02-21 Ind Tech Res Inst Method for forming conductive plugs
JP4800585B2 (ja) * 2004-03-30 2011-10-26 ルネサスエレクトロニクス株式会社 貫通電極の製造方法、シリコンスペーサーの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111755384A (zh) * 2020-06-18 2020-10-09 通富微电子股份有限公司 半导体器件以及制备方法

Also Published As

Publication number Publication date
TW200802769A (en) 2008-01-01
WO2007120959A3 (en) 2007-12-13
WO2007120959A2 (en) 2007-10-25
JP2009529244A (ja) 2009-08-13
US20070212865A1 (en) 2007-09-13

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Open date: 20090325