CN101388408A - 横向双扩散金属氧化物半导体器件 - Google Patents

横向双扩散金属氧化物半导体器件 Download PDF

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CN101388408A
CN101388408A CNA2008101460149A CN200810146014A CN101388408A CN 101388408 A CN101388408 A CN 101388408A CN A2008101460149 A CNA2008101460149 A CN A2008101460149A CN 200810146014 A CN200810146014 A CN 200810146014A CN 101388408 A CN101388408 A CN 101388408A
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朴日用
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DB HiTek Co Ltd
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Abstract

本发明公开一种横向双扩散金属氧化物半导体器件。在一个示例性实施例中，LDMOS器件包括在p型衬底上形成的第一n型阱，在所述第一n型阱中形成的多个隔离层，在所述多个隔离层的每一个的表面上形成的p型离子注入区域，以及在所述第一n型阱和所述多个隔离层上选择性形成的栅极。本发明涉及具有较高击穿电压和较低导通电阻的横向双扩散MOS器件。

Description

横向双扩散金属氧化物半导体器件
相关申请的交叉引用
本申请要求申请日为2007年9月12日的韩国专利申请No.10-2007-0092597的优先权，在此通过参考将该申请的全部内容合并于本申请中。
技术领域
本发明涉及一种横向双扩散金属氧化物半导体(lateral double diffusedmetal oxide semiconductor(LDMOS))器件。
背景技术
现有的高电压横向双扩散金属氧化物半导体(LDMOS)器件包括位于相对较窄的浅沟槽隔离(shallow trench isolation(STI))氧化层之间的硅区域。通常采用介电降低表面电场(dielectric reduced surface field(RESURF))技术产生较高的击穿电压以形成较窄的STI氧化层。然而，当器件开启时，由于电流流经较窄的STI氧化层，因此导通电阻(on-resistance)也较高。
发明内容
总的来说，本发明的实施例涉及具有较高击穿电压和较低导通电阻的横向双扩散(LD)MOS器件。
在一个实施例中，LDMOS器件包括在p型衬底上形成的第一n型阱，在所述第一n型阱中形成的多个隔离层，在所述隔离层的每一个的表面上形成的p型离子注入区域，以及在所述第一n型阱和所述隔离层上选择性地形成的栅极。
在另一个实施例中，LDMOS器件包括在p型衬底上形成的n型阱，在所述n型阱上形成的p型阱，在所述p型阱中形成的多个隔离层，以及在所述p型阱和所述隔离层上选择性地形成的栅极。
通过该发明内容以简单的形式介绍了概念的选用，在下文的具体实施例中将进一步描述所述概念。该发明内容并非用以辨别权利要求主题的关键特征或必要特性，也并非用于帮助确定权利要求主题的保护范围。此外，可以理解的是前文对本发明的总体描述和下文对本发明的详细描述都是用以举例和解释，并用于对本发明的权利要求提供进一步的解释。
附图说明
本发明实施例将通过下文实施例结合附图进行描述，其中：
图1为LDMOS器件实例的部分透视图；
图2为图1中LDMOS器件实例的平面视图；
图3为图1和图2中LDMOS器件实例的剖面侧视图；以及
图4为LDMOS器件的另一个实例的剖面侧视图。
具体实施方式
在下文的本发明实施例的详细描述中，将对本发明的具体实施例进行详细描述，在附图中示出了其实例。只要可能，附图中相同的附图标记在全部附图中指代相同或相似的部分。对所述实施例进行足够详细的描述以使得本领域技术人员可以实现本发明。并且在不脱离本发明保护范围的情况下，还可以采用其它实施例，并且进行结构、逻辑以及电性等的改变。此外，可以理解的是尽管本发明的各实施例均不相同，但并非独一无二的。例如，在一个实施例中描述的具体特征、结构或特性也可以包含于其它实施例中。因此下文的详细描述并非用于限制，并且本发明的保护范围仅通过随附的权利要求确定，以及具有这些权利要求所赋予的等同物的全部保护范围。
于此，可以理解的是当提到某一层位于另一层或衬底“上”或“下”时，此层可以直接位于另一层或衬底的“上”或“下”，或者其间也可以出现中间层。更进一步，下文中讨论的n型层和p型层通常可以调换。
LDMOS器件的第一实例
图1-图3公开LDMOS器件的第一实例。具体而言，图1为LDMOS器件的第一实例的部分透视图，图2为LDMOS器件的第一实例的部分平面视图，图3为沿图2中的线III-III的LDMOS器件的第一实例的剖面侧视图。
如图1-图3所示，LDMOS器件的第一实例包括在p型衬底110上形成的n型阱121，在所述n型阱121中形成的多个隔离层150，在所述多个隔离层150的表面上形成的p型离子注入区域140，以及在所述n型阱121和所述隔离层150上选择性地形成的栅极160。漏极170和源极180可以在栅极160的任何一侧形成。还可以围绕隔离层150形成p型离子注入区域140。
在图1-图3中的LDMOS器件的第一实施例中，采用STI处理而在所述多个隔离层150的表面上形成p型离子注入区域140，以增加第一实例的LDMOS器件的击穿电压，并降低第一实例的LDMOS器件的导通电阻。特别地，不同于导致相对较窄隔离层的现有的介电降低表面电场(RESURF)技术，第一实例的LDMOS器件是利用p-n结中的耗尽现象(depletionphenomenon)而形成的，其中该p-n结中的耗尽现象会导致相对较宽隔离层150。此外，不同于现有的RESURF技术，STI处理可以阻止电子电流(electronic current)移动距离的增大，其中该电子电流移动距离的增大会在第一实例的LDMOS器件中导致相对较低的导通电阻。
在第一实例的LDMOS器件中，在隔离层150上形成p型离子注入区域140。隔离层150增加的宽度导致作为隔离层150之间的有源区的n型阱121。因此，在导通状态时，有源区相对较宽的宽度允许相对较多的电子电流流过，使得第一实例的LDMOS器件的导通电阻相对较低。在关断(off state)状态时，在p型离子注入区域140和第一n型阱121之间形成耗尽层(depletionlayer)，所以击穿电压相对较高。
第一实例的LDMOS器件可以包括在漂移区中仅仅形成n型阱N1 121。可选择地，第一实例的LDMOS器件可以包括在漂移区中形成n型阱N1 121和第二n型阱N2 122。
如图3所示，当第一实例的LDMOS器件包括在漂移区中形成n型阱N1121和第二n型阱N2 122时，在第一n型阱121的情形下，两个p型区域140之间发生相互耗尽(mutual depletion)。在第二n型阱122的情形下，由于在p型衬底110和第二n型阱122之间的耗尽层增加，使得漂移区可以完全耗尽。
此外，可以控制第一n型阱121和第二n型阱122的掺杂密度(dopingdensity)，使得可以维持相对较高的击穿电压。例如，因为衬底表面上可能具有强电流，第一n型阱121的掺杂密度可以大于第二n型阱122的掺杂密度，从而能够提高性能。此外，p型离子注入区域140的掺杂密度可以大于p型衬底110的掺杂密度，从而使得耗尽能够主动(actively)产生。
在第一实例的LDMOS器件中，如图2所示，可以在栅极160和漏极170之间交替地形成器件隔离(isolation)层150和第一n型阱121。例如，隔离层150和第一n型阱121的取向(orientation)通常可以垂直于栅极160的取向。
LDMOS器件的第二实例
图4为LDMOS器件的第二实例的部分侧视图。第二实例的LDMOS器件可以包括在p型衬底110上形成的n型阱122，在所述n型阱122上形成p型阱142，在所述p型阱142中形成的多个隔离层150，以及在所述p型阱142和所述隔离层150上选择性形成的栅极160。
第二实例的LDMOS器件可以采用第一实例的LDMOS器件的技术特征。然而，第二实例的LDMOS器件与第一实例的LDMOS器件的不同之处在于，形成第二实例的LDMOS器件的p型阱142以代替第一实例的LDMOS器件的第一n型阱122。因此，衬底表面变成p型以便阻止电子流到衬底表面，并且阻止电子陷入隔离层中。
在第二实例的LDMOS器件中，将耗尽从p型衬底110和p型阱142转送到n型阱122，从而可以确保(secure)该耗尽。
此外，在第二实例的LDMOS器件中，在隔离层150和p型阱142之间进一步形成围绕隔离层150的p型离子注入区域140，从而可以阻止隔离层150和第二n型阱122直接接触并快速实现耗尽。
尽管示出并且描述了本发明的示例性实施例，但是可以在这些实施例中做出改变。因此本发明的保护范围由随附的权利要求的保护范围及其等同保护范围确定。

Claims (13)

1.一种横向双扩散金属氧化物半导体器件，包括：
第一n型阱，其形成在p型衬底上；
多个隔离层，其形成在所述第一n型阱中；
p型离子注入区域，其形成在所述多个隔离层的每一个的表面上；以及
栅极，其选择性地形成在所述第一n型阱和所述多个隔离层上。
2.如权利要求1所述的横向双扩散金属氧化物半导体器件，进一步包括第二n型阱，其形成在所述第一n型阱和所述p型衬底之间。
3.如权利要求2所述的横向双扩散金属氧化物半导体器件，其中所述第一n型阱的掺杂密度大于所述第二n型阱的掺杂密度。
4.如权利要求1所述的横向双扩散金属氧化物半导体器件，其中所述p型离子注入区域围绕所述多个隔离层。
5.如权利要求1所述的横向双扩散金属氧化物半导体器件，其中所述p型离子注入区域形成在所述第一n型阱和所述多个隔离层之间。
6.如权利要求1的横向双扩散金属氧化物半导体器件，其中在所述栅极和漏极之间交替形成所述多个隔离层和所述第一n型阱。
7.如权利要求6所述的横向双扩散金属氧化物半导体器件，其中所述多个隔离层和所述第一n型阱的取向垂直于所述栅极的取向。
8.如权利要求1所述的横向双扩散金属氧化物半导体器件，其中所述p型离子注入区域的掺杂密度大于所述p型衬底的掺杂密度。
9.一种横向双扩散金属氧化物半导体器件，包括：
n型阱，其形成在p型衬底上；
p型阱，其形成在所述n型阱上；
多个隔离层，其形成在所述p型阱中；以及
栅极，其选择性地形成在所述p型阱和所述多个隔离层上。
10.如权利要求9所述的横向双扩散金属氧化物半导体器件，进一步包括p型离子注入区域，其形成在所述多个隔离层的每一个的表面上。
11.如权利要求10所述的横向双扩散金属氧化物半导体器件，其中所述p型离子注入区域围绕所述多个隔离层。
12.如权利要求10所述的横向双扩散金属氧化物半导体器件，其中所述p型离子注入区域形成在所述p型阱和所述多个隔离层之间。
13.如权利要求9所述的横向双扩散金属氧化物半导体器件，其中在所述栅极和漏极之间交替形成所述多个隔离层和所述p型阱。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569392A (zh) * 2010-12-27 2012-07-11 中芯国际集成电路制造(北京)有限公司 Ldmos晶体管、布局方法和制作方法
CN102130162B (zh) * 2010-01-18 2012-11-07 上海华虹Nec电子有限公司 Ldmos及其制造方法
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CN109473476A (zh) * 2017-09-07 2019-03-15 无锡华润上华科技有限公司 一种横向双扩散金属氧化物半导体器件及其制作方法

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CN102130162B (zh) * 2010-01-18 2012-11-07 上海华虹Nec电子有限公司 Ldmos及其制造方法
CN102569392A (zh) * 2010-12-27 2012-07-11 中芯国际集成电路制造(北京)有限公司 Ldmos晶体管、布局方法和制作方法
CN102569392B (zh) * 2010-12-27 2014-07-02 中芯国际集成电路制造(北京)有限公司 Ldmos晶体管、布局方法和制作方法
CN104112774A (zh) * 2014-01-14 2014-10-22 西安后羿半导体科技有限公司 一种横向双扩散金属氧化物半导体场效应管
CN109473476A (zh) * 2017-09-07 2019-03-15 无锡华润上华科技有限公司 一种横向双扩散金属氧化物半导体器件及其制作方法
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