CN101339931A - 具铜线的半导体封装件及其打线方法 - Google Patents

具铜线的半导体封装件及其打线方法 Download PDF

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Publication number
CN101339931A
CN101339931A CNA2007101282166A CN200710128216A CN101339931A CN 101339931 A CN101339931 A CN 101339931A CN A2007101282166 A CNA2007101282166 A CN A2007101282166A CN 200710128216 A CN200710128216 A CN 200710128216A CN 101339931 A CN101339931 A CN 101339931A
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China
Prior art keywords
chip
copper cash
bearing part
semiconductor package
soldered
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CNA2007101282166A
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English (en)
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蔡汉龙
黄致明
萧承旭
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Priority to CNA2007101282166A priority Critical patent/CN101339931A/zh
Publication of CN101339931A publication Critical patent/CN101339931A/zh
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Abstract

一种具铜线的半导体封装件及其打线方法，半导体封装件包括：具有多个焊结点的承载件，以及接置于承载件上的芯片，且于芯片上形成有多个焊垫，复于承载件的焊结点上植设凸块，并且利用多条铜线，用以分别端接承载件上的凸块及芯片上的焊垫，从而通过铜线电性连接芯片与承载件，接着，于承载件上形成封装胶体，以包覆芯片、铜线及凸块。从而可通过植设于承载件焊结点上的凸块，改善铜线于承载件焊结点上的焊着性而解决缝点脱落的问题；因焊接端具有良好的共晶，故焊接后残留在焊嘴上的铜线，具平整的线尾端面及均一的线尾长度，而于下阶段烧球时可得大小均一的焊球，因此无需另于芯片的焊垫上植设凸块，即可与芯片的焊垫形成良好的共晶关系。

Description

具铜线的半导体封装件及其打线方法
技术领域
本发明涉及一种具铜线的半导体封装件及其打线方法，特别是涉及一种以铜线电性连接承载件及接置于该承载件上的芯片的半导体封装件及用于该半导体封装件的打线方法。
背景技术
现有的半导体封装件，通常是使用金线(Au wire)将芯片电性连接至如导线架或基板的芯片承载件，这是因为金线与导线架焊结点(Finger)上的镀银层或基板焊结点上的镀镍/金(Ni/Au)层可产生良好的共晶，而确保金线与相对焊结点的焊接品质；但金质材料的焊线有价格昂贵的缺点，因此在焊线材料使用上，遂有以铜(Cu)质材料取代金(Au)质材料的趋势，但铜线(Cu wire)与导线架焊结点上的镀银层或基板焊结点上的镀镍/金(Ni/Au)层间并无法产生良好的共晶，遂会使铜线焊接至焊结点的缝接端(stitch end)发生短尾(short tail)现象，而造成焊接后残留在焊嘴外的铜线的线尾端(Tail end)不平整及其线尾长度不一的问题，致而影响到进行次一打线(wire bonding)前铜线的线尾端经烧球成型的焊球(Free Air Ball，FAB)，使所成型的焊球的大小无法均一。当焊球的大小无法均一时，即易造成焊球与芯片上的焊垫(Bond pad)焊接的共晶性不良而产生焊球脱落(ball lift)的问题。
换言之，如图3A所示，传统的金线(Au wire)30的缝接端300与基板31的焊结点310上的镀镍/金(Ni/Au)层可产生良好的共晶，故金线30与焊结点310间不致发生缝点脱落(stitch lift)的问题，且于打线完成后，该缝接端300亦不会产生短尾现象，使残留在焊嘴M上的金线30具有平整的线尾端301，而令线尾端301具有均一线尾长度h，故于进行后续的打线作业前的烧球时，均能成型出大小较为均一的焊球302，而能确保金线与焊结点间的焊接品质。而在使用铜线时，如第3B图所示，由于铜线30’与基板31’的焊结点310’上的镀镍/金(Ni/Au)层间不具良好的共晶性，铜线30’的缝接端300’于焊接至该焊结点310’后，该缝接端300’易形成短尾现象，而造成焊接后残留在焊嘴M’外的铜线30’的线尾端301’会产生不平整的状况及线尾长度h’不一的问题，遂使进行后续打线作业前的烧球时，产生的焊球302’的大小无法均一，而易造成焊接至芯片33’的焊垫330’上的焊球302’脱落(ball lift)。
为了解决上述问题，如图4所示，美国专利公开第20040072396号揭示于芯片42的焊垫421上植设一金质凸块43(Au Stud Bump)，以供铜线40的焊球402得以焊接于金质凸块43上，由于该两者能产生良好的共晶，故得提升铜线40与焊垫421的焊结信赖性，有效改善焊球402脱落(ball lift)问题。但是，如前所述，铜线40与导线架或基板41的焊结点411上的镀银层或镀镍/金(Ni/Au)层，仍无法产生良好的共晶，故铜线的缝接端400焊接至焊结点411上后仍存在有缝接点脱落(stitch lift)问题或短尾现象，亦会影响到后续焊球形成的尺寸均一性(已详述于前，故不另赘言)。
因此，如何提出一种半导体封装件及其打线方法，以解决铜线于芯片的焊垫上的焊球脱落(ball lift)问题，及于导线架或基板上焊结点的缝点脱落(stitch lift)问题，提升铜线的焊结信赖性，确为此相关领域所迫切待解的问题。
发明内容
本发明的一目的在于提供一种具铜线的半导体封装件及其打线方法，由植设与承载件的焊结点共晶良好的金质凸块，提升铜线于焊结点的焊着性(bondability)，藉以解决焊结点的缝点脱落(stitch lift)的问题。
本发明的另一目的在于提供一种具铜线的半导体封装件及其打线方法，由植设与承载件的焊结点共晶良好的金质凸块，藉以解决铜线于芯片的焊垫的焊球脱落(ball lift)的问题。
本发明的又一目的在于提供一种具铜线的半导体封装件及其打线方法，由植设与承载件的焊结点共晶良好的金质凸块，使焊接后残留在焊嘴外的铜线，具平整的线尾端，及均一的线尾长度，从而于进行次一打线前铜线的线尾端经烧球成型的焊球得大小均一，而毋需再于芯片的焊垫上植设金质凸块，铜线即可与芯片的焊垫形成良好的共晶。
为达到前述及其它目的，本发明所提供的具铜线的半导体封装件，包括具有多个焊结点的承载件，该承载件可为导线架或基板；植设于该承载件的焊结点上的凸块(Stud Bump)，该凸块的材料为包含金(Au)的材料；接置于该承载件上的芯片，于该芯片的作用表面上具有多个焊垫；多条铜线，使各该铜线的两端部分别焊接至芯片上的焊垫与承载件上的凸块，从而通过该铜线电性连接该芯片与承载件；以及形成于该承载件上以包覆该芯片、铜线及凸块的封装胶体。
本发明还提供一种用于前述半导体封装件的打线方法，其步骤系包括：提供承载有芯片的承载件，而该承载件可为导线架或基板，且该承载件上具有多个焊结点，而于该多个焊结点上植设凸块，以及分别将多条铜线的一端部焊接至一接置于该承载件上的一芯片上所形成的多个焊垫，再将铜线的另一端部焊接至该焊结点上的凸块，以通过该铜线将芯片电性连接至承载件。
因此，本发明所揭示的具铜线的半导体封装件及其打线方法，乃通过植设于承载件的焊结点上金质凸块与铜线形成良好的共晶，而提升铜线于焊结点的焊着性(bondability)，从而解决铜线于承载件的焊结点上的缝点脱落(stitch lift)问题，且焊接后残留在焊嘴外的铜线的线尾(tail)具平整的线尾端及均一的线尾长度，进行次一打线前铜线的线尾端经烧球成型的焊球得大小均一，因此毋需再于芯片的焊垫上植设金质凸块，亦可一并解决因焊球的大小无法均一，而造成焊球自芯片的焊垫上脱落(ball lift)的问题，故可显著提升铜线的焊结信赖性。
附图说明
图1是本发明所提供的半导体封装件的剖视图；
图2A及图2B是本发明的打线方法的流程示意图；
图3A是现有的使用金线(Au wire)的半导体封装件的剖视图；
图3B是现有的使用铜线(Cu wire)的半导体封装件的剖视图；
图4是美国专利公开第20040072396号的半导体封装件的剖视图；元件符号说明
1    半导体封装件  11  承载件
111  焊结点        12   芯片
121  焊垫          13   凸块
14   铜线          141  焊球
142  缝接端        143  线尾端
15   封装胶体      30   金线
300  缝接端        301  线尾端
302  焊球          31   承载件
310  焊结点        30’ 铜线
300’缝接端        301’线尾端
302’焊球          31’ 承载件
310’焊结点        33’ 芯片
330’焊垫          40   铜线
400  缝接端        402  焊球
41   承载件        411  焊结点
42   芯片          421  焊垫
43   凸块
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点与功效。本发明亦可通过其它不同的具体实施例加以施行或应用，本说明书中的各项细节亦可基于不同观点与应用，在不背离本发明的精神下进行各种修饰与变更。
以下的实施例是进一步详细说明本发明的特征及功效，但并非用以限制本发明的可实施范畴。
本发明所提供的具铜线的半导体封装件，示于图1。如图所示，该半导体封装件，包括基板11、接置于该基板11上的芯片12、植设于该基板11上的金质凸块(Au Stud Bump)13、多条用以电性连接该基板11与芯片12的铜线14，以及形成于该基板11上以包覆该芯片12、金质凸块13与铜线14的封装胶体15。
该基板11上形成有多个焊结点111，以让金质凸块13焊设于该焊结点111上，从而供各该铜线14的一端部142以缝接焊接的方式与金质凸块13焊接。该基板11为公知的环氧树脂基板、聚亚酰胺基板、玻璃基板或陶瓷基板，故该焊结点111的形成在此不予赘述。同时，作为芯片12的承载件者并不限于本实施例所使用的基板11，亦可使用导线架承载芯片12。
该芯片12上形成有多个焊垫121，供各该铜线14的另一端部所烧球成型的焊球141焊接其上，从而在该铜线14分别端接至该基板11的焊结点111及芯片12的焊垫121后，芯片12能通过该铜线14而与基板电性连接。
由于形成该封装胶体15的模压作业(Molding Process)及芯片12与基板11的黏接作业(Die Bond)均为现有技术，故在此不另为文赘述。
该半导体封装件1的功效将于本发明的打线方法中予以详述。
如图2A至图2B所示，本发明的打线方法能应用于以批次(Batch)或单数(Piece by Piece)方式形成半导体封装件的制程中。
如图2A所示，该方法是先于形成于基板11上的多个焊结点111上植设多个金质凸块13，然后，如图2B所示，以打线机将一铜线14的端部烧球成型为焊球(Free Air Ball，FAB)141，再将焊球141以超声波热压或超声波接合的方式焊接至该芯片12上的焊垫121，接着，将打线机(未图示)的焊嘴M上移一预定高度后，下引焊嘴M朝基板11的焊结点111移动，以形成铜线14的线弧(Wire Loop)；该焊嘴M移至焊结点111处时，即下压该焊嘴M以将铜线14缝点焊接至该焊结点111上的金质凸块13，从而使该铜线14形成与金质凸块13良好共晶且呈半月型的缝接端142，而完成铜线14与芯片12的焊垫121及基板11的焊结点111的焊接。
由于该焊结点111上的金质凸块13能与铜线14的缝接端142良好地共晶，故该缝接端142不会发生短尾现象，也不致产生因短尾现象而导致缝接端142自金质凸块13上脱落的问题；且因铜线14于缝点焊接后，不会有短尾现象的发生，令外露出该焊嘴M的线尾端143不致产生不平整或长度不均的问题，而使进行次一打线作业时所烧球成型出的焊球141的大小能均一；由于该焊球141的形成均能大小均一，故在焊接至芯片12上的另一焊垫121后，不致产生焊球脱落(BallLift)的状况。因而，本发明的具铜线的半导体封装件及其打线方法，能显著提升铜线与芯片及芯片承载件间的焊着性，进而确保半导体封装件的信赖性。
上述实施例仅为例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修饰与变化。因此，本发明的权利保护范围，应以权利要求书的范围为依据。

Claims (10)

1.一种具铜线的半导体封装件，包括：
具有多个焊结点的承载件；
接置于该承载件上，且形成有多个焊垫的芯片；
多个植设于该承载件的焊结点上的凸块；
多条铜线，用以分别端接该承载件上的凸块及芯片上的焊垫，从而通过该铜线电性连接该芯片与承载件；以及
形成于该承载件上的封装胶体，以包覆该芯片、铜线及凸块。
2.根据权利要求1所述的具铜线的半导体封装件，其中，该凸块是以金为材料而制成的。
3.根据权利要求1所述的具铜线的半导体封装件，其中，该铜线的一端部是形成焊球以焊接至该芯片上的焊垫，而另一端部则以缝接焊接的方式焊接至该承载件上的凸块。
4.根据权利要求1所述的具铜线的半导体封装件，其中，该承载件为导线架。
5.根据权利要求1所述的具铜线的半导体封装件，其中，该承载件为基板。
6.一种用于具铜线的半导体封装件的打线方法，包括下列步骤：
于形成在一承载件上的多个焊结点上方植设多个凸块；以及
将多条铜线的一端焊接至一接置于该承载件上的芯片所具有的多个焊垫，而另一端则焊接至该承载件上的凸块，从而通过该多条铜线电性连接该芯片与承载件。
7.根据权利要求6所述的打线方法，其中，该凸块是以金为材料而制成的。
8.根据权利要求6所述的打线方法，其中，该铜线的一端部是形成焊球以焊接至该芯片上的焊垫，而另一端部则以缝接焊接的方式焊接至该承载件上的凸块。
9.根据权利要求6所述的打线方法，其中，该承载件为导线架。
10.根据权利要求6所述的打线方法，其中，该承载件为基板。
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CN104752383B (zh) * 2015-04-15 2017-08-08 苏州聚达晟芯微电子有限公司 一种新型半导体防脱落封装结构
CN115763449A (zh) * 2022-11-21 2023-03-07 中山芯承半导体有限公司 一种具有不同厚度小芯片的封装结构及其制造方法

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