CN101339907A - 在衬底上安装电子元件的方法以及电子衬底 - Google Patents
在衬底上安装电子元件的方法以及电子衬底 Download PDFInfo
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Abstract
一种在衬底上安装电子元件的方法,包括在衬底表面中形成至少一个沟槽。在衬底中形成的沟槽减小衬底的刚度,这提供对于剪切的较小阻抗。因此,沟槽减小将电子元件安装到衬底的焊点上的应变量,这增加焊点的寿命。
Description
技术领域
本发明一般地涉及一种在电子(有机)衬底上表面安装电容器的方法和装置,尤其涉及一种减小表面安装的元件中应变的方法和装置。
背景技术
电子元件例如电容器典型地安装在衬底上。例如,如图1A中所示,芯片102安装在衬底104的表面上。多个电容器106或者其他分立电子器件安装在衬底104的表面上,围绕芯片102。
图1B说明图1A中描绘的电子组件100的详细描述。
典型地,衬底104通过首先形成核心108而形成。衬底104的整个厚度可能典型地大约为1mm厚。接下来,构造层110形成在核心108的顶面和底面的每个上。构造层典型地包括聚合物和铜层。
焊料掩模112然后形成在衬底104的表面上。焊料掩模112覆盖衬底,除了期望制造焊料连接的区域之外。
芯片(例如硅芯片)102通过焊点114安装到衬底104。类似地,电容器106,或者其他表面安装元件,通过焊点116和焊垫118安装到衬底。
[下面的问题已经由发明者发现或者常规器件的这些问题先前已知吗?]
但是,根据上面的描述,安装在衬底上的电容器可能遭受显著的热机械应变。温度循环在电容器的陶瓷片中产生焊点疲劳或裂纹。
电子组件经历热循环以评估电子焊点的坚固性。图2说明在热循环期间表面安装的元件上的应变源。
首先,剪切应力208在将电容器204安装到衬底206的焊点202中引起。焊点202上的剪切应力由电容器204与衬底206的热膨胀系数的不匹配而引起。典型地,电容器204的热膨胀系数可能大约为3ppm,而衬底206的热膨胀系数可能大约为20ppm。
图3说明焊点202、电容器204和衬底206上的应力208的程度。应力也可能产生衬底206中的裂纹。
图4说明热循环期间在焊点上引起的两种类型的应变。冯迈斯(Von Mises)应力和剪切应变在焊点上引起。
返回到图2,热膨胀系数的不匹配也使得衬底206弯曲。衬底206的弯曲在焊点202上产生拉伸/压缩应力210。另外,虽然弯曲可能减小焊点202上的剪切应力208,但是这将引起置于电容器204上的应力的增加。
此外,焊点202具有可能与电容器204和/或衬底206的热膨胀系数不同的热膨胀系数。热膨胀系数的该不匹配在焊点202上引起限于局部的复杂应力状态212。
另外,焊点区域的应力渗透过电子元件的主体,这可以产生可能导致功能故障的裂纹。
因此,在本发明之前,还不存在将电子元件例如电容器表面安装到衬底上,同时减小焊点、电容器和衬底上应力的作用的方法。
发明内容
考虑到常规方法和结构的前述和其他实例问题、缺点和劣势,本发明的实例特征在于提供一种表面安装的电子元件中应变减小的方法和结构。
根据本发明的第一方面,一种在衬底上安装电子元件的方法包括在衬底表面中形成至少一个沟槽。
根据本发明的第二方面,一种电子组件包括衬底,其具有在衬底表面中形成的至少一个沟槽。
根据本发明的第三方面,一种电子衬底包括位于电子衬底表面中的至少一个沟槽。
在电子衬底的表面中形成沟槽减小电容器(或任何其他电子元件)周围的衬底的刚度,使得衬底具有对于剪切的较少阻抗。因此,将电子元件安装到衬底上的焊点上的应变减小,这增加焊点的寿命。
附图说明
前述和其他实例目的、方面和优点将从下面参考附图的本发明实例实施方案的详细描述中更好地理解,其中:
图1A和1B说明包括根据常规安装技术安装的表面安装电容器106的电子组件100;
图2说明在常规表面安装的电容器204的焊点202中引起的典型应力;
图3进一步说明在常规表面安装的电容器上引起的应力;
图4进一步说明在常规表面安装的电容器上引起的应力;
图5说明根据本发明实例实施方案的实例具有沟槽的衬底502;
图6说明根据本发明实例实施方案的第一沟槽设计;
图7说明图6中描绘的沟槽设计的三维视图;
图8用曲线图描绘由本发明的具有沟槽的衬底引起的应力减小,显示MTLIC左上引脚,分别表示:冯迈斯平均应力;RMS XZ剪切应力;RMS YZ剪切应力;
图9说明根据本发明实例实施方案的第二沟槽设计;以及
图10说明根据本发明实例实施方案的第三沟槽设计。
具体实施方式
现在参考附图,尤其参考图5-10,显示根据本发明的方法和结构的实例实施方案。
图5说明根据本发明实例实施方案的实例电子组件500。电子组件包括衬底502,其具有安装在衬底502表面上的电子元件(例如电容器)506。电容器506通过焊点(例如焊接点)504安装在衬底502上。
根据本发明的某些实例方面,至少一个沟槽508在衬底502的表面中形成。通过在衬底502的表面中形成沟槽508,衬底502的刚度减小。减小衬底502的刚度将减小衬底502对于剪切力的阻抗。因此,在衬底502和焊点504上引起的应力减小。因此,焊点504的寿命增加。
图6说明根据本发明实例实施方案的沟槽设计。图7说明图6中所示电子组件的三维视图。
如图6中所示,电子组件600包括安装在衬底602上的电子元件(电容器)608。电容器608通过多个电容器引脚(leg)(焊垫/焊点)606安装到衬底602。
根据图6中描绘的实例实施方案,电容器608由两行焊垫606安装到衬底602。连续沟槽604形成在每行焊垫606周围。各个沟槽每个大约为15μm深且大约200μm宽。
图8是描绘使用图6和7中说明的沟槽设计实现的应力减小的曲线图。如图8中所示,图6和7中描绘的沟槽设计提供18%的减小应力。
图9说明根据本发明某些实例实施方案的备选沟槽设计。图9中描绘的沟槽设计也包括在每行焊点904周围形成的连续沟槽902。另外,沟槽902包括在每个焊点904之间形成的沟槽延伸缝隙(slit)906。沟槽延伸缝隙906进一步减小衬底的刚度,从而进一步减小焊点904上的应力。
图10说明本发明的另一种备选实施方案。与上述实施方案类似,电子组件1000包括由多个电容器引脚1006安装到衬底1002的电容器1004。根据本实施方案,各个沟槽1008形成在各个电容器引脚1006的每个周围。沟槽1008具有与电容器引脚类似的形状。在图10中说明的实施方案中,沟槽具有圆形形状。
虽然已经根据几种实例实施方案描述了本发明,但是本领域技术人员将认识到,可以使用附加权利要求的本质和范围内的修改来实践本发明。
此外,应当注意,申请者的意图在于包括所有权利要求要素的等价物,即使随后在实行期间修正。
Claims (20)
1.一种在衬底上安装电子元件的方法,包括:
形成减小通过衬底的应力流的至少一个结构。
2.根据权利要求1的方法,其中所述结构包括位于衬底表面中的至少一个沟槽。
3.根据权利要求2的方法,其中所述至少一个沟槽形成在多个电容器引脚周围,所述电容器引脚将电子元件安装到衬底。
4.根据权利要求2的方法,其中所述至少一个沟槽包括:
形成在第一行电容器引脚周围的第一沟槽;以及
形成在第二行电容器引脚周围的第二沟槽。
5.根据权利要求3的方法,还包括形成多个沟槽延伸缝隙,所述沟槽延伸缝隙从所述沟槽的每个延伸并且在所述第一行电容器引脚和所述第二行电容器引脚的多个电容器引脚之间延伸。
6.根据权利要求3的方法,其中所述至少一个沟槽包括连续沟槽。
7.根据权利要求1的方法,还包括在所述衬底的所述表面中形成多个沟槽。
8.根据权利要求7的方法,其中所述多个沟槽包括在多个电容器引脚周围形成的多个连续沟槽。
9.根据权利要求7的方法,其中所述多个沟槽包括多个独立沟槽,所述独立沟槽形成在多个电容器引脚周围。
10.根据权利要求2的方法,其中所述至少一个沟槽具有大约15μm或更大的深度。
11.根据权利要求2的方法,其中所述至少一个沟槽具有大约200μm的宽度。
12.一种电子衬底,包括:
位于电子衬底的表面中的至少一个沟槽。
13.根据权利要求12的电子衬底,其中所述至少一个沟槽形成在多个电容器引脚周围,所述电容器引脚将电子元件安装到衬底。
14.根据权利要求12的电子衬底,其中所述至少一个沟槽包括:
形成在第一行电容器引脚周围的第一沟槽;以及
形成在第二行电容器引脚周围的第二沟槽。
15.根据权利要求13的电子衬底,还包括多个沟槽延伸缝隙,所述沟槽延伸缝隙从所述沟槽的每个延伸并且在所述第一行电容器引脚和所述第二行电容器引脚的多个电容器引脚之间延伸。
16.根据权利要求13的电子衬底,其中所述至少一个沟槽包括连续沟槽。
17.根据权利要求12的电子衬底,还包括位于所述衬底的所述表面中的多个沟槽。
18.根据权利要求17的电子衬底,其中所述多个沟槽包括在多个电容器引脚周围形成的多个连续沟槽。
19.根据权利要求17的电子衬底,其中所述多个沟槽包括多个独立沟槽,所述独立沟槽形成在多个电容器引脚周围。
20.一种电子组件,包括:
衬底,该衬底其具有在衬底表面中形成的至少一个沟槽。
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US11/679,407 US20080205023A1 (en) | 2007-02-27 | 2007-02-27 | Electronic components on trenched substrates and method of forming same |
US11/679,407 | 2007-02-27 |
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2007
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2008
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- 2008-02-13 US US12/030,260 patent/US8054630B2/en active Active
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Cited By (2)
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CN103227154A (zh) * | 2012-01-27 | 2013-07-31 | 英飞凌科技股份有限公司 | 具有压印底板的功率半导体模块及其制造方法 |
CN103227154B (zh) * | 2012-01-27 | 2017-05-03 | 英飞凌科技股份有限公司 | 具有压印底板的功率半导体模块及其制造方法 |
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US7777301B2 (en) | 2010-08-17 |
US8659119B2 (en) | 2014-02-25 |
US7855430B2 (en) | 2010-12-21 |
US20080205024A1 (en) | 2008-08-28 |
US20140151849A1 (en) | 2014-06-05 |
US20080218990A1 (en) | 2008-09-11 |
US20100276784A1 (en) | 2010-11-04 |
US7732894B2 (en) | 2010-06-08 |
US20080226875A1 (en) | 2008-09-18 |
US20090085161A1 (en) | 2009-04-02 |
US20080205023A1 (en) | 2008-08-28 |
US9508789B2 (en) | 2016-11-29 |
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