CN101317266B - 具有适应的转接触点的无凸起的倒装芯片组件 - Google Patents

具有适应的转接触点的无凸起的倒装芯片组件 Download PDF

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CN101317266B
CN101317266B CN2006800443855A CN200680044385A CN101317266B CN 101317266 B CN101317266 B CN 101317266B CN 2006800443855 A CN2006800443855 A CN 2006800443855A CN 200680044385 A CN200680044385 A CN 200680044385A CN 101317266 B CN101317266 B CN 101317266B
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integrated circuit
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韦恩·纳恩
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Abstract

根据示例实施例,集成电路器件(IC)被装配在封装基板上并且被封装在模塑材料中。半导体裸片具有带接触焊盘的电路图案。具有与电路图案的接触焊盘相对应的凸起焊盘连接端的封装基板具有夹在其中的转接层。转接层包括嵌入在弹性材料中的球形颗粒的随机分布相互分离的导电柱,其中转接层受到来自施加在半导体裸片的下表面上的压力的压缩力。压缩力使得转接层变形,使得球形颗粒的导电柱电连接到接触焊盘,该接触焊盘具有对应于封装基板的凸起焊盘连接端的电路图案。可以由模塑材料、封装基板、金属夹具及其组合的热膨胀特性所生成的力来获得压缩力。

Description

具有适应的转接触点的无凸起的倒装芯片组件
技术领域
本发明涉及集成电路(IC)封装。本发明尤其涉及在除去了凸起形成工艺的倒装芯片结构中组装IC器件。
背景技术
电子行业持续不断依托半导体技术的进步而在更紧凑的面积上实现更高性能的器件。对于很多应用来说,实现更高性能的器件需要把大量电子器件集成到单一硅晶片。随着单位给定面积的硅晶片上电子器件数目的增加,制造工艺变得更加困难。
已经生产出很多在各个学科中具有多种应用的半导体器件。这种硅基半导体器件通常包括金属氧化物半导体场效应晶体管(MOSFET),诸如p沟道MOS(PMOS)、n沟道MOS(NMOS)和互补型MOS(CMOS)晶体管、双极性晶体管、和BiCMOS晶体管。这种MOSFET器件包括导电栅极和类硅基板之间的绝缘材料,因此,这些器件通常被称为IGFET(绝缘栅极FET)。
这些半导体器件的每一个通常包括其上形成有多个有源器件的半导体基板。给定的有源器件的特定结构可以随器件类型变化。例如,在MOS晶体管中,有源器件通常包括源极区域和漏极区域以及调制源极区域和漏极区域之间的电流的栅电极。
另外,这种器件可以是以多种晶片制造工艺(例如,CMOS、BiMOS、双极性等)制造的数字或模拟器件。基板可以是硅、砷化镓(GaAs)或者适合在其上构建微电子电路的其他基板。
在经过制造工艺之后,硅晶片具有预定数目的器件。这些器件被加以测试。合格的器件被收集并封装起来。
复杂IC器件的封装在其最终性能方面的作用逐渐增大。通过消除使用接合线及其增加的重量,倒装芯片组件提供了封装外形的减小。而且,倒装芯片提供了牢固的高性能电连接,然而,倒装芯片凸起形成工艺增加了封装的复杂度,这是因为凸起焊盘必须被附接到IC器件的接合焊盘连接端从而使得IC器件可以被附接到封装基板。
需要减小倒装芯片IC器件的封装中的复杂度并且仍然保持硅裸片和基板互连之间的高性能电连接。
发明内容
本发明在实现硅裸片的接合焊盘与基板上的连接焊盘之间的高性能电连接方面是很有益的。通过消除凸起形成工艺,可以实现批量组件、可靠性、制造基础结构以及显著减小的封装成本。高性能、可商购的夹在IC裸片与封装基板之间的转接结构受到压缩力的作用。贯穿转接结构排列的(彼此分离的)球型线列在受到压缩时形成了在IC裸片的接合焊盘与封装基板之间的电连接。转接结构在从狭窄间距的接合焊盘到具有较宽间距的基板连接焊盘的信号走线的重新选择中起到再分布层的作用。
在示例实施例中,集成电路器件(IC)装配在封装基板上并且封装在模塑材料中。IC器件包括具有上表面和底面的半导体裸片,上表面具有电路图案,该电路图案包括预定排列的接触点。封装基板具有一定的长度和宽度,具有凸起焊盘连接端(bump pad landing)。凸起焊盘连接端在与电路图案的接触点的预定排列相对应的排列中,凸起焊盘连接端具有把焊盘连接端耦接到封装基板中的外部接触区域的连接走线。转接层夹在半导体裸片与封装基板之间,包括嵌入在弹性材料中的球形颗粒的随机分布的彼此分离的导电柱。转接层受到来自施加在半导体裸片的底面上的压力的压缩力的作用,该压缩力使得转接层变形,使得球形颗粒的导电柱电连接到电路图案的接触点,电路图案具有封装基板的对应凸起焊盘连接端。
在另一实施例中,集成电路器件(IC)被装配在封装基板上。IC器件包括具有上表面和底面的半导体裸片,上表面具有电路图案,该电路图案包括预定排列的接触点。封装基板具有一定的长度和宽度,具有凸起焊盘连接端。凸起焊盘连接端在与电路图案的接触点的预定排列相对应的排列中,凸起焊盘连接端具有把焊盘连接端耦接到封装基板中的外部接触区域的连接走线。转接层夹在半导体裸片与封装基板之间,包括嵌入在弹性材料中的球形颗粒的随机分布的彼此分离的导电柱。转接层受到来自施加在半导体裸片的底面上的压力的金属夹具的压缩力的作用,该压缩力使得转接层变形,使得球形颗粒的导电柱电连接到电路图案的接触点,该电路图案具有封装基板的对应凸起焊盘连接端。模塑材料的钝化封壳将半导体裸片和转接结构封装起来。
在又一实施例中,介绍了一种封装IC器件的方法,该IC器件具有电路图案,该电路图案在封装基板上沿倒装芯片朝向上包括I/O接触点,该封装基板具有与电路图案的I/O接触焊盘相对应的焊盘连接端。该方法包括选择适合IC器件的I/O焊盘布局的封装基板。转接结构被应用在封装基板上,具有嵌入在弹性材料中的球形颗粒的随机分布的彼此分离的导电柱。IC器件沿倒装芯片朝向被布置在转接结构上。在IC器件上施加压缩力。该压缩力使得转接层变形,使得球形颗粒的导电柱电连接到电路图案的接触点,该电路图案具有封装基板的对应凸起焊盘连接端。将压缩力保持在IC器件上,并且将IC器件封装在钝化封壳中。本发明的以上综述并非意在描绘本发明的每个公开的实施例或者每个方面。在附图以及随后的详细说明中提供了其他方面和示例实施例。
附图说明
结合附图考虑本发明各个实施例的以下详细描述,可以更全面的理解本发明:其中
图1A是转接结构的侧视图和俯视图;
图1B-1D是受到几个力能级变形的转接结构的侧视图,该转接结构把IC器件接触焊盘电连接到电路板基板上对应的焊盘连接端,其中
图1B是较小力度变形的转接结构的侧视图;
图1C是中等力度变形的转接结构的侧视图;
图1D是较大力度变形的转接结构的侧视图;
图2示出了针对两个示例基板材料的Z方向膨胀率与温度的曲线;
图3是IC器件的侧视图,使用高玻璃化转变温度(Tg)模塑材料的压力,利用转接结构把该IC器件电耦接到封装基板,在该结构与根据本发明实施例的转接结构之间产生较高的CTE失配;
图4是IC器件的侧视图,使用通过根据本发明实施例的金属夹具施加在IC器件上的压力,利用转接结构把该IC器件电耦接至封装基板;
图5A是IC器件的侧视图,使用通过图4的金属夹具施加在IC器件上的压力把该IC器件电耦接至封装基板,使该金属夹具变型,以在封装的IC器件上提供了附加的预应力压力;
图5B是图5A的IC器件的俯视图;
图6A是IC器件的侧视图,使用通过根据本发明实施例的金属夹具/保持头在IC器件上施加的力,利用转接结构把该IC器件电耦接至封装基板;
图6B是图6A中所示的封装的俯视图;以及
图7是实现本发明的工艺的流程图。
具体实施方式
尽管本发明可以修改成各种变型和替代形式,但是已经通过附图中的示例方式示出并详细描述了其细节。然而,应该理解的是,并非意在把本发明限定于所述的特定实施例。相反,意在覆盖落入如所附权利要求所限定的本发明的精神和范围内的全部变型、等同和替代。
实验证明,本发明在通过在IC器件上的输入/输出焊盘的信号走线的重新选择中形成有弹性的转接结构的再分布层,来向封装基板上的凸起图案提供接触接口方面是有用的。IC器件的输入/输出焊盘与封装基板的对应凸起图案之间的连接是以转接来实现的,该转接具有球形颗粒的随机分布相互分离的导电柱(例如,导电球体)的阵列,夹在IC器件和封装基板之间并受到压缩力的作用。施加在输入/输出焊盘和凸起处的力比施加在芯片的其他区域的力更大,被施加在较高地势的导电表面的力比施加在环绕的非导电电介质区域的力大。没有相互相对的导电表面的区域不进行电连接。在封装组件期间可以采用多种方式来得到压缩力。这种压缩力可以采用但并不限于较高的热膨胀系数(TCE)模塑材料、机械夹具或者机械预应力压具来获得。
在示例实施例中,转接结构可以与标准球栅阵列(BGA)封装形状因子及其相关装配工艺一起使用。然而,转接结构的使用并不必限于特定的封装基板类型。转接结构可以如片上系统(SIP)应用的情况一样用于印刷电路板(PCB)上的倒装芯片装配。参考图1A,以侧视图和俯视图示出了适应的弹性转接结构10。导电球形颗粒的随机分布的导电柱20分布在弹性隔膜30的周围。通过弹性隔膜30可以看到金接触焊盘40。参考图1B-1D,转接结构10被夹在封装基板50与硅裸片70之间。在向硅裸片70和封装基板50施加压缩力时,硅裸片70上的接触焊盘60和封装基板50上的凸起焊盘40通过导电球体阵列20被连接起来。图1B-1D示出了在增大的压力下转接结构10的变形。图1B示出了小于1%的变形,图1C示出而来大约10%的中间变形,而图1D示出了大约35%的较大变形。在硅裸片70与封装基板50之间的给定位移处,接触焊盘60和凸起焊盘40具有施加在其上的较大压缩力,这是由于显著地突出在硅裸片70或者封装基板50上面的特点。导电球体的随机分布的导电柱20在硅裸片70和封装基板50的绝缘区域上不进行连接。可以把封装基板50变型成包括焊接掩模(未示出)来在凸起焊盘40之间提供附加的绝缘物。BGA位置处焊接掩模的主要目的是把焊料的润湿隔离到特定区域,BGA焊盘用于将焊球附接到外部封装上。焊接掩模用来把焊盘与导体相隔离,或者与导向触点开口或者电镀孔的电路相隔离。没有焊接掩模的话,软焊料可以流到连接电路,或者流入附接的触点开口。发生焊接接缝断开和短路。对于本发明来说,焊接掩模增加了附加的绝缘物使得转接结构可以被引导入限定在凸起焊盘中的焊接掩模孔。焊接掩模的使用取决于凸起焊盘的数量及其彼此之间的距离。
在示例实施例中,在IC器件装配中,可以使用高TCE模塑材料来对转接层提供压缩力,从而在IC器件I/O焊盘与倒装芯片封装的凸起焊盘之间提供电连接。选择TCE模塑材料以使得在硅裸片和基板材料之间具有非常高的TCE失配从而提供压力机制。在图2中可以观测到材料垂直的Z方向膨胀。高Tg环氧材料的曲线110示出了从大约25℃到175℃之间大约1.0%的膨胀。这些材料在“X”和“Y”方向上理想地具有基本上较小的水平膨胀。当周围温度从大约175℃升高到300℃时,这中间存在额外的2.5%的膨胀(总共3.5%的膨胀)。玻璃化转变温度(Tg)是材料从固态成为“有弹力的”无定形状态的温度。相反,具有较低Tg的聚酰亚胺材料的曲线示出了从25℃到大约200℃只有1.0%的膨胀。从200℃到大约300℃存在额外的1.25%的膨胀(总共2.25%的膨胀)。因此,材料的垂直膨胀为转接结构提供了足够的力。
对于特定的IC器件和应用环境来说,不得不确定装配IC器件所需的适合材料。在确定好适合的材料后,设计人员进行实验来发现TCE相容材料、转接结构的最佳组合和构造,从而确保IC裸片接触焊盘与封装基板凸起焊盘之间长期可靠的电接触。这种最佳组合可以得自于实验设计(DOE)分析。
参考图3,以侧视图示出了装配在倒装芯片封装200中的IC器件。封装基板210具有置于转接结构220顶部上的硅裸片230。一个特定的转接结构是PARIPOSERTM,由Massachusetts,Fall River的Paricon Technologies Corporation制造。高Tg模塑材料240将硅裸片230、转接结构220、封装基板210具有凸起焊盘215的那部分封装起来。高TCE模塑材料240在硅裸片230、转接结构220和凸起焊盘215上施加向下的压缩力X2。具有不同TCE的封装基板210施加与压缩力X2相反的向上的力Y2。转接结构中的导电球体225提供了硅裸片230上的I/O接触焊盘235与封装基板210上的凸起焊盘215之间的电连接。焊球250提供了从装配的IC器件200到应用环境的电连接。
在特定实施例中,基板210可以使用热固塑料工业层压板,例如NEMA(国家电气制造商协会)G10级或者FR4玻璃纤维布增强环氧树脂玻璃。如果使用的话,焊接掩模材料将会具有大约180℃到大约220℃范围内的Tg。模塑材料将会具有大约200℃到260℃范围内的Tg
在示例实施例中,在IC器件装配期间,外部金属机械夹具可以放置在硅裸片、转接结构和封装基板上,并且夹持在封装基板上来提供压缩力,从而提供IC器件I/O接触焊盘与倒装芯片封装的凸起焊盘之间的电连接。参考图4,以侧视图示出了装配在倒装芯片封装300中的IC器件。封装基板310具有布置在转接结构320顶部的硅裸片330。金属夹具360夹持硅裸片330、转接结构320、封装基板310具有凸起焊盘315的那部分。金属夹具360在硅裸片330、转接结构320和凸起焊盘315上施加压缩力X3。转接结构320中的导电球体325提供了硅裸片上的I/O接触焊盘335与封装基板330上的凸起焊盘315之间的电连接。焊球350提供了从装配好的IC器件300到应用环境的电连接。模塑材料340把硅裸片330封装起来。金属夹具360位于模塑材料的外部。
参考图5A-5B,在外部机械夹具360的变型中,当夹具360a附接到封装基板310时,夹具360a具有定位槽370来给封装好的硅裸片330预加应力。在示例基板中,封装尺寸大约是35mm×35mm,图5B的U和V尺度。封装的高度大约是4.73mm,如图5A所示的H尺度。金属夹具遵循JEDEC硅封装体尺寸,例如35mm、37.5mm、40mm等。额外的信息可以见诸于JEDEC Publication 95(JEP95),题为“JEDEC Registered and Standard Outline for Solid State andRelated Products”。在另一实施例中,具有限定在该金属夹具360a中的开口380。
在示例实施例中,在IC器件装配器件,机械预应力夹具可置于硅裸片、转接结构和封装基板上。保持头把金属夹具固定在封装基板上并且给硅裸片、转接结构和封装基板提供了压缩力,从而提供了IC器件I/O接触焊盘与倒装芯片封装的凸起焊盘之间的电连接。参考图6A-6B,以侧视图示出了装配在倒装芯片封装400中的IC器件。封装基板410具有置于转接结构420顶部的硅裸片430。在硅裸片430顶部上,放置了与硅裸片具有相似TCE的材料470。被推入限定在封装基板430中的孔中的内部机械预应力金属夹具440夹持了硅裸片430、转接结构420、封装基板430具有凸起焊盘415的那部分。金属夹具440具有保持头445以提供机械安装。金属夹具440在硅裸片430、转接结构420和凸起焊盘415上施加压缩力X4。夹具被设计成在保持头445被插入、压入并穿过封装另一侧之前对裸片预加应力。在转接结构420中的导电球体425提供了硅裸片上的I/O接触焊盘435和封装基板420上的凸起焊盘之间的电连接。模塑材料460将硅裸片430、转接结构420和金属夹具440封装起来。金属夹具440中的开口480(诸如缝隙)有助于模塑材料的流动。焊球450提供了从装配好的IC器件到应用环境的电连接。
在另一示例实施例中,可以把额外的粘合剂层470涂覆到硅裸片的底面。选择粘合剂层470具有模塑材料460的类似TCE和Tg特征。
在示例实施例中,可以在模块测试条件下使用适应的弹性转接层的再利用特点来确定给定硅裸片在测试后是否可用。在封装基板的阵列中,可以把给定数量的硅裸片放置并压紧在每个封装基板的转接结构上。随后可以对每个硅裸片进行电气测试。剔除有缺陷的器件。替换器件可以取代有缺陷的器件。因此,在封装之前,确保封装基板的阵列中的全部器件是可用的。
参考图7。可以使用处理过程500来装配IC器件并且在封装之前对其进行测试。选择具有与IC器件的I/O接触焊盘数量相对应数量的凸起焊盘的相容的封装基板505。将按照电路图案区域尺寸所切割出来的弹性转接结构施加到封装基板510的凸起焊盘510。沿倒装芯片朝向把IC器件放置在转接结构上515。在IC器件裸片上施加压缩力520。压缩力使得在转接结构中相互分离的球形导体将I/O接触焊盘与封装基板上对应的凸起焊盘电连接起来。可以在IC器件裸片上进行电气测试(E-test)525。如果IC器件没有通过测试530,则可以将有缺陷的裸片剔除并且用其他的来代替。在IC器件裸片成功完成电气测试之后,可以把IC器件向下锁定在转接基板上535。向下锁定使得转接结构保持在变形状态,维持了I/O接触焊盘以及对应的凸起焊盘之间的相互分离的球形导体的电连接。另外,在向下锁定IC器件之后,可以把IC器件封装在模塑材料的钝化封壳中540。
如上所述,可以但是并不必限于通过把IC器件封装在具有相对于封装基板的较大TCE失配的钝化封壳中(见图3)来完成向下锁定。钝化封壳和封装基板在维持转接结构变形中提供了用于保持IC器件上的压力的相反的力。可以把机械夹具物理附接到封装基板来提供直接作用在IC器件裸片上的夹持力。一个夹具可以沿封装基板的长度围绕来提供夹持力(见图4、5A-5B)。安装在IC器件上并且用保持头向下固定的另一夹具可以提供夹持力。这个夹具(见图6A-6B)连同IC器件、转接结构和封装基板一起被封装在模塑材料的钝化封壳中。
相对于图4,压力可以源自多步骤固化处理。首先,在低温模塑后,接着进行高温模塑固化。因此,机械和材料压力组合在转接结构上提供了压缩力。二次模塑仍然主要用于环境保护。在示例封装中,足够使转接结构变形的力估计大约为10到40grams/mm2。最终的值由基板平整度来确定,并且可以随不同的封装类型而变化。
尽管参考几个特定示例实施例描述了本发明,但是本领域技术人员会认识到在不脱离由所附权利要求所确定的本发明的精神和范围的情况下可以对这些示例实施例进行很多变化。

Claims (15)

1.一种集成电路器件,其被装配在封装基板上并且被封装在模塑材料中,所述集成电路器件包括:
半导体裸片,其具有上表面和底面,所述上表面具有电路图案,所述电路图案包括预定排列的接触焊盘;
具有一定长度和宽度的封装基板,所述封装基板具有凸起焊盘连接端,所述焊盘连接端位于与电路图案的接触焊盘的预定排列相对应的排列中,所述凸起焊盘连接端具有把焊盘连接端耦接到封装基板中的外部接触区域的连接走线;以及
转接层,其夹在半导体裸片与封装基板之间,所述转接层包括嵌入在弹性材料中的球形颗粒的随机分布的相互分离的导电柱,
其中,所述转接层受到来自施加在半导体裸片的底面上的压力的压缩力的作用,所述压缩力使得转接层变形,使得球形颗粒的导电柱电连接到电路图案的接触焊盘,该电路图案具有封装基板的相应凸起焊盘连接端。
2.如权利要求1所述的集成电路器件,还包括焊接掩模层,具有与基板上的凸起焊盘连接端的排列相对应的开口。
3.如权利要求1所述的集成电路器件,其中从施加自模塑材料的压力来获得压缩力,所述模塑材料具有比封装基板的热膨胀系数大的热膨胀系数。
4.如权利要求2所述的集成电路器件,
其中所述模塑材料具有大约200℃到大约260℃范围内的玻璃化转变温度,
其中所述封装基板包括环氧树脂玻璃,以及
其中,所述焊接掩模层具有大约180℃到大约220℃范围内的玻璃化转变温度。
5.如权利要求1所述的集成电路器件,
其中所述压缩力是从与半导体裸片的底面相接触的金属夹具获得的,以及
所述金属夹具的长度跨过封装基板的长度和宽度,并且
所述金属夹具的高度小于半导体裸片、转接结构和封装基板的组合厚度,使得当金属夹具与封装基板啮合时,所述金属夹具提供所述压缩力。
6.如权利要求5所述的集成电路器件,其中所述压缩力是从与半导体裸片的底面相接触的预应力金属夹具获得的,
所 述金属夹具具有水平部件和垂直部件,所述水平部件基本上覆盖了半导体裸片的底面,所述垂直部件与保持头固定在限定于封装基板中的通孔中,所述保持头维持了所述压缩力。
7.如权利要求6所述的集成电路器件,其中所述金属夹具具有至少两个垂直部件。
8.如权利要求7所述的集成电路器件,其中所述金属夹具具有四个垂直部件。
9.一种集成电路器件,其被装配在封装基板上,所述集成电路器件包括:
半导体裸片,其具有上表面和底面,所述上表面具有电路图案,所述电路图案包括预定排列的接触焊盘;
具有一定长度和宽度的封装基板,所述封装基板具有凸起焊盘连接端,所述焊盘连接端位于与电路图案的接触焊盘的预定排列相对应的排列中,所述凸起焊盘连接端具有把焊盘连接端耦接到封装基板中的外部接触区域的连接走线;以及
转接层,其夹在半导体裸片与封装基板之间,所述转接层包括嵌入在弹性材料中的球形颗粒的随机分布的相互分离的导电柱,
其中,所述转接层受到来自施加在半导体裸片的底面上的压力的压缩力的作用,所述压缩力使得转接层变形,使得球形颗粒的导电柱电连接到电路图案的接触焊盘,该电路图案具有封装基板的相应凸起焊盘连接端,所述压缩力是由封装集成电路的模塑材料的热膨胀系数力所提供的。
10.如权利要求9所述的集成电路器件,其中附加压缩力是由半导体裸片的底面上与封装集成电路的模塑材料相接触的金属夹具所提供的,
所述金属夹具的长度和宽度是与封装基板的长度和宽度可比的,并且
所述金属夹具的长度略小于模塑材料、半导体裸片和转接结构的组合厚度,使得当所述金属夹具与封装基板啮合时,所述金属层提供了附加的压缩力。
11.一种集成电路器件,其被装配在封装基板上,所述集成电路器件包括:
半导体裸片,其具有上表面和底面,所述上表面具有电路图案,所述电路图案包括预定排列的接触焊盘;
具有一定长度和宽度的封装基板,所述封装基板具有凸起焊盘连接端,所述焊盘连接端位于与电路图案的接触焊盘的预定排列相对应的排列中,所述凸起焊盘连接端具有把焊盘连接端耦接到封装基板中的外部接触区域的连接走线;以及
转接层,其夹在半导体裸片与封装基板之间,所述转接层包括嵌入在弹性材料中的球形颗粒的随机分布的相互分离的导电柱,
其中,所述转接层受到来自金属夹具施加在半导体裸片的底面上的压力的压缩力的作用,所述压缩力使得转接层变形,使得球形颗粒的导电柱电连接到电路图案的接触焊盘,该电路图案具有封装基板对应的凸起焊盘连接端的;以及
模塑材料的钝化封壳将所述半导体裸片和转接结构封装起来。
12.如权利要求11所述的集成电路器件,所述金属夹具从以下金属夹具中选出:
外部金属夹具,其具有与封装基板的长度和宽度可比的长度和宽度,其高度略小于钝化封壳、半导体裸片、转接结构和封装基板的组合厚度,使得当所述金属夹具与封装基板啮合时,所述金属夹具提供所述压缩力,所述金属夹具安装在所述钝化封壳的外部;
内部金属夹具,其与半导体裸片的底面相接触,所述金属夹具具有水平部件和两个或多个垂直部件,所述水平部件基本上覆盖了半导体裸片的底面,所述垂直部件与保持头固定在限定于封装基板中的通孔中,所述保持头维持了所述压缩力,所述内部金属夹具与封装基板上的半导体裸片和转接结构一起被封装在所述钝化封壳中。
13.一种封装集成电路器件的方法,所述集成电路器件具有电路图案,所述电路图案包括在封装基板上沿倒装芯片朝向的I/O接触焊盘,所述封装基板具有与电路图案的I/O接触焊盘相对应的焊盘连接端,所述方法包括步骤:
a)选择适合于集成电路器件的I/O焊盘布局的封装基板;
b)在封装基板上施加转接结构,所述转接结构具有嵌入在弹性材料中的球形颗粒的随机分布的相互分离的导电柱;
c)在转接结构上沿倒装芯片朝向放置集成电路器件;
d)在集成电路器件上施加压缩力,所述压缩力使得转接层变形,使得球形颗粒的导电柱电连接到电路图案的接触焊盘,该电路图案具有封装基板对应的凸起焊盘连接端;
e)在集成电路器件上维持所述压缩力;以及
f)将集成电路器件封装在钝化封壳中。
14.如权利要求13所述的方法,其中在集成电路器件上保持所述压缩力还包括使用机械夹具。
15.如权利要求13所述的方法,还包括
d1)执行电气测试并且确定所述器件是否合格;
如果不合格,获得另一集成电路器件,并且执行步骤c)和d),
如果合格,转到步骤e)以及随后的步骤f)。
CN2006800443855A 2005-11-29 2006-11-29 具有适应的转接触点的无凸起的倒装芯片组件 Expired - Fee Related CN101317266B (zh)

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9861234B2 (en) * 2007-02-15 2018-01-09 Illinois Tool Works, Inc. Oil reclamation device and process
US7964444B2 (en) * 2007-02-15 2011-06-21 International Business Machines Corporation Method and apparatus for manufacturing electronic integrated circuit chip
WO2013165352A1 (en) 2012-04-30 2013-11-07 Hewlett-Packard Development Company, L.P. Socket with routed contacts
US9543197B2 (en) 2012-12-19 2017-01-10 Intel Corporation Package with dielectric or anisotropic conductive (ACF) buildup layer
US9202789B2 (en) * 2014-04-16 2015-12-01 Qualcomm Incorporated Die package comprising die-to-wire connector and a wire-to-die connector configured to couple to a die package
ITUB20155111A1 (it) * 2015-11-04 2017-05-04 St Microelectronics Srl Dispositivo a semiconduttore e relativo procedimento
US10014710B2 (en) * 2015-12-09 2018-07-03 Intel Corporation Foldable fabric-based packaging solution
US10153256B2 (en) * 2016-03-03 2018-12-11 X-Celeprint Limited Micro-transfer printable electronic component
US9953909B2 (en) * 2016-07-18 2018-04-24 Intel Corporation Ball grid array (BGA) with anchoring pins
EP3659055A4 (en) 2017-07-24 2021-04-28 Cerebras Systems Inc. DEVICE AND METHOD FOR MULTI-CHIP CONNECTION
EP3659178A4 (en) * 2017-07-24 2021-05-19 Cerebras Systems Inc. DEVICE AND METHOD FOR FASTENING SUBSTRATES WITH VARIATING COEFFICIENTS OF THERMAL EXPANSION
US10242891B2 (en) 2017-08-24 2019-03-26 Cerebras Systems Inc. Apparatus and method for securing components of an integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4820376A (en) * 1987-11-05 1989-04-11 American Telephone And Telegraph Company At&T Bell Laboratories Fabrication of CPI layers
US5345365A (en) * 1992-05-05 1994-09-06 Massachusetts Institute Of Technology Interconnection system for high performance electronic hybrids

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB804171A (en) 1954-12-01 1958-11-12 Westinghouse Brake & Signal Improvements relating to metal rectifier assemblies
US6190509B1 (en) 1997-03-04 2001-02-20 Tessera, Inc. Methods of making anisotropic conductive elements for use in microelectronic packaging
US6518089B2 (en) * 2001-02-02 2003-02-11 Texas Instruments Incorporated Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
US20030186572A1 (en) * 2002-04-01 2003-10-02 Hougham Gareth Geoffrey Self compensating design for elastomer interconnects

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4820376A (en) * 1987-11-05 1989-04-11 American Telephone And Telegraph Company At&T Bell Laboratories Fabrication of CPI layers
US5345365A (en) * 1992-05-05 1994-09-06 Massachusetts Institute Of Technology Interconnection system for high performance electronic hybrids

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