US20070252288A1 - Semiconductor module and method for forming the same - Google Patents

Semiconductor module and method for forming the same Download PDF

Info

Publication number
US20070252288A1
US20070252288A1 US11/772,901 US77290107A US2007252288A1 US 20070252288 A1 US20070252288 A1 US 20070252288A1 US 77290107 A US77290107 A US 77290107A US 2007252288 A1 US2007252288 A1 US 2007252288A1
Authority
US
United States
Prior art keywords
chip
semiconductor chip
substrate
interposer structure
connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/772,901
Inventor
Mukta Farooq
John Knickerbocker
Frank Pompeo
Subhash Shinde
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/772,901 priority Critical patent/US20070252288A1/en
Publication of US20070252288A1 publication Critical patent/US20070252288A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Definitions

  • the present invention generally relates to a semiconductor module and method for forming the same. Specifically, the present invention provides a semiconductor module having an interposer structure with metallurgical through connections for electrically connecting a semiconductor chip to a substrate.
  • a semiconductor chip In the production of semiconductor modules, a semiconductor chip is often connected to a carrier such as a substrate. Typically, the connection is made using controlled collapse chip connection (C4) technology whereby solder bumps are used to join the two components together.
  • C4 controlled collapse chip connection
  • the semiconductor chip usually has a different coefficient of thermal expansion (CTE) than the substrate. Given the close physical proximity of the semiconductor chip to the substrate, the solder bumps often deteriorate as the module heats up and cools off. This is especially the case with larger die sizes.
  • ceramic substrates are generally non-planar, which can become a gating factor as the substrate X-Y dimensions increase.
  • shrinking pitch there is a need to shrink C4 bump dimensions to avoid nearest neighbor shorting.
  • a small C4 bump height results in a larger percentage of variation across the grid of bumps.
  • current methods of depositing and joining C4 interconnections are expensive and involve the use of specific under bump metallization (UBM), which might have to be customized.
  • the UBM may need additional layers such as diffusion barriers and chip encapsulants so that it may endure a melting or partially melting C4 structure that reacts with the UBM during subsequent assembly operations.
  • the present invention provides a semiconductor module and method for forming the same.
  • a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure.
  • the interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape.
  • the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate.
  • a first aspect of the present invention provides a semiconductor module, comprising a semiconductor chip; a substrate; and an interposer structure electrically connecting the semiconductor chip to the substrate, wherein the interposer structure includes metallurgical through connections having a predetermined shape.
  • a second aspect of the present invention provides a semiconductor module, comprising a semiconductor chip having an under bump metallization; a substrate having a top surface metallization; and an interposer structure electrically connecting the under bump metallization to the top surface metallization, wherein the interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape.
  • a third aspect of the present invention provides a method for forming a semiconductor module, comprising: embedding metallurgical through connections within an elastomeric, compliant material to form an interposer structure; and positioning the interposer structure between a semiconductor chip and a substrate to electrically connect the semiconductor chip to the substrate.
  • the present invention provides a semiconductor module and method for forming the same.
  • FIG. 1 depicts a semiconductor module having an interposer structure, according to the present invention.
  • FIG. 2 depicts the semiconductor module of FIG. 1 further including a heat spreader and a heat sink.
  • FIG. 3 depicts the semiconductor module of FIG. 2 further including underfill.
  • FIG. 4 depicts the semiconductor module of FIG. 3 under a Land Grid Array load.
  • FIG. 5 depicts the semiconductor module of FIG. 1 in a TCA application.
  • the present invention provides a semiconductor module and method for forming the same.
  • a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure.
  • the interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape.
  • the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate.
  • semiconductor module 10 includes semiconductor chip 12 and carrier/substrate 14 with interposer structure 16 positioned therebetween.
  • semiconductor module 10 could be a single chip module or a multi-chip module.
  • interposer structure 16 could be positioned between each semiconductor chip and substrate 14 .
  • substrate 14 could be any type of substrate now known or later developed.
  • substrate 14 could be ceramic or organic.
  • interposer structure 16 is positioned between semiconductor chip 12 and substrate 14 under the present invention to preserve the interface therebetween.
  • interposer structure 16 generally comprises a elastomeric, compliant material 20 having metallurgical through connections 18 “embedded” or “positioned” therein.
  • Metallurgical through connections 18 electrically connect under bump metallization (UBM) or bottom layer metallurgy (BLM) 22 of semiconductor chip 12 to top surface metallurgy (TSM) 24 of substrate 14 .
  • interposer structure 16 can comprise Cupil-T, which is commercially available from Nitto Denko, Inc. of Osaka, Japan.
  • metallurgical through connections 18 can be formed to have a predetermined shape depending on the load applied to semiconductor module 10 to best optimize the contact.
  • metallurgical through connections 18 could be spherical, ellipsoid, s-shaped, c-shaped, or elongate (i.e., column-like). various factors can be considered when determining the shape of metallurgical through connections 18 .
  • Such factors include, among other things: (1) camber (i.e., non-flatness of substrate 14 and semiconductor chip 12 ) in that more camber might mean taller through connections with an overall greater degree of compressibility; (2) distortion (i.e., positional accuracy of the I/O pads on substrate 14 ) in that the worse the distortion, the bigger the contact area on metallurgical through connections 18 that would have to be provided so that some degree of contact is always present between metallurgical through connections 18 and the I/O pads; and (3) process considerations such as how the through connections are made.
  • metallurgical through connections 18 could be formed from one or more materials. To this extent, metallurgical through connections 18 could have a core formed from Copper, Copper-Beryllium, or the like that is coated with gold. Still yet, UBM 22 and/or TSM 24 could be gold, solder or the like.
  • interposer structure 16 could be rigidly attached (e.g., hard soldered) to either UBM 22 or TSM 24 , or both.
  • LGA Land Grid Array
  • metallurgical through connections 18 could be hard soldered to TSM 24 , while the contact between metallurgical through connections 18 and UBM 22 is maintained solely by the LGA load. This would enable free expansion of the semiconductor chip side of interposer structure 16 under the influence of temperature. Since interposer structure 16 would not cause any strains due to TCE mismatch, the reliability of semiconductor module 10 would increase considerably. Further, this method would allow for self-aligned solder joining of metallurgical through connections 18 to the I/O pads on substrate 14 , thus eliminating the concern of inadequate surface contact area when the to pad distortion is on the high end of the specification.
  • LGA Land Grid Array
  • FIG. 2 semiconductor module 10 of FIG. 1 further including a heat spreader 26 and heat sink 30 is shown.
  • heat spreader 26 is attached to semiconductor chip 12 using thermally conductive adhesive 28 .
  • substrate 14 and/or interposer structure 16 support posts 32 A-B can be provided adjacent to interposer structure 16 .
  • support posts 32 A-B extend from substrate 14 to heat spreader 26 , and support heat spreader 26 over semiconductor chip 12 . It should be appreciated that the quantity of support posts 32 A-B shown in FIG. 2 is intended to be illustrative only, and should not be limiting.
  • underfill 34 can be provided throughout the interconnection, or at predetermined locations.
  • underfill 34 can be a heat-curable material, selected from a broad range of chemical compositions including both rigid and flexibilized thermosetting epoxies, thermoplastics, urethanes, polysulfones, polyimides, polyetheramides/imides, and hybrids of same.
  • underfill 34 can be a more compliant, thermoplastic material such as a silicone based product.
  • underfill 34 when underfill 34 is used, metallurgical through connections 18 could be rigidly attached to both UBM 22 and TSM 24 to provide a desired level of thermo-mechanical fatigue.
  • underfill 34 may be applied between interposer structure 16 and semiconductor chip 12 , between interposer structure 16 and substrate 14 , or between semiconductor chip 12 and substrate 14 (including interposer structure 16 ).
  • a typical, high-modulus of elasticity underfill is indicated, e.g., materials having modulus ranging from 1-10 Giga Pascals.
  • yet another embodiment uses underfill 34 between semiconductor chip 12 and interposer structure 16 if metallurgical through connections 18 are permanently attached to the semiconductor chip 12 .
  • a more compliant, flexible, underfill material (having elastic modulus in the tens or hundreds of Mega Pascals, for example) is provided between the semiconductor chip 12 and substrate, including metallurgical through connections 18 .
  • This feature would allow lateral displacement of the electrical contacts in response to thermally-induced stresses while preserving environmental protection of the IC devices(s) and joints.
  • interposer structure 16 can be used within semiconductor modules 10 in a variety of scenarios and applications. In addition, although not shown herein, interposer structure 16 could be used as a fan-out layer so that a very fine pitch in UBM 22 may be connected to a more coarse pitch in substrate 14 .
  • interposer structure 16 could be integrated at the wafer level (e.g., 8 or 12 inch wafers) and electrically tested before chip singulation (e.g., dicing) is performed.

Abstract

Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.

Description

    REFERENCE TO PRIOR APPLICATIONS
  • The current application is a continuation application of co-pending U.S. patent application Ser. No. 10/721,984, filed on 25 Nov. 2003, which is hereby incorporated by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention generally relates to a semiconductor module and method for forming the same. Specifically, the present invention provides a semiconductor module having an interposer structure with metallurgical through connections for electrically connecting a semiconductor chip to a substrate.
  • 2. Related Art
  • In the production of semiconductor modules, a semiconductor chip is often connected to a carrier such as a substrate. Typically, the connection is made using controlled collapse chip connection (C4) technology whereby solder bumps are used to join the two components together. Unfortunately, several problems emerge with the existing technology. First, the semiconductor chip usually has a different coefficient of thermal expansion (CTE) than the substrate. Given the close physical proximity of the semiconductor chip to the substrate, the solder bumps often deteriorate as the module heats up and cools off. This is especially the case with larger die sizes.
  • In addition, ceramic substrates (if used) are generally non-planar, which can become a gating factor as the substrate X-Y dimensions increase. With shrinking pitch, there is a need to shrink C4 bump dimensions to avoid nearest neighbor shorting. However, a small C4 bump height results in a larger percentage of variation across the grid of bumps. Further, when the interconnections at the chip to substrate level migrate to a lead-free system, there will be no solder temperature hierarchy between first and second level interconnections, thus, creating an increased strain on the C4 structure due to higher temperatures of subsequent assembly operations. Still yet, current methods of depositing and joining C4 interconnections are expensive and involve the use of specific under bump metallization (UBM), which might have to be customized. Also, the UBM may need additional layers such as diffusion barriers and chip encapsulants so that it may endure a melting or partially melting C4 structure that reacts with the UBM during subsequent assembly operations.
  • In view of the foregoing, there exists a need for an improved semiconductor module and method for forming the same. Specifically, a need exists for a semiconductor chip to be electrically connected to a substrate or the like so that the above concerns are alleviated.
    • SUMMARY OF THE INVENTION
  • In general, the present invention provides a semiconductor module and method for forming the same. Specifically, under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.
  • A first aspect of the present invention provides a semiconductor module, comprising a semiconductor chip; a substrate; and an interposer structure electrically connecting the semiconductor chip to the substrate, wherein the interposer structure includes metallurgical through connections having a predetermined shape.
  • A second aspect of the present invention provides a semiconductor module, comprising a semiconductor chip having an under bump metallization; a substrate having a top surface metallization; and an interposer structure electrically connecting the under bump metallization to the top surface metallization, wherein the interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape.
  • A third aspect of the present invention provides a method for forming a semiconductor module, comprising: embedding metallurgical through connections within an elastomeric, compliant material to form an interposer structure; and positioning the interposer structure between a semiconductor chip and a substrate to electrically connect the semiconductor chip to the substrate.
  • Therefore, the present invention provides a semiconductor module and method for forming the same.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
  • FIG. 1 depicts a semiconductor module having an interposer structure, according to the present invention.
  • FIG. 2 depicts the semiconductor module of FIG. 1 further including a heat spreader and a heat sink.
  • FIG. 3 depicts the semiconductor module of FIG. 2 further including underfill.
  • FIG. 4 depicts the semiconductor module of FIG. 3 under a Land Grid Array load.
  • FIG. 5 depicts the semiconductor module of FIG. 1 in a TCA application.
  • The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.
    • DETAILED DESCRIPTION OF THE INVENTION
  • As indicated above, the present invention provides a semiconductor module and method for forming the same. Specifically, under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.
  • Referring now to FIG. 1, an illustrative semiconductor module 10 formed in accordance with the present invention is shown. As depicted, semiconductor module 10 includes semiconductor chip 12 and carrier/substrate 14 with interposer structure 16 positioned therebetween. It should be appreciated in advance that semiconductor module 10 could be a single chip module or a multi-chip module. In the case of a multi-chip module, interposer structure 16 could be positioned between each semiconductor chip and substrate 14. Moreover, it should be understood that substrate 14 could be any type of substrate now known or later developed. For example, substrate 14 could be ceramic or organic. In any event, interposer structure 16 is positioned between semiconductor chip 12 and substrate 14 under the present invention to preserve the interface therebetween. As indicated above, differences in the CTE between semiconductor chip 12 (e.g., 3 ppm/° C., CTE) and substrate 14 (15-18 ppm/° C., CTE for an organic substrate) cause various issues as semiconductor module 10 is subjected to temperature change. Positioning interposer structure 16 between semiconductor chip 12 and substrate 14 increases the distance between the two components and alleviates the problems associated with the difference in CTEs.
  • In any event, interposer structure 16 generally comprises a elastomeric, compliant material 20 having metallurgical through connections 18 “embedded” or “positioned” therein. Metallurgical through connections 18 electrically connect under bump metallization (UBM) or bottom layer metallurgy (BLM) 22 of semiconductor chip 12 to top surface metallurgy (TSM) 24 of substrate 14. In a typical embodiment, interposer structure 16 can comprise Cupil-T, which is commercially available from Nitto Denko, Inc. of Osaka, Japan. Moreover, metallurgical through connections 18 can be formed to have a predetermined shape depending on the load applied to semiconductor module 10 to best optimize the contact. For example, metallurgical through connections 18 could be spherical, ellipsoid, s-shaped, c-shaped, or elongate (i.e., column-like). various factors can be considered when determining the shape of metallurgical through connections 18. Such factors include, among other things: (1) camber (i.e., non-flatness of substrate 14 and semiconductor chip 12) in that more camber might mean taller through connections with an overall greater degree of compressibility; (2) distortion (i.e., positional accuracy of the I/O pads on substrate 14) in that the worse the distortion, the bigger the contact area on metallurgical through connections 18 that would have to be provided so that some degree of contact is always present between metallurgical through connections 18 and the I/O pads; and (3) process considerations such as how the through connections are made. In addition, metallurgical through connections 18 could be formed from one or more materials. To this extent, metallurgical through connections 18 could have a core formed from Copper, Copper-Beryllium, or the like that is coated with gold. Still yet, UBM 22 and/or TSM 24 could be gold, solder or the like.
  • To provide a more stable structure, interposer structure 16 could be rigidly attached (e.g., hard soldered) to either UBM 22 or TSM 24, or both. For example, if semiconductor module 10 is placed under a Land Grid Array (LGA) load, metallurgical through connections 18 could be hard soldered to TSM 24, while the contact between metallurgical through connections 18 and UBM 22 is maintained solely by the LGA load. This would enable free expansion of the semiconductor chip side of interposer structure 16 under the influence of temperature. Since interposer structure 16 would not cause any strains due to TCE mismatch, the reliability of semiconductor module 10 would increase considerably. Further, this method would allow for self-aligned solder joining of metallurgical through connections 18 to the I/O pads on substrate 14, thus eliminating the concern of inadequate surface contact area when the to pad distortion is on the high end of the specification.
  • Referring now to FIG. 2, semiconductor module 10 of FIG. 1 further including a heat spreader 26 and heat sink 30 is shown. As depicted, heat spreader 26 is attached to semiconductor chip 12 using thermally conductive adhesive 28. To prevent the increased weight cause by heat spreader 26 and heat sink 30 from damaging semiconductor chip 12, substrate 14 and/or interposer structure 16, support posts 32A-B can be provided adjacent to interposer structure 16. Specifically, support posts 32A-B extend from substrate 14 to heat spreader 26, and support heat spreader 26 over semiconductor chip 12. It should be appreciated that the quantity of support posts 32A-B shown in FIG. 2 is intended to be illustrative only, and should not be limiting.
  • Regardless, to further seal interposer member 16 between semiconductor chip 12 and substrate 14, underfill could be provided. Specifically, referring to FIG. 3, semiconductor module 10 of FIG. 2 is shown as further including underfill 34. Under the present invention, underfill 34 can be provided throughout the interconnection, or at predetermined locations. Further, underfill 34 can be a heat-curable material, selected from a broad range of chemical compositions including both rigid and flexibilized thermosetting epoxies, thermoplastics, urethanes, polysulfones, polyimides, polyetheramides/imides, and hybrids of same. Alternatively, underfill 34 can be a more compliant, thermoplastic material such as a silicone based product.
  • In any event, when underfill 34 is used, metallurgical through connections 18 could be rigidly attached to both UBM 22 and TSM 24 to provide a desired level of thermo-mechanical fatigue. To this extent, underfill 34 may be applied between interposer structure 16 and semiconductor chip 12, between interposer structure 16 and substrate 14, or between semiconductor chip 12 and substrate 14 (including interposer structure 16). In a typical embodiment, it is desirable to rigidly affix interposer structure 16 to substrate 14 whenever metallurgical through connections 18 are soldered to the substrate 14. In this case, a typical, high-modulus of elasticity underfill is indicated, e.g., materials having modulus ranging from 1-10 Giga Pascals. Similarly, yet another embodiment uses underfill 34 between semiconductor chip 12 and interposer structure 16 if metallurgical through connections 18 are permanently attached to the semiconductor chip 12.
  • In yet another embodiment of the invention, a more compliant, flexible, underfill material (having elastic modulus in the tens or hundreds of Mega Pascals, for example) is provided between the semiconductor chip 12 and substrate, including metallurgical through connections 18. This feature would allow lateral displacement of the electrical contacts in response to thermally-induced stresses while preserving environmental protection of the IC devices(s) and joints.
  • Referring now to FIG. 4, semiconductor module 10 of FIG. 3 under an LGA load is shown. Under an LGA load, forces are exerted on semiconductor module 10 in the direction of the arrows shown. As indicated above in conjunction with FIG. 1, metallurgical through connections 18 could be rigidly attached to TSM 24 under such a load. Referring to FIG. 5, semiconductor module 10 under a Temporary Chip Attachment (TCA) application is depicted. Under a TCA application, a porous surface is provided for vacuum pickup and/or placement of semiconductor chip 10. Accordingly, as can be seen, interposer structure 16 can be used within semiconductor modules 10 in a variety of scenarios and applications. In addition, although not shown herein, interposer structure 16 could be used as a fan-out layer so that a very fine pitch in UBM 22 may be connected to a more coarse pitch in substrate 14.
  • The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of this invention as defined by the accompanying claims. For example, in another embodiment, interposer structure 16 could be integrated at the wafer level (e.g., 8 or 12 inch wafers) and electrically tested before chip singulation (e.g., dicing) is performed.

Claims (11)

1. A temporary chip attachment structure, comprising:
a semiconductor chip;
a substrate;
an interposer structure electrically connecting the semiconductor chip to the substrate, wherein the interposer structure includes metallurgical through connections having a predetermined shape; and
a chip pick and place head adapted to one of pick up or place the semiconductor chip.
2. The temporary chip attachment structure of claim 1, the chip pick and place head further comprising a vacuum system for picking up the semiconductor chip.
3. The temporary chip attachment structure of claim 2, the vacuum system further comprising a porous surface on a side of the head adjacent the semiconductor chip.
4. The temporary chip attachment structure of claim 1, the chip pick and place head further comprising a cooling system configured to cool the head.
5. A temporary chip attachment structure, comprising:
a semiconductor chip having an under bump metallization;
a substrate having a top surface metallization;
an interposer structure electrically connecting the under bump metallization to the top surface metallization, wherein the interposer structure comprises an elastomeric, compliant material that includes metallurgical through connections having a predetermined shape; and
a chip pick and place head including a vacuum chip pick-up.
6. The temporary chip attachment structure of claim 5, the vacuum chip pick-up further comprising a porous surface on a side of the head adjacent the semiconductor chip.
7. The temporary chip attachment structure of claim 5, the chip pick and place head further comprising a cooling system configured to cool the head.
8. A method for attaching a semiconductor module, comprising:
providing embedded metallurgical through connections within an elastomeric, compliant material to form an interposer structure;
positioning the interposer structure between a semiconductor chip and a substrate to electrically connect the semiconductor chip to the substrate;
providing a chip pick and place head; and
attaching the chip pick and place head to the semiconductor chip.
9. The method of claim 8, the attaching further comprising using a vacuum system for picking up the semiconductor chip.
10. The method of claim 9, the vacuum system further comprising a porous surface on a side of the head adjacent the semiconductor chip.
11. The method of claim 8, the chip pick and place head further comprising a cooling system configured to cool the head.
US11/772,901 2003-11-25 2007-07-03 Semiconductor module and method for forming the same Abandoned US20070252288A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/772,901 US20070252288A1 (en) 2003-11-25 2007-07-03 Semiconductor module and method for forming the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/721,984 US7245022B2 (en) 2003-11-25 2003-11-25 Semiconductor module with improved interposer structure and method for forming the same
US11/772,901 US20070252288A1 (en) 2003-11-25 2007-07-03 Semiconductor module and method for forming the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/721,984 Continuation US7245022B2 (en) 2003-11-25 2003-11-25 Semiconductor module with improved interposer structure and method for forming the same

Publications (1)

Publication Number Publication Date
US20070252288A1 true US20070252288A1 (en) 2007-11-01

Family

ID=34591936

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/721,984 Expired - Fee Related US7245022B2 (en) 2003-11-25 2003-11-25 Semiconductor module with improved interposer structure and method for forming the same
US11/772,901 Abandoned US20070252288A1 (en) 2003-11-25 2007-07-03 Semiconductor module and method for forming the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/721,984 Expired - Fee Related US7245022B2 (en) 2003-11-25 2003-11-25 Semiconductor module with improved interposer structure and method for forming the same

Country Status (1)

Country Link
US (2) US7245022B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140035134A1 (en) * 2011-12-21 2014-02-06 Chuan Hu Dense interconnect with solder cap (disc) formation with laser ablation and resulting semiconductor structures and packages

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7566960B1 (en) 2003-10-31 2009-07-28 Xilinx, Inc. Interposing structure
US7245022B2 (en) * 2003-11-25 2007-07-17 International Business Machines Corporation Semiconductor module with improved interposer structure and method for forming the same
US9299634B2 (en) * 2006-05-16 2016-03-29 Broadcom Corporation Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages
US9013035B2 (en) * 2006-06-20 2015-04-21 Broadcom Corporation Thermal improvement for hotspots on dies in integrated circuit packages
JP5450188B2 (en) * 2010-03-16 2014-03-26 株式会社東芝 Radiation detection apparatus, method for manufacturing radiation detection apparatus, and image capturing apparatus
JP5699610B2 (en) * 2011-01-11 2015-04-15 富士通株式会社 MOUNTING STRUCTURE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE
KR102161173B1 (en) * 2013-08-29 2020-09-29 삼성전자주식회사 Package-on-package device and method of fabricating the same
US9706662B2 (en) 2015-06-30 2017-07-11 Raytheon Company Adaptive interposer and electronic apparatus
EP3115081B1 (en) 2015-07-08 2021-12-22 ScandiDos AB A system and a method for verifying a treatment plan
US9648729B1 (en) 2015-11-20 2017-05-09 Raytheon Company Stress reduction interposer for ceramic no-lead surface mount electronic device
WO2019022942A1 (en) 2017-07-24 2019-01-31 Cerebras Systems Inc. Apparatus and method for securing substrates with varying coefficients of thermal expansion
WO2019022902A1 (en) 2017-07-24 2019-01-31 Cerebras Systems Inc. Apparatus and method for multi-die interconnection
US10242891B2 (en) 2017-08-24 2019-03-26 Cerebras Systems Inc. Apparatus and method for securing components of an integrated circuit
US10840216B2 (en) 2019-03-05 2020-11-17 Cerebras Systems Inc. Systems and methods for powering an integrated circuit having multiple interconnected die
US11145530B2 (en) 2019-11-08 2021-10-12 Cerebras Systems Inc. System and method for alignment of an integrated circuit

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5338363A (en) * 1991-12-13 1994-08-16 Mitsubishi Denki Kabushiki Kaisha Chemical vapor deposition method, and chemical vapor deposition treatment system and chemical vapor deposition apparatus therefor
US5994910A (en) * 1994-12-21 1999-11-30 International Business Machines Corporation Apparatus, and corresponding method, for stress testing wire bond-type semi-conductor chips
US6020257A (en) * 1995-06-07 2000-02-01 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US6064217A (en) * 1993-12-23 2000-05-16 Epi Technologies, Inc. Fine pitch contact device employing a compliant conductive polymer bump
US6472305B1 (en) * 1999-04-08 2002-10-29 Casio Computer Co., Ltd. Method of manufacturing bonded structure of film substrate and semiconductor chip
US6799976B1 (en) * 1999-07-28 2004-10-05 Nanonexus, Inc. Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies
US6875921B1 (en) * 2003-10-31 2005-04-05 Xilinx, Inc. Capacitive interposer
US6911624B2 (en) * 2002-08-23 2005-06-28 Micron Technology, Inc. Component installation, removal, and replacement apparatus and method
US7245022B2 (en) * 2003-11-25 2007-07-17 International Business Machines Corporation Semiconductor module with improved interposer structure and method for forming the same
US7279358B2 (en) * 2002-04-26 2007-10-09 Toray Engineering Co., Ltd. Mounting method and mounting device

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5468681A (en) * 1989-08-28 1995-11-21 Lsi Logic Corporation Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias
US5810607A (en) * 1995-09-13 1998-09-22 International Business Machines Corporation Interconnector with contact pads having enhanced durability
US5734201A (en) * 1993-11-09 1998-03-31 Motorola, Inc. Low profile semiconductor device with like-sized chip and mounting substrate
US5834339A (en) * 1996-03-07 1998-11-10 Tessera, Inc. Methods for providing void-free layers for semiconductor assemblies
US6870272B2 (en) * 1994-09-20 2005-03-22 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
WO1996025839A1 (en) * 1995-02-16 1996-08-22 Micromodule Systems, Inc. Multiple chip module mounting assembly and computer using same
US6133744A (en) * 1995-04-28 2000-10-17 Nec Corporation Apparatus for testing semiconductor wafer
US5691041A (en) * 1995-09-29 1997-11-25 International Business Machines Corporation Socket for semi-permanently connecting a solder ball grid array device using a dendrite interposer
US5842273A (en) * 1996-01-26 1998-12-01 Hewlett-Packard Company Method of forming electrical interconnects using isotropic conductive adhesives and connections formed thereby
US5729433A (en) * 1996-01-30 1998-03-17 Micromodule Systems, Inc. Multiple chip module assembly for top of mother board
US6020220A (en) * 1996-07-09 2000-02-01 Tessera, Inc. Compliant semiconductor chip assemblies and methods of making same
US6133072A (en) * 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
US6224396B1 (en) * 1997-07-23 2001-05-01 International Business Machines Corporation Compliant, surface-mountable interposer
US6730541B2 (en) * 1997-11-20 2004-05-04 Texas Instruments Incorporated Wafer-scale assembly of chip-size packages
US6573609B2 (en) * 1997-11-25 2003-06-03 Tessera, Inc. Microelectronic component with rigid interposer
US6124546A (en) * 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
JP3849277B2 (en) * 1998-01-26 2006-11-22 ソニー株式会社 Semiconductor device
US6294407B1 (en) * 1998-05-06 2001-09-25 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same
US6365978B1 (en) * 1999-04-02 2002-04-02 Texas Instruments Incorporated Electrical redundancy for improved mechanical reliability in ball grid array packages
US6583354B2 (en) * 1999-04-27 2003-06-24 International Business Machines Corporation Method of reforming reformable members of an electronic package and the resultant electronic package
US6524115B1 (en) * 1999-08-20 2003-02-25 3M Innovative Properties Company Compliant interconnect assembly
US6264476B1 (en) * 1999-12-09 2001-07-24 High Connection Density, Inc. Wire segment based interposer for high frequency electrical connection
JP2001203318A (en) * 1999-12-17 2001-07-27 Texas Instr Inc <Ti> Semiconductor assembly having plural flip-chips
US6957963B2 (en) * 2000-01-20 2005-10-25 Gryphics, Inc. Compliant interconnect assembly
US6664621B2 (en) * 2000-05-08 2003-12-16 Tessera, Inc. Semiconductor chip package with interconnect structure
US6774315B1 (en) * 2000-05-24 2004-08-10 International Business Machines Corporation Floating interposer
US6459039B1 (en) * 2000-06-19 2002-10-01 International Business Machines Corporation Method and apparatus to manufacture an electronic package with direct wiring pattern
US6399892B1 (en) * 2000-09-19 2002-06-04 International Business Machines Corporation CTE compensated chip interposer
US6486415B2 (en) * 2001-01-16 2002-11-26 International Business Machines Corporation Compliant layer for encapsulated columns
US6756797B2 (en) * 2001-01-31 2004-06-29 Wentworth Laboratories Inc. Planarizing interposer for thermal compensation of a probe card
US7083436B2 (en) * 2001-03-06 2006-08-01 International Business Machines Corporation Particle distribution interposer and method of manufacture thereof
US6386890B1 (en) * 2001-03-12 2002-05-14 International Business Machines Corporation Printed circuit board to module mounting and interconnecting structure and method
US6583635B2 (en) * 2001-03-15 2003-06-24 Micron Technology, Inc. Semiconductor die test carrier having conductive elastomeric interposer
US6545226B2 (en) * 2001-05-31 2003-04-08 International Business Machines Corporation Printed wiring board interposer sub-assembly
US6695623B2 (en) * 2001-05-31 2004-02-24 International Business Machines Corporation Enhanced electrical/mechanical connection for electronic devices
JP3860000B2 (en) * 2001-09-07 2006-12-20 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US6830177B2 (en) * 2001-09-10 2004-12-14 General Dynamics Information Systems, Inc. Method and apparatus to compliantly interconnect commercial-off-the-shelf chip scale packages and printed wiring boards
US20030094666A1 (en) * 2001-11-16 2003-05-22 R-Tec Corporation Interposer
US6717066B2 (en) * 2001-11-30 2004-04-06 Intel Corporation Electronic packages having multiple-zone interconnects and methods of manufacture
JP2004031203A (en) * 2002-06-27 2004-01-29 Shin Etsu Polymer Co Ltd Electrically conductive contact element and electric connector
TW547771U (en) * 2002-07-23 2003-08-11 Via Tech Inc Elastic electrical contact package structure
US20040135594A1 (en) * 2003-01-14 2004-07-15 Beaman Brian Samuel Compliant interposer assembly for wafer test and "burn-in" operations
US6981879B2 (en) * 2004-03-18 2006-01-03 International Business Machines Corporation Land grid array (LGA) interposer with adhesive-retained contacts and method of manufacture
US7042077B2 (en) * 2004-04-15 2006-05-09 Intel Corporation Integrated circuit package with low modulus layer and capacitor/interposer
US6981880B1 (en) * 2004-06-22 2006-01-03 International Business Machines Corporation Non-oriented wire in elastomer electrical contact

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5338363A (en) * 1991-12-13 1994-08-16 Mitsubishi Denki Kabushiki Kaisha Chemical vapor deposition method, and chemical vapor deposition treatment system and chemical vapor deposition apparatus therefor
US6064217A (en) * 1993-12-23 2000-05-16 Epi Technologies, Inc. Fine pitch contact device employing a compliant conductive polymer bump
US5994910A (en) * 1994-12-21 1999-11-30 International Business Machines Corporation Apparatus, and corresponding method, for stress testing wire bond-type semi-conductor chips
US6020257A (en) * 1995-06-07 2000-02-01 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US6472305B1 (en) * 1999-04-08 2002-10-29 Casio Computer Co., Ltd. Method of manufacturing bonded structure of film substrate and semiconductor chip
US6799976B1 (en) * 1999-07-28 2004-10-05 Nanonexus, Inc. Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies
US7279358B2 (en) * 2002-04-26 2007-10-09 Toray Engineering Co., Ltd. Mounting method and mounting device
US6911624B2 (en) * 2002-08-23 2005-06-28 Micron Technology, Inc. Component installation, removal, and replacement apparatus and method
US6875921B1 (en) * 2003-10-31 2005-04-05 Xilinx, Inc. Capacitive interposer
US7245022B2 (en) * 2003-11-25 2007-07-17 International Business Machines Corporation Semiconductor module with improved interposer structure and method for forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140035134A1 (en) * 2011-12-21 2014-02-06 Chuan Hu Dense interconnect with solder cap (disc) formation with laser ablation and resulting semiconductor structures and packages
US9741645B2 (en) * 2011-12-21 2017-08-22 Intel Corporation Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages

Also Published As

Publication number Publication date
US20050110160A1 (en) 2005-05-26
US7245022B2 (en) 2007-07-17

Similar Documents

Publication Publication Date Title
US20070252288A1 (en) Semiconductor module and method for forming the same
US6570259B2 (en) Apparatus to reduce thermal fatigue stress on flip chip solder connections
US5528462A (en) Direct chip connection using demountable flip chip package
US6507119B2 (en) Direct-downset flip-chip package assembly and method of fabricating the same
EP1134804B1 (en) Thermally enhanced semiconductor carrier
US7224048B1 (en) Flip chip ball grid array package
US6221753B1 (en) Flip chip technique for chip assembly
US7300822B2 (en) Low warpage flip chip package solution-channel heat spreader
US6627998B1 (en) Wafer scale thin film package
US7015131B2 (en) Semiconductor device using bumps, method for fabricating same, and method for forming bumps
US9997383B2 (en) Bond head assemblies, thermocompression bonding systems and methods of assembling and operating the same
US20030051909A1 (en) Ball grid array attaching means having improved reliability and method of manufacturing same
US6552267B2 (en) Microelectronic assembly with stiffening member
JP3070579B2 (en) Semiconductor device mounting structure and mounting method
US7605020B2 (en) Semiconductor chip package
JP2002359345A (en) Semiconductor device and its manufacturing method
US7015066B2 (en) Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly
US6943060B1 (en) Method for fabricating integrated circuit package with solder bumps
US20030085453A1 (en) Flip chip semiconductor devices and heat sink assemblies, and the coupling thereof to form an electronic apparatus including a compliant support for supporting a heat sink
KR100298829B1 (en) Structure and Method of Solder Joint for Chip Size Package
US20230011493A1 (en) Package assembly including a package lid having a step region and method of making the same
US7094966B2 (en) Packaging integrated circuits with adhesive posts
CN113380723A (en) Packaging structure
JP3879319B2 (en) Semiconductor device and manufacturing method thereof
JPH10229105A (en) Semiconductor integrated circuit device and manufacture thereof

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE