CN101312158B - 互补式金氧半导体元件及其制造方法 - Google Patents

互补式金氧半导体元件及其制造方法 Download PDF

Info

Publication number
CN101312158B
CN101312158B CN200710167311.7A CN200710167311A CN101312158B CN 101312158 B CN101312158 B CN 101312158B CN 200710167311 A CN200710167311 A CN 200710167311A CN 101312158 B CN101312158 B CN 101312158B
Authority
CN
China
Prior art keywords
type metal
layer
semiconductor element
metal level
volts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN200710167311.7A
Other languages
English (en)
Other versions
CN101312158A (zh
Inventor
余振华
姚亮吉
林正堂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101312158A publication Critical patent/CN101312158A/zh
Application granted granted Critical
Publication of CN101312158B publication Critical patent/CN101312158B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26566Bombardment with radiation with high-energy radiation producing ion implantation of a cluster, e.g. using a gas cluster ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

本发明是关于一种有功函数值约等于或小于4.3或4.4eV的P型金属材料层形成于高介电系数介电层之上。部分的N型金属层添加例如是氧、氮、碳、硅或其他物后,转换成P型金属材料,成为一具有高功函数值约等于或大于4.7或4.8eV的P型金属材料。利用这项技术可将一碳化钽薄膜转换成氮碳化钽、氧碳化钽、或氮氧碳化钽。包括原始N型金属部分和已转换的P型金属部份的材料层利用单一图刻操作以同时在未转换的N型金属区域和已转换的P型金属区域形成半导体元件。

Description

互补式金氧半导体元件及其制造方法
技术领域
本发明涉及一种半导体元件和形成半导体元件的方法,特别是涉及一种适用于具有高介电系数的介电材料的金属栅极半导体元件的方法和结构。
背景技术
现今半导体制造工业迅速发展,用最有效率的方法,制造出最高多功能和最高集成度的半导体,在制程中显得相当重要。在制程操作为了符合经济效率,元件的制造上有相当程度上的复杂性和集积性,借此达到以最小的制造成本达到最大的生产量。
随着元件的复杂度和性能提升,高介电系数的介电材料应用在MOSFET的栅极电极上,也随着增加。一互补金氧半导体CMOS元件以高介电系数介电材料作为栅极介电材料时,须在P型金氧半导体PMOS和N型金氧半导体NMOS晶体管的栅极电极上使用不同的适当金属。在习知惯例上,不同材料需要分开进行制造和图刻操作。换言之,如果进行单一图刻,即,在两不同的材料上,要进行相同的蚀刻操作时,则其中至少有一材料会因为蚀刻进行过度或不足,而使元件的功能受到损害或元件完全失效。
由此,需要能仅提供一单一材料层,并在此单一材料层上使用一种蚀刻操作进行图刻,但是却能分别具有如同可与高介电系数材料及NMOS和PMOS元件结合的P型金属和N型金属的功能。这样的目的在于,使具有N型金属和P型金属元件在同一基板上的CMOS元件有效地的制造出来,并在制程操作上能提升经济产量。
有鉴于上述现有的互补金氧半导体CMOS元件存在的缺陷,本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识,并配合学理的运用,积极加以研究创新,以期创设一种新型的高介电系数金属栅极元件和制造方法,能够改进一般现有的互补金氧半导体CMOS元件,使其更具有实用性。经过不断的研究、设计,并经过反复试作样品及改进后,终于创设出确具实用价值的本发明。
发明内容
本发明的目的在于,克服现有的互补金氧半导体CMOS元件存在的缺陷,而提供一种新型的高介电系数金属栅极元件,所要解决的技术问题是使其大幅简化互补金氧半导体CMOS元件原有复杂的制造流程。
在同一材料的原始膜层上形成,同时进行图刻形成的P型金属和N型金属材料以形成对应的PMOS和NMOS的半导体元件。P型金属和N型金属是分别对应适用于N型和P型半导体元件上的材料,从而更加适于实用。
本发明的另一目的在于,提供一种形成金属栅极半导体元件的方法。此形成方法包括在基板表面上,形成一合适的N型金属层当作栅极电极或N型金属半导体元件,以及将部分N型金属层转换成P型金属层,作为P型金属半导体元件的栅极电极。本方法更提供利用N型金属层的未转换区形成N型金属半导体元件,利用P型金属部份的区域形成P型金属半导体元件。
根据本发明的另一目的,提出一种配置在基板上CMOS元件,包括至少一种NMOS半导体元件,此NMOS半导体元件包括一部分的碳化钽(TaC)层;和至少一PMOS半导体元件进一步包括一部分的碳化钽(TaC)层,这些进一步的部分包括至少添加一种氧、碳、氮和硅的杂质。
根据本发明又另一目的,提出一种配置在基板上的CMOS元件,包括至少一种NMOS晶体管,在二元材料层的一部分形成一栅极,其功函数值约等于或小于4.5eV;以及包括至少一种PMOS晶体管,在二元材料层的另一部位形成一栅极,其功函数值约等于或大于4.7eV。此二元材料层的另一部位包括至少添加一种氧、碳、氮和硅的杂质。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种半导体元件的形成方法,包括以下步骤:形成一N型金属层于一基板的一表面上,该N型金属层适用作为一N型金属半导体元件上的一栅极电极;转换部分该N型金属层成P型金属层部分,P型金属层适用作为一P型金属半导体元件上的栅极电极;以及形成N型金属半导体元件和P型金属半导体元件,这些N型金属半导体元件使用该N型金属层的未转换区,该P型金属半导体元件使用该P型金属部分其中该转换过程包含在N型金属层添加至少一碳(C)、氧(O)和硅(Si),用来将该N型金属层的该部分转换成P型金属部分。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的方法,其中所述的N型金属层包括碳化钽(TaC)或氮化钽(TaN)。
前述的方法,其中所述的N型金属层具有一功函数值为4.4电子伏特(eV)或小于4.4电子伏特。
前述的方法,其中所述的转换过程包括该P型金属区具有一功函数值4.8电子伏特(eV)或大于4.8电子伏特。
前述的方法,其中所述的转换过程包括在N型金属层添加至少一碳(C)、氧(O)、氮(N)和硅(Si),用来将该N型金属层的该部分转换成P型金属部分。
前述的方法,其中所述的添加方法包括离子注入法、扩散法或气体团簇离子束法(gas cluster ion beam)其中之一。
前述的方法,其中所述的转换过程包括在该N型金属层上形成一已图刻可移除层,该部分包括未受该已图刻可移除层覆盖的该N型金属层部分,更进一步包括在转换之后,移除该已图刻可移除层。
前述的方法,其中所述的可移除层包括光阻层、多晶硅层、氮化硅和氧化层其中之一。
前述的方法,其中形成这些N型金属半导体元件和P型金属半导体元件包括同时蚀刻该N型金属层的这些未转换部分和这些P型金属部分。
前述的方法,其中所述的N型金属层包括碳化钽(TaC)和经过转换的这些P型金属部位包括氧碳化钽(TaCO)、氮氧碳化钽(TaCON)和氮碳化钽(TaCN)其中之一。
前述的方法,其中所述的N型金属层包括以XY表示的二元材料以及经过转换的这些P型金属部分包括XY氧化物或XY氮化物或XY氮氧化合物其中之一。
前述的方法,其中形成这些N型金属半导体元件包括至少形成一N型金属栅极金氧半场效晶体管,和这些P型金属半导体元件的形成包括至少一P型金属栅极金氧半场效晶体管的形成。
前述的方法,其中形成一N型金属层包括在该表面上形成具有一高介电系数的该N型金属层,形成该N型金属半导体元件和形成该P型金属半导体元件包括利用该高介电系数介电材料作为栅极介电材料和该N型金属半导体元件与该P型金属半导体元件各自包括金属栅极晶体管。
前述的方法,其中所述的N型金属层包括钌(ruthenium)和这些转换部分包括将该钌氧化成氧化钌(RuO)。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种位于基板上的互补式金氧半导体元件,其特征在于包括:至少一NMOS半导体元件包括一碳化钽(TaC)层的一部分;以及至少一PMOS半导体元件包括该碳化钽(TaC)层的进一部分,该进一部分包括至少一氧(O)、氮(N)、碳(C)和硅(Si)杂质的添加。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的互补式金氧半导体元件,其中所述的其中该部分至少包括一功函数值等于4.4电子伏特(eV)或小于4.4电子伏特(eV),和该进一部分包括一功函数值约等于或大于4.42电子伏特(eV)。
前述的互补式金氧半导体元件,其中所述的NMOS半导体元件包括一NMOS金属栅极晶体管,具有在该碳化钽层的该部分形成的该金属栅极且配置于在该基板的一表面上形成的一高介电系数栅极介电材料上;以及该PMOS半导体元件包括一PMOS金属栅极晶体管,具有在该碳化钽层的该进一部分形成的该金属栅极且配置在该高介电系数栅极介电材料上。
本发明的目的及解决其技术问题另外还采用以下技术方案来实现。依据本发明提出的一种位于基板上的互补式金氧半导体元件,包括:至少一NMOS晶体管有一栅极在二元材料层的一部分形成,有一功函数值等于4.5电子伏特(eV)或小于4.5电子伏特(eV);和至少一PMOS晶体管,有一栅极形成于二元材料层的进一部分,有一功函数值等于4.7电子伏特(eV)或大于4.7电子伏特(eV);该进一部分包括至少一种氧(O)、碳(C)和硅(Si)杂质的添加。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的互补式金氧半导体元件,其中所述的二元材料的该层的该部分包括碳化钽(TaC)和该二元材料的该层的该进一部分包括氧碳化钽(TaCO)、氮氧碳化钽(TaCON)和氮碳化钽(TaCN)其中之一。
前述的互补式金氧半导体元件,其中每一该NMOS晶体管和该PMOS晶体管包括一高介电系数栅极介电材料。
借由上述技术方案,本发明互补式金氧半导体元件及其制造方法至少具有以下优点:
仅需要提供一单一材料层,并在此单一材料层上使用一种蚀刻操作进行图刻,但是却能分别具有如同可与高介电系数材料及NMOS和PMOS元件结合之P型金属和N型金属的功能。如此一来,具有N型金属和P型金属元件在同一基板上的CMOS元件能被有效地的制造出来,并在制程操作上能提升经济产量。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂。在施作上的方便,对于图式比例与详细特征并未按比例绘制,反而相对的作一些放大和缩小,达到清楚的显示,所附图式的详细说明如下:
图1到5是绘示一种侧视图,用来表示N型金属和P型金属元件依照本发明一实施例的连续操作程序。
2:半导体基板              4:绝缘元件
6:表面                    8:高介电系数介电层
10:layer                  10A:转换区
10B:未转换区              12:上表面
16:图刻区                 18:N型金属区
22:P型金属区              24:图刻层
26:图刻区            28:图刻区
46:图刻区            48:图刻区
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的高介电系数金属栅极元件和制造方法其具体实施方式、结构、特征及其功效,详细说明如后。
本发明是提供一种方法,在一原始N型金属层上形成一P型金属区域,以及在原始的N型金属层,形成P型半导体元件和N型半导体元件。此形成P型半导体元件的区域是由N型金属材料转换成P型金属材料区域。
请参照图1,是依照习知技术所绘示一基板2的剖面示意图。基板2是为一习知的半导体基板,可由各种适合的半导体材料,例如硅但不局限于硅,所制造。绝缘元件4由表面6向下形成于半导体基板2内。绝缘元件4可以是一浅沟渠隔离(shallow trench isolation;STI)元件或其他适合元件,用来将基板区彼此之间电性隔离。由各种适合的高介电系数介电材料所形成的高介电系数介电层8覆盖在基板2的表面6之上。在其他实施例中,适合的高介电性材料包括但不局限于各式的氧化硅、氮化硅和氮氧硅,或高介电系数的材料例如镧氧化物:三氧化二镧(La2O3)、铝氧化物:三氧化二铝(Al2O3)、铪氧化物:二氧化铪(HfO2)、氮氧铪化物(HfON)或锆氧化物:二氧化锆(ZrO2),或在相对于自由空间的介电常数大于5的高介电系数介电材料所形成的其他适合的栅极介电材料亦可运用于其他实施例上。高介电系数介电层8的尺寸依照元件的需求而定。高介电系数介电层8能形成一薄层适合用在NMOS和PMOS半导体元件,例如N型和P型金氧半导体场效晶体管(metal oxide semiconductor field effect transistors)。
膜层10形成于高介电系数介电层8上并具有上表面12。膜层10可为N型金属材料,N型金属材料适合作为N型半导体元件的栅极电极,N型半导体元件例如是NMOS晶体管,亦即膜层10具有4.3电子伏特(eV)或4.4电子伏特(eV)的功函数值。膜层10可为钌(ruthenium)、TaC、氮化钽(TaN)或各种适合的二元N型金属材料。膜层10的厚度约为1.0到2.0奈米(nm),但在其他实施例中则有不同厚度。
请参照图2,在膜层10的上表面12形成一可移除层,在经过图刻后,形成一不连续的部分。而图刻区16是可移除层经图刻后剩余在膜层10之上的部分。此可移除层为一光阻材料、多晶硅、氧化硅或其他适合的氧化物或其他材料,例如氮化硅(silicon nitride)。可利用传统的方法将完全覆盖于膜层10的上表面12的可移除层形成一图刻区16。图刻区16在N型金属区18中形成,其中的N型金属区18可形成N型元件,且位于此N型金属区18的膜层10会留下一不转换的N型金属材料。P型金属区22代表图刻区16形成的孔洞区域,在此区域可形成P型元件,而膜层10在此转换成P型金属层。通过位于N型金属区18的图刻区16,可利用多种方法将膜层10的曝露部分从N型金属材料转换成为P型金属材料。
将氧、氮、碳和/或硅晶与硅这类材料以植入法或其他方法导入膜层10的曝露部分,亦即,位于P型金属区22内的膜层10部分。在一实施例中,可利用离子注入法。在另一实施例中,可利用气体团簇离子束(gas cluster ionbeam;GCIB)注入技术,还有在其他实施例中,利用扩散作用将所需要的添加物/杂质驱入膜层10的曝露部分,并配合图刻区16防止添加物/杂质进入N型金属区18的膜层10。添加剂的加入可使膜层10的功函数值由沉积时约等于4.3或4.4eV或小于的数值,转换成等于或大于4.7或4.8eV。其他功函数值可利用在其他实施例上,但本发明的目的是使原始膜层18成为一种部分具有不同(相对高/相对低)功函数的膜层,其中已转换的P型金属区域具有增加的功函数值。
图3是绘示将图1和2中膜层10上的未转换区经过转换操作后,得到一P型金属材料的结构图。当在原始膜层所留下的未转换区10B作为N型金属材料并具有功函数值等于或小于4.3或4.4eV时,在P型金属区22内的转换区10A为P型金属材料并具有相对地高功函数值约等于或小于4.7或4.8eV。依照一实施例,其中原始膜层10是碳化钽(TaC),转换区10A可为碳氧化钽(TaCO)、碳氮化钽(TaCN)或碳氮氧化钽(TaCON),而未转换区10B为剩余的碳化钽(TaC)。依照另一实施例,其中膜层10是钌(ruthenium),转换区10A可为氧化钌(RuO),而未转换区10B为剩余的钌。依照另一实施例,其中原始膜层10为氮化钽(TaN),转换区10A可为氮氧化钽(TaON)或氮硅化钽(TaSiN)。这些薄膜层的细部在此为一举例,在其他实施例中可使用其他材料。依照习知描述,膜层10是由XY组成的二元材料,为一般的N型金属材料具有功函数值约等于或小于4.3或4.4eV,且经过转换后可得到一转换区10A。此转换区10A是由氧、氮或二元材料的氮氧化合物变化如XYON,XYN或XYO所组成。依照另一实施例目的,其中碳作为杂质添加在膜层10中,此添加的碳成份可将原始N型金属转换成具有高功函数值的P型金属。
图4是绘示,从图3中,将可移除层16利用习知方法移除之后,并在膜层10的转换区10A和未转换区10B上方形成图刻层24的结构图。然后再进一步进行图刻操作,将图刻区26和28在P型金属区22内的转换区10A上和在N型金属区18内的未转换区10B上同时分别形成。
如图5所示,不连续的区域46和48是应用习知的布局和蚀刻操作方法形成。由未转换区10B的N型金属材料所形成的不连续区域46可用来形成例如是N型金氧半场效晶体管的N半导体元件的栅极电极。由转换区10A的P型金属材料所形成的不连续区域48可作为半导体元件中的P型金属结构,作为PMOS晶体管的栅极,例如是P型金氧半场效晶体管。通过这些方法可形成各自具有高介电系数栅极介电材料的P型金属栅极晶体管和N型金属栅极晶体管。这些应用在此仅作为实施范例,且在其他施实例中,转换区10A和未转换区10B可同时通过图刻形成各自的P型金属和N型金属结构,然后在各种不同的应用上使用。
虽然本发明已以一较佳实施例揭露如上,然其并非用以限定本发明,任何熟习此技艺者,在不脱离本发明的精神和范围内,当可作各种的更动与润饰。所有提及的实施例和条件可作为一教学目的并有助于操作者了解本发明的原理和对本发明概念进一步的延伸。更甚之,本发明所有的步骤、原理细节、目的和其相关的发明实施例皆包括等效的结构与功能。此外,与此相同的等效性亦包括现今经验和未来发展,即开发任何与其相同功能或构造的元件。
本发明实施例中所提及的一些与附属图上,对于整体描述时的相关术语,例如是“低”、“高”、“水平”、“垂直”、“上”、“下”、“底”或其他衍生词例如是“水平的”、“下方的”、“上方的”可依照图示内容做判示。这类相关术语可提供方便的描述,但不要求在某一特定部位进行操作。关于其他专有名词像是“耦合”、“邻接”、“连接”、“内部连接”用以表示在构造中,相邻两物的稳定性和附属性,而非指直接或间接介于结构中间。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。

Claims (19)

1.一种半导体元件的形成方法,其特征在于包括以下步骤:
形成一N型金属层于一基板的一表面上,该N型金属层适用作为一N型金属半导体元件上的一栅极电极;
转换部分该N型金属层成P型金属层部分,P型金属层适用作为一P型金属半导体元件上的栅极电极;以及
形成N型金属半导体元件和P型金属半导体元件,这些N型金属半导体元件使用该N型金属层的未转换区,该P型金属半导体元件使用该P型金属层部分;
其中该转换过程包含在N型金属层添加至少一碳(C)或氧(O),用来将该N型金属层的该部分转换成P型金属层部分。
2.根据权利要求1所述的方法,其特征在于所述的N型金属层包括碳化钽或氮化钽。
3.根据权利要求1所述的方法,其特征在于所述的N型金属层具有一功函数值为4.4电子伏特或小于4.4电子伏特。
4.根据权利要求3所述的方法,其特征在于所述的转换过程包括该P型金属层部分具有一功函数值4.8电子伏特或大于4.8电子伏特。
5.根据权利要求1所述的方法,其特征在于所述的添加方法包括离子注入法、扩散法或气体团簇离子束法其中之一。
6.根据权利要求1所述的方法,其特征在于所述的转换过程包括在该N型金属层上形成一已图刻可移除层,该P型金属层部分包括未受该已图刻可移除层覆盖的该N型金属层部分,更进一步包括在转换之后,移除该已图刻可移除层。
7.根据权利要求6所述的方法,其特征在于所述的可移除层包括光阻层、多晶硅层、氮化硅和氧化层其中之一。
8.根据权利要求1所述的方法,其特征在于其中形成这些N型金属半导体元件和P型金属半导体元件包括同时蚀刻该N型金属层的这些未转换部分和这些P型金属层部分。
9.根据权利要求1所述的方法,其特征在于所述的N型金属层包括碳化钽和经过转换的这些P型金属层部分包括氧碳化钽、氮氧碳化钽(TaCON)和氮碳化钽其中之一。
10.根据权利要求1所述的方法,其特征在于所述的N型金属层包括以XY表示的二元材料以及经过转换的这些P型金属层部分包括XY氧化物或XY氮氧化合物其中之一。
11.根据权利要求1所述的方法,其特征在于其中形成这些N型金属半导体元件包括至少形成一N型金属栅极金氧半场效晶体管,和这些P型金属半导体元件的形成包括至少一P型金属栅极金氧半场效晶体管的形成。
12.根据权利要求1所述的方法,其特征在于其中形成一N型金属层包括在该表面上形成具有一高介电系数的该N型金属层,形成该N型金属半导体元件和形成该P型金属半导体元件包括利用该高介电系数介电材料作为栅极介电材料和该N型金属半导体元件与该P型金属半导体元件各自包括金属栅极晶体管。
13.根据权利要求1所述的方法,其特征在于所述的N型金属层包括钌和这些转换部分包括将该钌氧化成氧化钌。
14.一种位于基板上的互补式金氧半导体元件,其特征在于包括:
至少一NMOS半导体元件包括一碳化钽层的一部分;以及
至少一PMOS半导体元件包括该碳化钽层的进一部分,该进一部分包括至少一氧(O)或碳(C)杂质的添加。
15.根据权利要求14所述的互补式金氧半导体元件,其特征在于其中该部分至少包括一功函数值等于4.4电子伏特或小于4.4电子伏特,和该进一部分包括一功函数值等于或大于4.42电子伏特。
16.根据权利要求14所述的互补式金氧半导体元件,其特征在于所述的NMOS半导体元件包括一NMOS金属栅极晶体管,具有在该碳化钽层的该部分形成的该NMOS金属栅极晶体管的金属栅极且配置于在该基板的一表面上形成的一高介电系数栅极介电材料上;以及该PMOS半导体元件包括一PMOS金属栅极晶体管,具有在该碳化钽层的该进一部分形成的该PMOS金属栅极晶体管的金属栅极且配置在该高介电系数栅极介电材料上。
17.一种位于基板上的互补式金氧半导体元件,其特征在于包括:
至少一NMOS晶体管有一栅极在二元材料层的一部分形成,有一功函数值等于4.5电子伏特或小于4.5电子伏特;和
至少一PMOS晶体管,有一栅极形成于二元材料层的进一部分,有一功函数值等于4.7电子伏特或大于4.7电子伏特;该进一部分包括至少一氧(O)或碳(C)杂质的添加。
18.根据权利要求17所述的互补式金氧半导体元件,其特征在于所述的二元材料的该层的该部分包括碳化钽和该二元材料的该层的该进一部分包括氧碳化钽、氮氧碳化钽和氮碳化钽其中之一。
19.根据权利要求17所述的互补式金氧半导体元件,其特征在于其中每一该NMOS晶体管和该PMOS晶体管包括一高介电系数栅极介电材料。
CN200710167311.7A 2007-05-21 2007-10-22 互补式金氧半导体元件及其制造方法 Active CN101312158B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/751,403 2007-05-21
US11/751,403 US20080290416A1 (en) 2007-05-21 2007-05-21 High-k metal gate devices and methods for making the same

Publications (2)

Publication Number Publication Date
CN101312158A CN101312158A (zh) 2008-11-26
CN101312158B true CN101312158B (zh) 2011-05-25

Family

ID=40071604

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200710167311.7A Active CN101312158B (zh) 2007-05-21 2007-10-22 互补式金氧半导体元件及其制造方法

Country Status (3)

Country Link
US (2) US20080290416A1 (zh)
CN (1) CN101312158B (zh)
TW (1) TWI405269B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7585762B2 (en) * 2007-09-25 2009-09-08 Applied Materials, Inc. Vapor deposition processes for tantalum carbide nitride materials
US7678298B2 (en) 2007-09-25 2010-03-16 Applied Materials, Inc. Tantalum carbide nitride materials by vapor deposition processes
US7960802B2 (en) 2008-11-21 2011-06-14 Texas Instruments Incorporated Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low thermal budget
US8643113B2 (en) 2008-11-21 2014-02-04 Texas Instruments Incorporated Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer and a sacrificial oxygen gettering layer
CN101930913B (zh) * 2009-06-26 2012-05-23 中芯国际集成电路制造(上海)有限公司 金属栅电极形成方法
US8536654B2 (en) 2010-01-13 2013-09-17 Texas Instruments Incorporated Structure and method for dual work function metal gate CMOS with selective capping
US8330227B2 (en) * 2010-02-17 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated semiconductor structure for SRAM and fabrication methods thereof
US9384962B2 (en) * 2011-04-07 2016-07-05 United Microelectronics Corp. Oxygen treatment of replacement work-function metals in CMOS transistor gates
US8765590B2 (en) 2012-10-31 2014-07-01 International Business Machines Corporation Insulative cap for borderless self-aligning contact in semiconductor device
US9362230B1 (en) 2015-05-27 2016-06-07 Globalfoundries Inc. Methods to form conductive thin film structures
KR102358318B1 (ko) 2015-06-04 2022-02-04 삼성전자주식회사 멀티 일함수 게이트 패턴들을 갖는 반도체 소자

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7033919B1 (en) * 2002-10-30 2006-04-25 Yu Allen S Fabrication of dual work-function metal gate structure for complementary field effect transistors

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5907780A (en) * 1998-06-17 1999-05-25 Advanced Micro Devices, Inc. Incorporating silicon atoms into a metal oxide gate dielectric using gas cluster ion beam implantation
US6130123A (en) * 1998-06-30 2000-10-10 Intel Corporation Method for making a complementary metal gate electrode technology
US20020008257A1 (en) * 1998-09-30 2002-01-24 John P. Barnak Mosfet gate electrodes having performance tuned work functions and methods of making same
US6265296B1 (en) * 1999-03-04 2001-07-24 Vanguard International Semiconductor Corporation Method for forming self-aligned contacts using a hard mask
US6815816B1 (en) * 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US6518106B2 (en) * 2001-05-26 2003-02-11 Motorola, Inc. Semiconductor device and a method therefor
US6890807B2 (en) * 2003-05-06 2005-05-10 Intel Corporation Method for making a semiconductor device having a metal gate electrode
US20050104142A1 (en) * 2003-11-13 2005-05-19 Vijav Narayanan CVD tantalum compounds for FET get electrodes
US7023064B2 (en) * 2004-06-16 2006-04-04 International Business Machines Corporation Temperature stable metal nitride gate electrode
US20070059929A1 (en) * 2004-06-25 2007-03-15 Hag-Ju Cho Method of forming a tantalum carbon nitride layer and method of manufacturing a semiconductor device using the same
US20060060930A1 (en) * 2004-09-17 2006-03-23 Metz Matthew V Atomic layer deposition of high dielectric constant gate dielectrics
US7514310B2 (en) * 2004-12-01 2009-04-07 Samsung Electronics Co., Ltd. Dual work function metal gate structure and related method of manufacture
US20060172480A1 (en) * 2005-02-03 2006-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Single metal gate CMOS device design
US7348232B2 (en) * 2005-03-01 2008-03-25 Texas Instruments Incorporated Highly activated carbon selective epitaxial process for CMOS
US20070059874A1 (en) * 2005-07-06 2007-03-15 Sematech, Inc. Dual Metal Gate and Method of Manufacture
US7229873B2 (en) * 2005-08-10 2007-06-12 Texas Instruments Incorporated Process for manufacturing dual work function metal gates in a microelectronics device
WO2008058049A2 (en) * 2006-11-06 2008-05-15 Semequip, Inc. Ion implantation device and method of semiconductor manufacturing by the implantation of molecular ions containing phosphorus and arsenic
US7682891B2 (en) * 2006-12-28 2010-03-23 Intel Corporation Tunable gate electrode work function material for transistor applications
US7732285B2 (en) * 2007-03-28 2010-06-08 Intel Corporation Semiconductor device having self-aligned epitaxial source and drain extensions

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7033919B1 (en) * 2002-10-30 2006-04-25 Yu Allen S Fabrication of dual work-function metal gate structure for complementary field effect transistors

Also Published As

Publication number Publication date
CN101312158A (zh) 2008-11-26
US20080290416A1 (en) 2008-11-27
TW200847293A (en) 2008-12-01
US20150011059A1 (en) 2015-01-08
TWI405269B (zh) 2013-08-11

Similar Documents

Publication Publication Date Title
CN101312158B (zh) 互补式金氧半导体元件及其制造方法
CN1828937B (zh) 单一金属闸极互补式金氧半导体元件
Auth et al. 45nm high-k+ metal gate strain-enhanced transistors
DE102005063582B3 (de) Verfahren zum Herstellen eines Halbleiterbauelements
US9419099B2 (en) Method of fabricating spacers in a strained semiconductor device
CN101421839B (zh) 使用金属/金属氮化物双层结构作为自对准强按比例缩放cmos器件中的栅电极
TWI476822B (zh) 金屬高介電常數場效電晶體之雙金屬與雙介電質整合
KR101938533B1 (ko) 반도체 디바이스를 형성하는 방법
US8410555B2 (en) CMOSFET device with controlled threshold voltage and method of fabricating the same
US9000533B2 (en) Device and methods for high-K and metal gate stacks
US8969916B2 (en) Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode
US8574981B2 (en) Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same
JP4220509B2 (ja) 半導体装置の製造方法
DE112006001809T5 (de) CMOS-Transistoren mit doppeltem Gate-Dielektrikum mit hohem k und Verfahren zur Herstellung derselben
CN102456720A (zh) 高k金属栅极半导体晶体管的结构
JP2010129880A (ja) 半導体装置及びその製造方法
US20130119405A1 (en) Semiconductor device with enhanced strain
CN104347411A (zh) 金属栅电极等效功函数调节方法
CN103178012A (zh) 具有金属栅极的cmos器件及其形成方法
CN107293488A (zh) 半导体结构及其制造方法
US9209089B2 (en) Method of fabricating a metal gate semiconductor device
JP5086665B2 (ja) 半導体装置およびその製造方法
JP2006278376A (ja) 半導体装置およびその製造方法
CN101740570A (zh) 互补型金属氧化物半导体晶体管器件及其制作方法
CN109390397A (zh) 半导体元件及其制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant