CN101288159B - 具有多晶硅电极的半导体器件 - Google Patents

具有多晶硅电极的半导体器件 Download PDF

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CN101288159B
CN101288159B CN2006800213073A CN200680021307A CN101288159B CN 101288159 B CN101288159 B CN 101288159B CN 2006800213073 A CN2006800213073 A CN 2006800213073A CN 200680021307 A CN200680021307 A CN 200680021307A CN 101288159 B CN101288159 B CN 101288159B
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polysilicon
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巴特罗米杰·J·帕夫拉克
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Imec Corp
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Abstract

一种制造例如MOS晶体管的半导体器件的方法。所述器件包括在半导体基片(12)中形成的多晶硅栅极(10)和掺杂区(22，24)，它们通过一个沟道区(26)分隔开。所述半导体基片的暴露表面例如通过离子轰击被非结晶化，以便在加温退火期间禁止掺杂剂离子的随后扩散。低热预算对于所述激活和多晶硅再生长是有利的，以便确保用于所述源极/漏极区域的突变掺杂分布图。因此所述栅电极的上部(10b)保持非晶态。所述栅电极的上部被除去以便允许与所述多晶硅下部(10a)产生低电阻接触。

Description

具有多晶硅电极的半导体器件
技术领域
本发明涉及一种制造具有经过非结晶和再结晶处理的多晶硅电极的半导体器件的方法。具体地说，但不是唯一地，本发明涉及一种制造具有多晶硅栅电极的MOS晶体管的方法。
背景技术
在半导体器件制造领域需要不断地减小器件尺寸。这种减小允许在一个给定尺寸的晶片上并入更多的器件。同样，也需要保持(如果不能改善)器件的性能。随着器件元件的尺寸被做得较小，某些不希望的电子效应将变得更加明显。
其中发生这种影响的器件的一个好例子是MOSFET。这里，由半导体沟道区分开的源极和漏极扩展区包括掺杂半导体晶片的各个掺杂部分。如果基片是N型掺杂的，则植入P型掺杂剂，例如硼。如果基片是p型掺杂的，则植入N型掺杂剂，例如磷或者砷。因此，提供一个p-n结，其为在所述源极和漏极区之间流动的电流产生一个势垒。施加在布置于沟道上面的绝缘栅电极上的电压控制所述势垒的高度，并因此控制流过所述沟道区的电流。
期望形成具有浅的但是突变的结分布的源极和漏极扩展区以便避免由相对较短的沟道区所引起的不利的电子效应。结典型地是通过将掺杂剂植入到半导体晶片或者基片中形成的。通过使用所述已经形成的栅极屏蔽所述沟道区来将掺杂剂植入到所述半导体晶片的顶面中。然后通过加热退火激活所述掺杂剂。随后对半导体的加热会使掺杂剂更深地扩散到所述半导体中，由此能够减小结分布的突变。这是一个公认的问题。
美国专利申请No.US-2004/0115889披露了一种能够在植入掺杂剂物质的前后执行的非结晶植入处理。植入物质(例如硅或者锗)会使所述半导体基片的上部区域变成非结晶的。继非结晶植入和n型或者p型掺杂植入之后，执行加热退火以激活所述掺杂剂并使所述非结晶区再结晶。
图1a表示在类似于在US-2004/0115889中披露的非结晶步骤期间的基片的高度示意剖面图。最初由多晶硅(polysilicon)组成的栅电极10通过栅极电介质14而与半导体基片12绝缘。如箭头100所示，所述半导体基片的暴露表面通过植入锗原子而被非结晶化。由所述植入的锗携带的能量用于瓦解靠近所述多晶硅表面的规则结晶栅格，由此产生一个非结晶区。然后将N型或者p型掺杂剂离子植入(未示)到所述基片的非结晶区域中。
执行加热退火以驱动所述非结晶区域的固相外延再生长并连同激活所述掺杂剂。这种非结晶和再生长处理已经被示出用于提供出色的掺杂剂激活水平和突变结分布。参照图1b，所述激活的源极和漏极扩展22、24被与所述栅极10的边缘对齐并由所述无掺杂的沟道区26分离开。所述非结晶用于产生一个非结晶/结晶边界，其禁止掺杂剂离子的扩散，由此有助于突变结形成。
与在掺杂剂激活之前执行非结晶植入相关的问题是所述多晶硅栅极的至少一部分也变成非结晶的。使栅极再结晶所需的热预算大大高于块状半导体所需的热预算。当使用低温预算时，这将导致栅极的局部再结晶。如图1b中举例说明的，栅极10a的下部被成功地再生长，而上部10b保持非结晶态。
图2为表示继锗的预先非结晶植入(PAI)和1分钟的加热退火(再生长)之后的多晶硅栅极的电阻率值的试验结果的曲线图。由菱形表示的‘D02’图表示未经过PAI的栅极电阻。能够看出用于具有较高能量的锗的PAI的曲线图示出了在较低热预算下的极大增加的电阻。
图3表示经历了锗的PAI和在680℃下加热退火一分钟的栅极的截面X-TEM图。这在图2中由高亮显示为‘X’的数据点表示。在图2中由所述箭头指示的所述栅极的上部仍然是非结晶的。该栅极的相对较高的电阻和所导致的较差器件性能归因于该非结晶部分。
在大约780℃以上的热预算下，所述栅极变成完全再结晶，并且因此具有较低的、更加有利的电阻。然而，在这些高温下，所述源极和漏极结开始减活，这是由掺杂剂的增加扩散所引起的。因此，不存在栅极能够被完全地再结晶并且所述结能够被保持充足地突变的工艺窗口(process window)。
发明内容
本发明的一个目的是提供一种制造半导体器件的改进方法。
本发明的另一个目的是提供一种制造包括被完全地再结晶的栅极和被保持充足突变的结的半导体器件的方法。
根据本发明，提供一种制造半导体器件的方法，所述方法包括下述步骤：在半导体基片上形成多晶硅的栅电极，使所述半导体基片和栅电极的暴露表面非结晶化，对邻接所述栅电极的半导体基片的区域进行掺杂，然后，使所述栅电极和所述半导体基片的一部分进行再结晶，和除去所述栅电极的上部。通过在所述再结晶步骤之后除去所述栅电极的上部，对于处理温度的选择自由度得以提高。可自由使用低热预算以确保期望的结分布被保持，同时栅电极的再结晶程度并不紧要。所述栅电极中的任何剩余非晶硅被方便地除去以确保能与其进行低电阻接触。
术语‘非结晶化’意味着将材料的基本上结晶区转换成基本上非结晶区的任何处理。相关术语，例如‘非结晶’和‘非结晶的’之后将采用取自上述定义的含义。
除去栅电极的上部非结晶部分可例如通过对所述电极的最上端暴露表面进行抛光或者蚀刻来执行。这些处理每个都很简单，并且不需要除了在CMOS或者高级CMOS生产线中已有设备以外的额外设备。
所述栅电极的大约20-50nm的最上端表面被除去，即使这将取决于硅栅极的再生长程度。如上述，随后除去栅电极的非结晶部分将允许利用低温。例如，非结晶化区域的固相外延再生长是通过将所述基片加热至600℃-750℃范围内的温度而执行的。加热的持续时间将取决于采用的温度。
除去栅电极的高电阻部分允许与其产生低电阻接触。这种接触可以通过在所述栅电极上形成硅化物接触区被进一步增强。优选的，其是如下实现的：即在所述除去步骤之后在所述栅电极之上沉淀金属层、然后加热所述基片以便在所述栅电极上形成硅化物接触区。
在一个优选实施例中，根据本发明制造的半导体器件被并入到一个集成电路芯片中。这可使用建造好的CMOS或者高级CMOS处理工厂来制造。
附图说明
现在将参考附图仅以实例的方式说明本发明的实施例，其中：
图1表示在已知制造工艺的两个阶段中的贯穿MOS晶体管的栅极和沟道区的高度示意剖面图；
图2为表示已经以变化的热预算被非结晶化和再生长的栅极电阻的曲线图，所述结果是从实验得到的；
图3为已经在680℃被非结晶化和再生长一分钟的栅极的X-TEM图像；和
图4表示贯穿借助根据本发明的方法制造的MOS晶体管的栅极和沟道区的示意剖面图。
应该意识到所述附图仅仅是示意图。相同的参考数字通篇用于表示相同或者相似的部分。
具体实施方式
本发明提供一种制造具有低电阻多晶硅栅极的MOS晶体管同时适应形成浅的、突变结所需的非结晶和低温再生长处理的简单方法。图1和4现在将被用于说明根据本发明的方法的一个示例实施例。
参考图1a，一个介电层被沉积在硅基片12上。例如，所述介电层可由二氧化硅或者四氮化三硅组成。然后在所述基片上沉积一个厚约100nm的多晶硅层10。
栅极介电层14和多晶硅层10的沉淀是使用已知的沉积技术(例如外延生长、化学汽相淀积(CVD)或者原子层沉积(ALD))执行的。
然后使用标准平版印刷技术模制所述多晶硅层和所述介电层以便在所述硅基片12上提供具有多晶硅栅电极10的栅极叠层，所述多晶硅栅电极10通过一个栅极电介质14与所述硅基片12分离开。例如，可利用光致抗蚀剂来屏蔽基片上与将要形成隔离栅极叠层的期望位置相对应的多个区域。然后可使用蚀刻步骤来除去多晶硅层10和介电层14的多余区域。然后在基片上除去所述光致抗蚀剂以保留隔离栅叠层。应该意识到在一个典型的集成电路器件中，在单个晶片上将形成许多分离的栅极叠层。然而，为了保持说明本发明的简单性，将只说明关于单个栅极叠层(如图1a所示)的方法。
然后如箭头100所示，执行锗植入来使所述硅基片和所述栅电极10的暴露表面非结晶化。所述植入是用5e14至1e15at/cm3的剂量以8至30kev的能量执行的。在最高表面上的原子轰击动作使所述结晶结构瓦解，由此提供有限深度的非晶硅。该非结晶化用于限制随后掺杂剂离子扩散到所述硅晶片12的深度，由此提供期望的浅源极/漏极区域。
眼下，可形成邻接所述栅电极的绝缘隔离片(没有示出)以在随后的p型掺杂处理中屏蔽下面基片的各个区域。
再次参考图1b，以0.2-10keV、5e14和5e15at/cm3之间的剂量植入硼离子。该硼植入用于对与所述栅电极10邻接的硅基片的区域22、24进行掺杂。所述掺杂区域最终将用作p型掺杂导电源极和漏极区。在另一个实施例中，相反地通过在所述基片的区域中植入N型磷离子而可以提供N型半导体器件。
然后执行低温退火以激活所述器件的非结晶部分22、24(包括栅电极的一部分)的固相外延再生长。除了对所述栅电极的10a部分和所述半导体基片22、24进行再结晶之外，所述退火还用于激活所述植入的硼掺杂剂。
在600-750℃之间(典型地为650℃)的保持一分钟的热预算被用于执行这种退火。设想对于一个短期间使用较高的温度，只要不超出所述温度便可以破坏所述突变结分布。参考图1b，由此提供再结晶源极和漏极区22和24并通过所述无掺杂的沟道区26将二者分离开。此外，加热退火会使栅极10的硅再结晶至一个程度以便形成多晶硅下部10a和非晶硅上部10b。
根据本发明的一个优选实施例，然后通过对其最上端暴露表面进行抛光以除去栅电极的上部10b。可以利用化学机械抛光(CMP)。CMP用于从所述栅极10的最上端表面除去顶部20-50nm。然而，设想除去部分的厚度取决于所述栅极在所述固相外延再生长期间被再结晶的程度。有利地，所述抛光将基本上除去所述栅极的全部非结晶高电阻区域，由此允许形成低电阻接触。由于CMP处理的性质，抛光的程度在所述晶片上会有+/-20nm的变动。
在另一个优选实施例中，通过有选择的蚀刻来除去所述多晶硅栅极的非结晶部分。在此情况中，例如可使用基于HF的酸来执行湿式蚀刻以除去所述栅电极的非晶硅部分10b。有利地，只有栅极的高电阻部分被除去。
在另一个实施例中，使用等离子(干式)蚀刻除去所述栅电极的上部10b。
图4表示除去顶端部分10b之后的栅极叠层。
然后使用标准沉积技术在所述栅电极上面沉积厚度为20-40nm的镍层(没有示出)。然后加热所述基片以便将所述镍和下面的多晶硅的一部分转变成硅化物接触区。所述硅化物有利地提供与所述器件的均匀低电阻接触。然后例如使用湿式蚀刻除去任何无用的镍。虽然在本实施例中使用了镍，但也可设想使用适合于形成硅化物的其它金属来代替。
然后执行基片的进一步前端处理以对所述半导体器件提供触点，其然后可在一个集成电路芯片内部继续形成一个元件。然而，将不说明进一步的处理，因为它与本发明并不直接相关。
概括地说，提供一种制造半导体器件(例如MOS晶体管)的方法。所述器件包括多晶硅栅极和在半导体基片中形成的掺杂区域，它们由一个沟道区分开。所述半导体基片的暴露表面例如通过离子轰击被非结晶化，以便在加温退火期间禁止掺杂剂离子的随后扩散。低热预算对于所述激活和多晶硅再生长是有利的，以便确保用于所述源极/漏极区域的突变掺杂分布图。因此栅电极的上部保持非结晶。所述栅电极的上部被除去以便允许与所述多晶硅下部产生低电阻接触。
通过读取本公开，其它变化和修改对于本领域技术人员将是显而易见的。这种变化和修改可包括在半导体的设计、制造和使用中已知的和除了此处所述的特征之外或者代替所述特征使用的等同物和其它特征。虽然在本申请中已经将权利要求表达为特征的特定组合，但应该理解所述公开的范围还包括文中或明示或暗示或者概括得出的任何新颖的特征及其组合，而不论它是否会缓和本发明所处理的任何或者全部相同技术问题。本申请人在此声明，在本申请或者源自本申请的进一步申请的受理期间，可以根据任意此类特征和/或其组合而构成新的权利要求。

Claims (8)

1.一种制造半导体器件的方法，所述包括步骤：
在半导体基片(12)上形成多晶硅的栅电极(10)；
使所述半导体基片和栅电极的暴露表面非结晶化；
对邻接所述栅电极的半导体基片的区域(22，24)进行掺杂；然后
使所述栅电极和所述半导体基片的下部(10a)进行再结晶；和
除去所述栅电极的上部非结晶部分(10b)。
2.根据权利要求1所述的方法，其中所述除去步骤包括对所述栅电极的最上端的暴露表面进行抛光。
3.根据权利要求1所述的方法，其中所述除去步骤包括对所述栅电极的最上端的暴露表面进行蚀刻。
4.根据任何一个前述权利要求所述的方法，其中所述除去步骤用于从所述电极的最上端表面除去具有20-50nm的厚度的层。
5.根据任何一个前述权利要求所述的方法，其中所述再结晶步骤包括固相外延再生长。
6.根据权利要求5所述的方法，其中所述再生长是通过将所述基片加热至600℃-750℃范围内的温度而执行的。
7.根据任何一个前述权利要求所述的方法，还包括步骤：
在所述除去步骤之后在所述栅电极之上沉淀金属层；以及然后加热所述基片以便在所述栅电极上形成硅化物接触区。
8.一种集成电路芯片，其包括根据任何一个前述权利要求制造的半导体器件。
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