CN101281874B - 封装结构及其制造方法 - Google Patents
封装结构及其制造方法 Download PDFInfo
- Publication number
- CN101281874B CN101281874B CN2008100998474A CN200810099847A CN101281874B CN 101281874 B CN101281874 B CN 101281874B CN 2008100998474 A CN2008100998474 A CN 2008100998474A CN 200810099847 A CN200810099847 A CN 200810099847A CN 101281874 B CN101281874 B CN 101281874B
- Authority
- CN
- China
- Prior art keywords
- crystal grain
- adhesive material
- carrying platform
- carrier
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000005538 encapsulation Methods 0.000 title abstract description 37
- 239000013078 crystal Substances 0.000 claims abstract description 78
- 239000000463 material Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 41
- 239000000853 adhesive Substances 0.000 claims description 46
- 230000001070 adhesive effect Effects 0.000 claims description 46
- 239000002184 metal Substances 0.000 claims description 22
- 229910000679 solder Inorganic materials 0.000 claims description 18
- 238000003860 storage Methods 0.000 claims description 14
- 238000009736 wetting Methods 0.000 claims description 13
- 239000000843 powder Substances 0.000 claims description 10
- 238000012545 processing Methods 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000004907 flux Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 5
- 238000005520 cutting process Methods 0.000 abstract description 2
- 238000002360 preparation method Methods 0.000 abstract 3
- 239000012945 sealing adhesive Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
本发明是关于一种晶粒自动对位的封装结构及其制造方法,以及堆栈式封装结构及其制造方法,该晶粒自动对位的封装结构的制造方法,包括:(a)提供一载体,该载体具有数个承载平台;(b)提供数个晶粒,且分别将所述晶粒置放于所述承载平台上;(c)进行回焊制程,使得所述晶粒对齐于所述承载平台;(d)形成一封胶材料于所述晶粒间的间隙;及(e)进行切割制程,以形成数个封装结构。藉此,所述晶粒在回焊过程中会有自动对齐的效果,因此晶粒附着机的精度要求不高。
Description
技术领域
本发明是关于一种封装结构及其制造方法,详言之,是关于一种晶粒自动对位的封装结构及其制造方法,以及堆栈式封装结构及其制造方法。
背景技术
传统堆栈式封装结构的制造方法是先于晶片上形成数个晶粒单元,再将二片以上的晶片堆栈在一起,之后再进行切割,以形成数个堆栈式封装结构。此种传统方法的缺点为,该晶片上的晶粒单元皆未经过测试,因此,所形成的所述堆栈式封装结构中会有不良率的问题。尤其如果堆栈越多片晶片,则不良率会越高。
为了改善上述缺点,另一种传统方法是先将该晶片上的晶粒单元切割下来,经过测试后再进行堆栈。此种方式的缺点为,所述晶粒单元在堆栈时会有不易对准的问题,使得上下的二个晶粒单元间会有偏移。
因此,有必要提供一种创新且具进步性的晶粒自动对位的封装结构及其制造方法,以及堆栈式封装结构及其制造方法,以解决上述问题。
发明内容
本发明的主要目的在于提供一种晶粒自动对位的封装结构的制造方法,包括:(a)提供一载体(Carrier),该载体具有数个承载平台;(b)提供数个晶粒,且分别将所述晶粒置放于所述承载平台上;(c)进行回焊制程,使得所述晶粒对齐于所述承载平台;(d)形成一封胶材料于所述晶粒间的间隙;及(e)进行切割制程,以形成数个封装结构。藉此,所述晶粒在回焊过程中会有自动对齐的效果,因此晶粒附着机(Die Attach Machine)的精度要求不高。亦即,仅需低精度的晶粒附着机即可达到高精度的定位,因而可以减少设备成本。
本发明的另一目的在于提供一种堆栈式封装结构的制造方法,包括:(a)提供一第一载体,该第一载体具有数个第一承载平台;(b)提供数个第一晶粒,每一第一晶粒具有至少一个第一穿导孔,分别将所述第一晶粒置放于所述第一承载平台上;(c)进行回焊制程,使得所述第一晶粒对齐于所述第一承载平台;(d)形成一第一封胶材料于所述第一晶粒间的间隙;(e)移除该第一载体,以暴露出该第一穿导孔,且该第一封胶材料具有一第一表面及一第二表面;(f)分别形成一第一上电路层及一第一下电路层于该第一封胶材料的第二表面及第一表面,该第一上电路层是利用该第一穿导孔电性连接至该第一下电路层,以形成一第一封装单元;(g)提供一第二封装单元;及(h)堆栈该第一封装单元及该第二封装单元;及(i)进行切割制程,以形成数个堆栈式封装结构。
附图说明
图1至图10显示本发明晶粒自动对位的封装结构的制造方法的示意图;及
图11至图23显示本发明堆栈式封装结构的制造方法的示意图。
具体实施方式
参考图1至图10,显示本发明晶粒自动对位的封装结构的制造方法的示意图。首先,参考图1,提供一载体(Carrier)1,该载体1具有数个承载平台10。在本实施例中,该载体1为一硅晶片,且每一该承载平台10包含一焊料层11及一金属垫块12,该金属垫块12是位于该焊料层11及该载体1之间。较佳地,所述金属垫块12的材质为金属。
接着,参考图2,形成一助焊剂(Flux)13于所述承载平台10及该载体1上。
接着,参考图3,提供数个晶粒2,且分别将所述晶粒2置放于所述承载平台10上,亦即位于该助焊剂13上。在本实施例中,所述晶粒2为测试合格的晶粒。每一晶粒2包括一第一表面21及一第二表面22。该第二表面22是朝向所述承载平台10,该第二表面22更包括一润湿层(Wettable layer)23。该第一表面21更包括数个球垫(Ball pad)24。
接着,参考图4,进行回焊制程,使得所述晶粒2自动对齐于所述承载平台10。这是由于该焊料层11在回焊过程中的表面张力使得位于其上的晶粒2会有自动对齐的效果。
接着,参考图5,移除该助焊剂13。接着,参考图6,形成一封胶材料14于所述晶粒2间的间隙,且显露出所述球垫24。较佳地,在另一实施例中,该载体1更具有数个沟槽15,位于所述承载平台10之间。而该封胶材料14会填入所述沟槽15,以增加该封胶材料14与该载体1间的结合力,如图7所示。
接着,参考图8,形成一电路层16于该封胶材料14上,该电路层16电性连接所述晶粒2。在本实施例中,该电路层16包括一重布线层161,该重布线层161是连接所述球垫24。较佳地,数个焊球(Solder Ball)17更形成于该电路层16上,所述焊球17是连接该重布线层161,进而电性连接所述球垫24。
接着,参考图9,移除该载体1。最后,参考图10,进行切割制程,以形成数个封装结构3。要注意的是,在本实施例中,也可以不移除该载体1而直接进行切割制程,如此所述封装结构3则会包括该载体1。
在本实施例中,所述金属垫块12是利用黄光制程而形成于该载体1,且该焊料层11是利用电镀方式形成于所述金属垫块12,因此其定位十分准确。此外,所述晶粒4在回焊过程中会有自动对齐的效果,因此晶粒附着机(Die Attach Machine)的精度要求不高。亦即,在本实施例中,仅需低精度的晶粒附着机即可达到高精度的定位,因而可以减少设备成本。
再参考图10,显示本发明的封装结构的示意图。该封装结构3包括一封胶材料14、一承载平台10、一晶粒2、一润湿层23及一电路层16。
该封胶材料14具有一第一表面141、一第二表面142及一容置槽143,该容置槽143是贯穿该封胶材料14。该承载平台10是位于该容置槽143内且暴露于该封胶材料14的第二表面142。在本实施例中,该承载平台10包含一焊料层11及一金属垫块12,该焊料层11是位于该金属垫块12及该润湿层23之间,该金属垫块12的材质为金属。
该晶粒2是位于该容置槽143内,该晶粒2具有一第一表面21及一第二表面22,该第一表面21是暴露于该封胶材料14的第一表面141。较佳地,该晶粒2的第一表面21更包括数个球垫24。
该润湿层23是位于该晶粒2的第二表面22,且连接该承载平台10的该焊料层11。该电路层16是位于该封胶材料14的第一表面141上,且该电路层16电性连接该晶粒2的第一表面21。在本实施例中,该电路层16是包括一重布线层161,该重布线层161是连接所述球垫24。较佳地,该电路层16上更包括数个焊球17,所述焊球17是连接该重布线层161,进而电性连接所述球垫24。在另一实施例中,该封装结构3更包括一载体(图中未示),位于该封胶材料14的第二表面142。
参考图11至图23,显示本发明堆栈式封装结构的制造方法的示意图。首先,参考图11,提供一第一载体4,该第一载体4具有数个第一承载平台40。在本实施例中,该第一载体4为一硅晶片,且每一该第一承载平台40包含一第一焊料层41及一第一金属垫块42,该第一金属垫块42是位于该第一焊料层41及该第一载体4之间。
接着,参考图12,形成一第一助焊剂43于所述第一承载平台40及该第一载体4上。
接着,参考图13,提供数个第一晶粒5,且分别将所述第一晶粒5置放于所述第一承载平台40上,亦即位于该第一助焊剂43上。在本实施例中,所述第一晶粒5为测试合格的晶粒。每一第一晶粒5包括一第一表面51、一第二表面52及至少一第一穿导孔(Via)55。该第二表面52是朝向所述第一承载平台40,该第二表面52更包括一第一润湿层53。该第一表面51更包括数个第一球垫54。该第一穿导孔55内含一导电金属,其材质可以和该第一润湿层53相同或不同。
接着,参考图14,进行回焊制程,使得所述第一晶粒5自动对齐于所述第一承载平台40。接着,移除该第一助焊剂43。
接着,参考图15,形成一第一封胶材料44于所述第一晶粒5间的间隙,且显露出所述第一球垫54。
接着,参考图16,移除该第一载体4、部分该第一封胶材料44、该第一焊料层41、该第一金属垫块42及该第一润湿层53,以暴露出该第一穿导孔55,且该第一封胶材料44具有一第一表面441及一第二表面442。
接着,参考图17,分别形成一第一上电路层46及一第一下电路层47于该第一封胶材料44的第二表面442及第一表面441。该第一上电路层46是利用所述第一穿导孔55及所述第一球垫54电性连接至该第一下电路层47,以形成一第一封装单元6A。在本实施例中,该第一上电路层46包括一第一上重布线层461,该第一下电路层47包括一第一下重布线层471。较佳地,数个第一焊球48更形成于该第一下电路层47上,所述第一焊球48是连接该第一下重布线层471。
接着,提供一第二封装单元。该第二封装单元可以是任何型式的封装体。在本实施例中,该第二封装单元与该第一封装单元6A大致相同,其制造方法如下。
首先,参考图18,提供一第二载体7,该第二载体7具有数个第二承载平台70。在本实施例中,该第二载体7为一硅晶片,且每一该第二承载平台70包含一第二焊料层71及一第二金属垫块72,该第二金属垫块72是位于该第二焊料层71及该第二载体7之间。
接着,形成一第二助焊剂(图中未示)于所述第二承载平台70及该第二载体7上。
接着,参考图19,提供数个第二晶粒8,且分别将所述第二晶粒8置放于所述第二承载平台70上,亦即位于该第二助焊剂上。所述第二晶粒8的功能或尺寸是相同或不同于所述第一晶粒5。在本实施例中,所述第二晶粒8为测试合格的晶粒。每一第二晶粒8包括一第一表面81、一第二表面82及至少一第二穿导孔85。该第二表面82是朝向所述第二承载平台70,该第二表面82更包括一第二润湿层83。该第一表面81更包括数个第二球垫84。该第二穿导孔85内含一导电金属,其材质可以和该第二润湿层83相同或不同。接着,进行回焊制程,使得所述第二晶粒8自动对齐于所述第二承载平台70。接着,移除该第二助焊剂。
接着,参考图20,形成一第二封胶材料74于所述第二晶粒8间的间隙,且显露出所述第二球垫84。接着,移除该第二载体7、部分该第二封胶材料74、该第二焊料层71、该第二金属垫块72及该第二润湿层83,以暴露出该第二穿导孔85,且该第二封胶材料74具有一第一表面741及一第二表面742。
接着,参考图21,分别形成一第二上电路层76及一第二下电路层77于该第二封胶材料74的第二表面742及第一表面741。该第二上电路层76是利用所述第二穿导孔85及所述第二球垫84电性连接至该第二下电路层77,以形成一第二封装单元6B。在本实施例中,该第二上电路层76包括一第二上重布线层761,该第二下电路层77包括一第二下重布线层771。较佳地,数个第二焊球78更形成于该第二下电路层77上,所述第二焊球78是连接该第二下重布线层771。
接着,参考图22,堆栈该第一封装单元6A及该第二封装单元6B。可以理解的是,该第二封装单元6B的上还可以再堆栈其它封装单元。接着,参考图23,进行切割制程,以形成数个堆栈式封装结构9。
再参考图23,显示本发明的堆栈式封装结构的示意图。该堆栈式封装结构9包括一第一封装单元6A及一第二封装单元6B。
该第一封装单元6A包括一第一封胶材料44、一第一晶粒5、一第一上电路层46及一第一下电路层47。
该第一封胶材料44具有一第一表面441、一第二表面442及一第一容置槽443,该第一容置槽443是贯穿该第一封胶材料44。该第一晶粒5是位于该第一容置槽443内,该第一晶粒5具有一第一表面51、一第二表面52及至少一第一穿导孔55。该第一表面51是暴露于该第一封胶材料44的第一表面441,该第二表面52是暴露于该第一封胶材料44的第二表面442。较佳地,该第一晶粒5的第一表面51更包括数个第一球垫54。
该第一上电路层46是位于该第一封胶材料44的第二表面442上。该第一下电路层47是位于该第一封胶材料44的第一表面441上。该第一上电路层46是利用该第一穿导孔55电性连接至该第一下电路层47。较佳地,该第一下电路层47更包括数个第一焊球48。
该第二封装单元6B是堆栈于该第一封装单元6A上,且电性连接至该第一上电路层46。
该第二封装单元6B包括一第二封胶材料74、一第二晶粒8、一第二上电路层76及一第二下电路层77。
该第二封胶材料74具有一第一表面741、一第二表面742及一第二容置槽743,该第二容置槽743是贯穿该第二封胶材料74。该第二晶粒8的功能或尺寸是相同或不同于该第一晶粒5。该第二晶粒8是位于该第二容置槽743内,该第二晶粒8具有一第一表面81、一第二表面82及至少一第二穿导孔85。该第一表面81是暴露于该第二封胶材料84的第一表面841,该第二表面82是暴露于该第二封胶材料84的第二表面842。较佳地,该第二晶粒8的第一表面81更包括数个第二球垫84。
该第一上电路层46是位于该第一封胶材料44的第二表面442上。该第一下电路层47是位于该第一封胶材料44的第一表面441上。该第一上电路层46是利用该第一穿导孔55电性连接至该第一下电路层47。较佳地,该第二下电路层77更包括数个第二焊球78。该第二下电路层77是利用所述第二焊球78电性连接该第一上电路层46。
在本实施例中,因是以测试合格的晶粒做堆栈,而且可以准确对位,因此可以提高良率。此外,本实施例可以堆栈不同尺寸的晶粒,增加设计弹性。
惟上述实施例仅为说明本发明的原理及其功效,而非用以限制本发明。因此,习于此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。本发明的权利范围应如所述的权利要求所列。
Claims (12)
1.一种晶粒自动对位的封装结构的制造方法,包括:
(a)提供一载体(Carrier),该载体具有数个承载平台;
(b)提供数个晶粒,且分别将所述晶粒置放于所述承载平台上;
(c)进行回焊制程,使得所述晶粒对齐于所述承载平台;
(d)形成一封胶材料于所述晶粒间的间隙;及
(e)进行切割制程,以形成数个封装结构,
其中该步骤(a)中该承载平台包含数个焊料层。
2.如权利要求1的制造方法,其中该步骤(a)中,该载体为一硅晶片。
3.如权利要求1的制造方法,其中该步骤(a)中,每一该承载平台包含一焊料层及一金属垫块,且该金属垫块是位于该焊料层及该载体之间。
4.如权利要求1的制造方法,其中该步骤(a)之后且步骤(b)之前更包括一形成一助焊剂(Flux)于所述承载平台上的步骤。
5.如权利要求1的制造方法,其中该步骤(b)中,每一晶粒包括一第一表面及一第二表面,该第二表面是朝向所述承载平台,该第二表面更包括一润湿层(Wettable layer),而该第一表面更包括数个球垫(Ball pad)。
6.如权利要求1的制造方法,其中该载体更具有数个沟槽,位于所述承载平台之间,该步骤(d)中该封胶材料更形成于所述沟槽内。
7.如权利要求1的制造方法,其中该步骤(d)之后且步骤(e)之前更包括一移除该载体的步骤。
8.如权利要求1的制造方法,其中该步骤(d)之后且步骤(e)之前更包括一形成一电路层于该封胶材料上的步骤,该电路层电性连接所述晶粒。
9.一种封装结构,包括:
封胶材料,具有第一表面、第二表面及容置槽,该容置槽是贯穿该封胶材料;
承载平台,位于该容置槽内且暴露于该封胶材料的第二表面;
晶粒,位于该容置槽内,该晶粒具有第一表面及第二表面,该第一表面是暴露于该封胶材料的第一表面,其中该晶粒的第一表面更包括数个球垫(Ball pad);
润湿层,位于该晶粒的第二表面,且连接该承载平台;及
电路层,位于该封胶材料的第一表面上,且该电路层电性连接该晶粒的第一表面,
其中所述晶粒经一回焊制程对齐于所述承载平台。
10.如权利要求9的封装结构,更包括一载体,位于该封胶材料的第二表面。
11.如权利要求9的封装结构,其中该承载平台包含一焊料层及一金属垫块,且该焊料层是位于该金属垫块及该润湿层之间。
12.如权利要求9的封装结构,更包括数个焊球,位于该电路层上。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2008100998474A CN101281874B (zh) | 2008-05-26 | 2008-05-26 | 封装结构及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2008100998474A CN101281874B (zh) | 2008-05-26 | 2008-05-26 | 封装结构及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101281874A CN101281874A (zh) | 2008-10-08 |
CN101281874B true CN101281874B (zh) | 2010-06-02 |
Family
ID=40014264
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008100998474A Active CN101281874B (zh) | 2008-05-26 | 2008-05-26 | 封装结构及其制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101281874B (zh) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101086971A (zh) * | 2006-06-06 | 2007-12-12 | 日月光半导体制造股份有限公司 | 覆晶式集成电路构装方法 |
-
2008
- 2008-05-26 CN CN2008100998474A patent/CN101281874B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101086971A (zh) * | 2006-06-06 | 2007-12-12 | 日月光半导体制造股份有限公司 | 覆晶式集成电路构装方法 |
Non-Patent Citations (1)
Title |
---|
JP特开2005-322774A 2005.11.17 |
Also Published As
Publication number | Publication date |
---|---|
CN101281874A (zh) | 2008-10-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI418001B (zh) | 半導體封裝結構及其製造方法 | |
US20190265273A1 (en) | 3d chip testing through micro-c4 interface | |
US7683459B2 (en) | Bonding method for through-silicon-via based 3D wafer stacking | |
CN103325703B (zh) | 在封装件形成期间探测芯片 | |
CN106233462B (zh) | 半导体器件以及半导体器件的制造方法 | |
US7811858B2 (en) | Package and the method for making the same, and a stacked package | |
CN108695284A (zh) | 包括纵向集成半导体封装体组的半导体设备 | |
CN102263070A (zh) | 一种基于基板封装的wlcsp封装件 | |
US9040350B2 (en) | Packaging and function tests for package-on-package and system-in-package structures | |
US20020017709A1 (en) | Assembly jig and manufacturing method of multilayer semiconductor device | |
CN103579171B (zh) | 半导体封装件及其制造方法 | |
JP2017005187A (ja) | 半導体装置の製造方法、および半導体装置 | |
CN102163591A (zh) | 一种球型光栅阵列ic芯片封装件及其生产方法 | |
US9918388B2 (en) | Circuit substrate, method of manufacturing circuit substrate, and electronic component | |
CN101281875B (zh) | 堆栈式封装结构及其制造方法 | |
CN105895605A (zh) | 一种薄芯片贴装基板扇出型封装结构及其制造方法 | |
CN102842558A (zh) | 一种基于锡膏层的wlcsp多芯片堆叠式封装件及其封装方法 | |
CN101281874B (zh) | 封装结构及其制造方法 | |
CN102842560A (zh) | 一种wlcsp多芯片堆叠式封装件及其封装方法 | |
CN102842551A (zh) | 一种基于基板、锡膏层的wlcsp多芯片堆叠式封装件及其封装方法 | |
CN103208467A (zh) | 内嵌封装体的封装模块及其制造方法 | |
TW201803064A (zh) | 用於高密度互連架構之表面修整層 | |
US7371607B2 (en) | Method of manufacturing semiconductor device and method of manufacturing electronic device | |
TWI376777B (en) | Stacked, interconnected semiconductor packages and method of stacking and interconnecting semiconductor packages | |
KR101546591B1 (ko) | 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |