CN101276782B - Method for manufacturing fin transistor that prevents etching loss of a spin-on-glass insulation layer - Google Patents
Method for manufacturing fin transistor that prevents etching loss of a spin-on-glass insulation layer Download PDFInfo
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- CN101276782B CN101276782B CN2008100804750A CN200810080475A CN101276782B CN 101276782 B CN101276782 B CN 101276782B CN 2008100804750 A CN2008100804750 A CN 2008100804750A CN 200810080475 A CN200810080475 A CN 200810080475A CN 101276782 B CN101276782 B CN 101276782B
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- 238000009413 insulation Methods 0.000 title abstract 6
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
Abstract
A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer coming into contact with a gate forming region is etched so as to protrude the gate forming region in the active region. A protective layer over the semiconductor substrate is formed to fill the portion of the etched flowable insulation layer. The portion of the protective layer formed over the active region is removed to expose the active region of the semiconductor substrate. The exposed active region of the semiconductor substrate is cleaned. The protective layer remaining on the portion of the etched flowable insulation layer is removed. Gates are formed over the protruded gate forming regions in the active region.
Description
Technical field
The present invention relates to make the method for fin transistor, particularly, relate to the manufacture method of such fin transistor, in this fin transistor, prevented etching loss as spin-coating glass (spin-on-glass) layer of the material of field insulating layer.
Background technology
When the design rule of semiconductor device reduced, transistorized channel length and width correspondingly reduced.As a result, existing flat crystal tubular construction is realizing that minimum feature is less than limited aspect the required threshold voltage of the highly intergrated semiconductor device of 100nm.In order to address this problem, a kind of fin transistor has been proposed, wherein by increasing the increase that channel width can obtain the speed of service of drive current and requirement.
The fin transistor structure comprises an insulant, and it is etched to have the active region of bulge-structure with generation, and therefore transistorized live width increase is raised with the height of source region.The advantage of fin transistor comprises owing to having increased the drive current and the speed of service that channel width increases.
Yet along with the increase of semiconductor device integration density, the interval between the active region of fin transistor is filled (gap-fill) and is become difficult.Therefore, it is more useful than existing high-density plasma (HDP) insulating barrier as the interval packing material to have a spin-coating glass insulating barrier of preferable filling characteristic.
Yet, to compare with existing high-density plasma insulating barrier, the spin-coating glass insulating barrier has very high etching speed for wet solution.Therefore, shown in Figure 1A, when adopting wet etching to remove oxide layer 120, the big loss A of generation on the sidewall of the etched spin-coating glass insulating barrier 106 of institute.At this, oxide layer 120 is at least one in pad oxide (pad oxide), screen oxide (screen oxide) and the native oxide (native oxide), pad oxide is used to form groove in isolation technology, screen oxide is used for preventing damage in injection technology.
With reference to Figure 1A and 1B, the loss A of spin-coating glass insulating barrier 106 can cause short circuit (shortage) B between the neighboring gates 140 and grid 140 and the contact plunger that forms subsequently between short circuit.Loss A is the factor that reduces the reliability of semiconductor device, this be because it may cause short circuit B between the neighboring gates 140 and grid 140 and the contact plunger that forms subsequently between short circuit, shown in Figure 1B.
In addition, because the loss of spin-coating glass insulating barrier, distance between the territory, place may reduce, cause disturbing from the signal that passes through grid that is provided with in the spin-coating glass insulating barrier of filling in the insulant on the scene, promptly, at the semiconductor device run duration, increased the territory, place for the main grid that is arranged on the active region.Therefore, increase gate induced leakage (GIDL, gate induced drain leakage) electric current, reduced transistorized short circuit raceway groove surplus (short channel margin) thus.For example, in the DRAM device, data retention time shortens, and makes that normal operation is difficult, and has therefore reduced the productive rate and the reliability of device.
Summary of the invention
Embodiments of the invention relate to the method for making fin transistor, wherein can suppress the etching loss as the spin-coating glass insulating barrier of field insulating layer material.
In addition, embodiments of the invention relate to the method for making fin transistor, wherein by suppressing can to improve device performance and reliability as the etching loss of the spin-coating glass insulating barrier of field insulating layer material.
In one embodiment, the method that is used to make fin transistor can comprise: form groove by etching semiconductor; In groove, fill runny insulating barrier, be limited with the field insulating layer of source region with formation; Etching and grid form the part of the runny insulating barrier that the zone contacts, so that the projection grid forms the zone in active region; Be formed on the protective layer on the Semiconductor substrate, to fill this part of the etched insulating barrier that easily flows; Removal is formed on the protective layer on the active region, to expose the active area of semiconductor substrate territory; The active area of semiconductor substrate territory that cleaning exposes; Removal is retained in the protective layer on this part of the etched insulating barrier that easily flows; And the grid of projection forms and forms grid on the zone in active region.
In the step of the active region that cleaning exposes, Semiconductor substrate has and is formed on its lip-deep oxide layer.
Adopt etch back process to remove the step of the part that is formed on the protective layer on the active region.
Carry out the step of active region of the exposure of clean semiconductor substrate, be formed on oxide on the Semiconductor substrate with removal.
By adopting dilution HF solution or HF and NH
4The wet etching process of F mixed solution carries out the step of active region of the exposure of clean semiconductor substrate.
The insulating barrier that easily flows can comprise the spin-coating glass insulating barrier.
Any solution that employing is derived in hydrolysising polyethylene silazane, hydrolysis silsesquioxane, polymethyl siloxane, siloxanes and the silicate forms the spin-coating glass insulating barrier.
Protective layer can comprise carbon polymer.
Form protective layer and comprise employing spin-coating method coating carbon polymer layer; And cure coated carbon polymer layer.
Coating carbon polymer layer makes its this part of filling etched spin-coating glass insulating barrier, the scope of its thickness on the active area of semiconductor substrate territory be 200 to
The temperature range of curing is 150 to 400 ℃.
Removing the step of the protective layer that stays on the part of the etched insulating barrier that easily flows can finish by oxygen plasma etch technology.
The temperature range of carrying out the oxygen plasma etch process is 20 to 300 ℃.
Description of drawings
Figure 1A is the sectional view of diagram according to the loss of the spin-coating glass insulating barrier of prior art.
Figure 1B is the sectional view of diagram according to the short circuit of prior art between grid.
Fig. 2 is used to illustrate the plane graph of making the fin transistor method according to the embodiment of the invention.
Fig. 3 A to 3G is that X-X ' line cuts open the sectional view of getting in Fig. 2, and illustrates the processing step of making the fin transistor method according to the embodiment of the invention.
Fig. 4 A to 4G is that the Y-Y ' line in Fig. 2 cuts open the sectional view of getting, and illustrates the processing step of making the fin transistor method according to the embodiment of the invention.
Embodiment
The preferred embodiments of the present invention relate to the method for making fin transistor, and wherein carbon polymer (carbonpolymer) layer forms the protective layer above the spin-coating glass insulating barrier, and its thickness is etched, carry out wet etching process then to realize fin transistor.Equally; if when protective layer is formed on the spin-coating glass insulating barrier, carry out wet etching process; then can prevent the loss in the etched spin-coating glass insulating layer sidewalls; this is because protective layer is filled in spin-coating glass becomes attached in the etching part of layer, and has protected sidewall thus in follow-up wet etching process.
As mentioned above, in an embodiment of the present invention, though adopt the spin-coating glass insulating barrier as thin interval packing material, in the loss that can prevent during the wet etching process in the spin-coating glass insulating layer sidewalls.Like this, it can prevent from the short circuit that produces between the short circuit that produces between the neighboring gates and grid and the contact plunger from therefore to cause the production productive rate of semiconductor device and the improvement of reliability.
Hereinafter, method according to the manufacturing fin transistor of the embodiment of the invention is described with reference to the accompanying drawings.
Fig. 2,3A to 3G and 4A to 4G are used to illustrate the view of making the method for fin transistor according to the embodiment of the invention.Fig. 2 is used to illustrate the plane graph of making the fin transistor method according to the embodiment of the invention; Fig. 3 A to 3G is that X-X ' line cuts open the sectional view of getting in Fig. 2, and illustrates the processing step of making the fin transistor method according to the embodiment of the invention; And Fig. 4 A to 4B to be Y-Y ' line in Fig. 2 cut open the sectional view of getting, and illustrate the processing step of making the fin transistor method according to the embodiment of the invention.Omitted the detailed description of Fig. 2.In Fig. 2, label 200, A/R, F/R and G/R represent that respectively Semiconductor substrate, active region, territory, place and grid form the zone.
With reference to Fig. 3 A and 4A, prepared to provide the Semiconductor substrate 200 of territory, place F/R and active region A/R.Territory, place F/R and active region A/R comprise that grid forms regional G/R.Territory, the place F/R of etching semiconductor substrate 200 is to form groove.Then, sidewall oxide 202 is formed on the surface of groove.After forming sidewall oxide 202, the insulating barrier that easily flows is preferably spin-coating glass insulating barrier 206 and is formed on the whole surface that Semiconductor substrate 200 comprises sidewall oxide 202 with filling groove.Preferably, before forming spin-coating glass insulating barrier 206, linear nitride layer (not shown) and linear oxide skin(coating) (not shown) are formed on the whole surface that Semiconductor substrate 200 comprises sidewall oxide 202 successively.Spin-coating glass insulating barrier 206 by chemico-mechanical polishing forming field insulating layer 210, thereby active region A/R is limited among territory, the place F/R of Semiconductor substrate 200.
Spin-coating glass insulating barrier 206 adopts many hydrogen polysilazane (PSZ, per-hydro poly-silazane), hydrogen silsesquioxane (HSQ, hydro-silsesquioxane), methyl silsesquioxane (MSQ, methyl-silsesquioxane), any solution forms in siloxanes and the silicate, in heating plate or baking oven, under 50 to 350 ℃ of temperature, cure overlay then, to remove the solvent in overlay.Then, the layer that cures is annealed under 300 to 1000 ℃ of temperature in stove, with the layer that hardens and densification is cured.When spin-coating glass insulating barrier 206 adopted PSZ solution to form, annealing was comprising H
2, O
2, H
2Carry out in the atmosphere of one of O or its mixture.When any formation in spin-coating glass insulating barrier 206 employing HSQ, MSQ, siloxanes and the silicate solutions, annealing is comprising N
2Perhaps O
2Perhaps carry out in the atmosphere of its mixture.
With reference to Fig. 3 B and 4B, to form the part spin-coating glass insulating barrier that regional G/R contacts etched with grid in active region A/R, forms regional G/R with the projection grid.When etching spin-coating glass insulating barrier 206, prepared fin formula grid and formed the zone, and fin formula grid forms the zone and increased transistorized channel width.
With reference to Fig. 3 C and 4C, protective layer 230 is formed on Semiconductor substrate 200 and the etched spin-coating glass insulating barrier 206.By adopting spin-coating method coating carbon polymer layer [(CH
x)
n], and, form protective layer curing coated carbon polymer layer under 150 to 400 ℃ the temperature range to remove the solvent in coated carbon polymer layer.Coating carbon polymer layer makes it fill etched spin-coating glass insulating barrier.The thickness of the carbon polymer layer on the active region A/R of Semiconductor substrate 200 be about 200 to
With reference to Fig. 3 D and 4D, the protective layer 230 that etch-back is made by the carbon polymer layer is formed on partial protection layer 230 among the active region A/R with removal.Preferably, carry out etch back process until the screen oxide layer 220 that is exposed on the active region A/R.
With reference to Fig. 3 E and 4E, adopt wet etching process to remove the screen oxide layer that is exposed.Adopt dilution HF solution or HF and NH
4The F mixed solution carries out wet etching process.Because protective layer 230 has been formed on the spin-coating glass insulating barrier 206, so in wet etching process, prevented the loss of spin-coating glass insulating barrier 206.
With reference to Fig. 3 F and 4F, remove protective layer 230 residual on the partially-etched spin-coating glass insulating barrier 206.Adopt oxygen plasma etch technology under 20 to 300 ℃ temperature range, to remove protective layer.When on by the protective layer of carbon polymer layer manufacturing, carrying out oxygen plasma etch technology, only removed protective layer.Spin-coating glass insulating barrier 206 does not have loss, shown in following expression 1:
CH
x(s)+O
2(g)-＞CO
2(g)+H
2(g)+H
2O(g)------(1)
With reference to Fig. 3 G and 4G, grid material is used for forming grid 240.Comprise at semiconductor device 200 on the whole surface of spin-coating glass insulating barrier 206 of exposure and setting gradually: the gate insulator of making by oxide skin(coating) 242, first grid conductive layer 244, the second grid conductive layer 246 of Metal Substrate and the nitride based hard mask layer 248 made by polysilicon.The etching grid material form the zone with the protruding grid in active region A/R and the spin-coating glass insulating barrier 206 that exposes in grid form the zone and form grid 240.As mentioned above, during being used to remove the wet etching process of mask pattern, protective layer is protected spin-coating glass insulating barrier 206, and therefore prevents the short circuit between the neighboring gates 240.
Source/drain is formed on the both sides of the grid among the regional A/R that has chance with, and finishes the formation fin transistor according to embodiments of the invention thus.
By top description as seen, in an embodiment of the present invention, when carrying out wet etching process, be formed on protective layer on the spin-coating glass insulating barrier prevents the spin-coating glass insulating barrier during removing the wet etching process of oxide skin(coating) loss.By preventing this loss, can suppress to take place short circuit between the neighboring gates and the short circuit between grid and the contact plunger.Therefore can improve the reliability and the productive rate of transistor and resulting semiconductor device thereof.
In addition, in an embodiment of the present invention, comprise that the passive component of resistor, inductor and capacitor is formed on the rear surface of semiconductor chip.There is no need on printed circuit board (PCB), to be provided with separately passive component.Therefore, can reduce the size and the thickness of printed circuit board (PCB), make it that semiconductor packages that quantity increases can be set on printed circuit board (PCB).Equally, in an embodiment of the present invention, passive component is formed on the rear surface of semiconductor chip.Therefore, can shorten the connection length between active element and the passive component, make it can improve the electrical property that electrical/electronic is used.In addition, in the present invention, the rear surface of semiconductor chip is protected by protective layer, causes improving the reliability of final products.
On the other hand, the oxide skin(coating) in the described preferred embodiment of the present invention is a screen oxide, and it is used to prevent damage when carrying out injection technology.Yet, this oxide skin(coating) can be in isolation technology, be used to form the pad oxide of groove or the native oxide that during semiconductor fabrication process, produces in any.
Although described specific embodiments of the invention for illustrative purposes, those skilled in the art should be understood that, can carry out various modifications, increase and replacement to it, and not break away from the scope and spirit of the present invention that disclose as claim.
The priority that korean patent application 10-2007-0031908 number of requiring to submit on March 30th, 2007 of the application and submission on November 29th, 2007 korean patent application are 10-2007-0122998 number is all quoted as a reference at this.
Claims (13)
1. method of making fin transistor comprises following step:
Become groove by the etching semiconductor substrate-like;
In this groove, fill the insulating barrier that easily flows, be limited with the field insulating layer of source region with formation;
Etching and grid in this active region form the part of the easily mobile insulating barrier that the zone contact, so that this grid of projection forms the zone in this active region;
On this Semiconductor substrate, form protective layer to fill the etched insulating barrier that easily flows;
Removal is formed on the part of the protective layer on this active region, to expose this active area of semiconductor substrate territory;
Clean the active region of the exposure of this Semiconductor substrate;
Removal is retained in the protective layer on the etched insulating barrier that easily flows; And
The grid of the projection in this active region forms and forms grid on the zone.
2. the method for manufacturing fin transistor according to claim 1, wherein in the step of active region of this exposure of cleaning, this Semiconductor substrate has and is formed on its lip-deep oxide skin(coating).
3. the method for manufacturing fin transistor according to claim 1 wherein adopts etch back process to remove the step of the part that is formed on the protective layer on this active region.
4. the method for manufacturing fin transistor according to claim 2 wherein cleans the step of active region of the exposure of this Semiconductor substrate, is formed on oxide on this Semiconductor substrate with removal.
5. the method for manufacturing fin transistor according to claim 4 is wherein by adopting HF solution or the HF and the NH of dilution
4The wet etching process of F mixed solution cleans the step of active region of the exposure of this Semiconductor substrate.
6. the method for manufacturing fin transistor according to claim 1, wherein this runny insulating barrier comprises the spin-coating glass insulating barrier.
7. the method for manufacturing fin transistor according to claim 6, wherein this spin-coating glass insulating barrier adopts any solution in derive hydrolysising polyethylene silazane, hydrolysis silsesquioxane, polymethyl siloxane, siloxanes and the silicate to form.
8. the method for manufacturing fin transistor according to claim 1, wherein this protective layer comprises carbon polymer.
9. the method for manufacturing fin transistor according to claim 8 wherein forms this protective layer and comprises the steps:
Adopt spin-coating method to apply this carbon polymer protective layer; And
Cure the carbon polymer protective layer of coating.
10. the method for manufacturing fin transistor according to claim 9, wherein apply this carbon polymer protective layer make the scope of the thickness of this carbon polymer protective layer on this active area of semiconductor substrate territory be 200 to
11. the method for manufacturing fin transistor according to claim 9, wherein carrying out this temperature range of curing is 150 to 400 ℃.
12. the method for manufacturing fin transistor according to claim 1 wherein adopts oxygen plasma etch technology to remove to be retained in the step of the protective layer on the etched insulating barrier that easily flows.
13. the method for manufacturing fin transistor according to claim 12, the temperature range of wherein carrying out this oxygen plasma etch technology are 20 to 300 ℃.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR31908/07 | 2007-03-30 | ||
| KR20070031908 | 2007-03-30 | ||
| KR122998/07 | 2007-11-29 | ||
| KR1020070122998A KR100929636B1 (en) | 2007-03-30 | 2007-11-29 | Pin transistor manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101276782A CN101276782A (en) | 2008-10-01 |
| CN101276782B true CN101276782B (en) | 2010-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100804750A Expired - Fee Related CN101276782B (en) | 2007-03-30 | 2008-02-19 | Method for manufacturing fin transistor that prevents etching loss of a spin-on-glass insulation layer |
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| Country | Link |
|---|---|
| KR (1) | KR100929636B1 (en) |
| CN (1) | CN101276782B (en) |
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| CN103295882A (en) * | 2013-06-03 | 2013-09-11 | 上海华力微电子有限公司 | Formation method of semiconductor structure |
| KR102165249B1 (en) | 2019-02-19 | 2020-10-13 | 국방과학연구소 | Fin structure forming method of high electron mobility transistor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6852620B2 (en) * | 2002-07-26 | 2005-02-08 | Samsung Electronics Co., Ltd. | Semiconductor device with self-aligned junction contact hole and method of fabricating the same |
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| JP2000114362A (en) | 1998-10-02 | 2000-04-21 | Nec Corp | Manufacture of semiconductor device |
| KR20040055389A (en) * | 2002-12-21 | 2004-06-26 | 주식회사 하이닉스반도체 | Method for forming STI oxide film for semiconductor process |
| KR20070017656A (en) * | 2005-08-08 | 2007-02-13 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR100713924B1 (en) | 2005-12-23 | 2007-05-07 | 주식회사 하이닉스반도체 | Fin transistor and method for forming thereof |
-
2007
- 2007-11-29 KR KR1020070122998A patent/KR100929636B1/en not_active IP Right Cessation
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2008
- 2008-02-19 CN CN2008100804750A patent/CN101276782B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6852620B2 (en) * | 2002-07-26 | 2005-02-08 | Samsung Electronics Co., Ltd. | Semiconductor device with self-aligned junction contact hole and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101276782A (en) | 2008-10-01 |
| KR20080089138A (en) | 2008-10-06 |
| KR100929636B1 (en) | 2009-12-03 |
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