CN101232002A - 一具有标示结构之封装及其方法 - Google Patents

一具有标示结构之封装及其方法 Download PDF

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CN101232002A
CN101232002A CNA2008100000260A CN200810000026A CN101232002A CN 101232002 A CN101232002 A CN 101232002A CN A2008100000260 A CNA2008100000260 A CN A2008100000260A CN 200810000026 A CN200810000026 A CN 200810000026A CN 101232002 A CN101232002 A CN 101232002A
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substrate
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semiconductor subassembly
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杨文焜
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Yupei Science & Technology Co Ltd
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Abstract

本发明提供一方法其具有一金属标示结构之半导体组件封装，其包含一具有晶粒容纳凹槽之基板，其形成于基板之上表面，以及一通孔结构通过此基板，其中具有一终端接点于通孔结构之下方，且此基板包含一导电线路形成于此基板之下表面；一晶粒黏着于晶粒容纳槽中，且具有复数个焊垫于其上；一第一介电层形成于晶粒与基板上方，且露出焊垫与通孔结构表面；一重布层形成于此第一介电层之上以耦合此焊垫与此通孔结构；一第二介电层形成于此第一介电层与此重布层线路之上；一金属标示层形成于此第二介电层之上；一散热层形成于金属标示层之上。

Description

一具有标示结构之封装及其方法
技术领域
本发明系关于一种封装结构，尤其是一种板材级封装-芯片尺寸级封装结构制作方法，其标示结构封装可保护结构不受电磁辐射干扰且提供更好之散热处理。
背景技术
近几年来，高科技电子制造业开始更小且更人性化之电子产品，快速发展之半导体技术致使半导体封装面积缩小，以适应多脚位、高精密线宽以及极小化电子零件需求。晶圆级封装之目的与优点在于降低制造成本，以及藉由降低传导路径，以减少寄生电容与电感效应，得到更好之讯杂比(SNR)。
芯片级封装(CSP)，一般形成之方式为将一半导体晶圆切割成半导体芯片，接着半导体芯片黏着于基板上，且事先决定好之位置并将之黏着，并将之密封于一树脂中，接着将此密封树脂与基板切割成片，成为一半导体芯片组件。另一传统方式，一半导体晶圆(尚未切割成为半导体芯片)黏着于基板上，接着此半导体晶圆与基板被切割，且切割分离半导体芯片，并封装封装密封树脂。
更进一步因电路设计、晶圆制作与晶圆封装，皆会影响其操作性、性能与芯片寿命，此发明叙述便针对芯片封装技术。因为IC芯片之特性与性能快速增加，芯片外部电路之讯号延迟与衰减产生，益增导电性增加之需求。一芯片封装于一小面积IC芯片封装中，其需具良好之散热以及保护，加上较高性能之特性，此其为芯片封装所需达到之目标。
更进一步，因为传统封装技术须于晶圆上切割成晶粒，并个别封装晶粒，故而此技术于制程中较为耗时。当组件面积成为需求因素，因为芯片封装技术高度影响集成电路开发，封装技术亦需要求。由上述因素，封装技术之发展，由球门阵列(BGA)、覆晶球门阵列(FC-BGA)、芯片级封装(CSP)演进至今日晶圆尺寸级封装。晶圆级封装”顾名思义，其于个别化(切割)成为芯片(晶粒)前，便将整个封装以及晶圆内部电性连结与其它之制程完成。一般而言于所有组装制程或封装制程完成，单独的半导体封装于晶圆上被分离，使其具有多个半导体晶粒。晶圆级封装其具有极小之尺寸，兼具极佳之电气特性。
于制造方法中，晶圆尺寸级封装(WLCSP)为一先进封装方法，藉由于晶圆上作晶粒制造与测试，接着将其切割并组装成适合表面黏着生产线用。因为晶圆级封装使用整片晶圆作为标的，非使用单一晶粒，因此于施行切割制程前，测试也已完成，进一步WLP为先进封装技术，致使打线、黏晶与上胶填隙等制程可被省略。藉由使用WLP技术其成本与制造时间可被降低，且其结构大小与晶粒同，此技术可符合电子组件之极小化。更进一步，WLCSP其具有可直接制作重布层于晶粒上，藉由使用晶粒区域作为黏着点。此达成与晶粒表面上重布一面数组，其可使用此晶粒之整个表面。藉由形成覆晶凸块，此黏着点位于重布电路，而于其晶粒背面藉由微小黏着点，直接连结于印刷电路板(PCB)。
虽然WLCSP可大大地降低讯号路径长度，旦当其整合晶粒与内部组件变多时，依然难以容纳所有黏着点于晶粒表面上。当于更高之整合中，脚位于晶粒上增加时，于一有限面积中增加重布脚数变难以达成。纵使重布脚数可设计，其脚位间距将过小，亦将难以符合印刷电路板间距需求。亦即此叙述之习知结构与制程，将有良率与可靠度因素之困扰，进一步此制作方式之缺点为更高之制造成本且更为耗时。
基于前述之观点，本发明提出一面板尺寸封装-芯片尺寸封装之新结构与方法，其作为可防护电磁干扰并克服上述缺点之技术。
发明内容
本发明前述之形式、目的、观点、特征及优点将随着以下较佳实施例中详细的描述及其伴随之图式而愈见明显，其细节描述与图式仅用以述明本发明。而本发明之范畴将由随附之专利请求项来定义。
本发明之一目的，为藉由一PSP-CSP制作标示结构封装之结构与方法，提供半导体组件封装，以作为保护结构不受电磁(EM)波干扰。
本发明之另一目的，为藉由一PSP-CSP制作标示结构封装之结构与方法，提供一半导体组件封装，于组件之上表面使具有较好之外观。
本发明之又一目的，为藉由一PSP-CSP制作标示结构封装之结构与方法，提供一半导体组件封装，其可连结地线作为导热路径。
本发明之再一目地，为藉由一PSP-CSP制作标示结构封装之结构与方法，提供一半导体组件封装，其可改进接地屏蔽效能。
本发明之再一目的，为藉由一PSP-CSP制作标示结构封装之结构与方法，提供一半导体组件封装，其可保护组件之重布线路。
本发明提供一具有标示结构封装之半导体封装结构，其包含此基板之上表面形成具有一晶粒容内槽于其中之结构，且具有一通孔贯穿，其中具终端接点形成于基板下表面之上，且其基板下表面上具有导电线路。一晶粒黏着于晶粒容纳槽中，且具有复数个焊垫于其上，一第一介电层作为连接此焊垫与此通孔结构；一第二介电层形成于此第一介电层与此重布层线路之上；一金属标示层形成于此第二介电层，且一散热层形成于金属标示层之上。
本发明提供一方法以作为半导体组件封装，其结构包含一具有晶粒容纳凹槽之基板，其形成于基板之上表面，以及一通孔结构通过此基板，其中具有一终端接点于通孔结构之下方，且此基板包含一导电线路形成于此基板之下表面；黏着一晶粒于此容纳凹槽中，其中晶粒上具有复数个焊垫；形成一第一介电层于此基板上且此晶粒露出焊垫与通孔结构；形成一重布层于此第一介电层之上，以连结焊垫与此通孔结构；形成一第二介电层于此重布层之上；形成一金属标示层于此第二介电层之上；且形成一散热层于此金属标示层之上。
本发明之积极效果如下：本发明可保护结构不受电磁辐射干扰；本发明可连接至地线作为散热，且亦可增进接地屏蔽效能；本发明具有微小化之芯片尺寸封装结构面积；本发明可保护此组件之重布层(RDL)电路。故而本发明可提供不同于习知技艺之效果，且解决习知技艺之问题，此方法可用于晶圆或面板工业，且亦可经调整并实施于其它相关应用。
附图说明
本发明可藉由说明书中若干较佳实施例及详细叙述以及后附图式得以了解。然而，此领域之技艺者应得以领会所有本发明之较佳实施例系用以说明而非用以限制本发明之申请专利范围，其中：
图1为一根据本发明所述，半导体组件封装具有一标示结构封装结构之基板尺寸芯片尺寸封装(PSP-CSP)之剖面图；
图2为一根据本发明所述，半导体组件封装具有一标示结构之基板尺寸芯片尺寸封装(PSP-CSP)之上视图；
图3为一根据本发明所述方法，半导体组件封装具有一标示结构之基板尺寸芯片尺寸封装(PSP-CSP)之流程图；
图中：
100标示结构
102基板
104黏着材料
106晶粒
108焊垫
110第一介电层
112接触面导电层
114容纳凹槽
116重布层(RDL)
118第二介电层
120金属标示层
121散热层
122导通线路
124通孔
125终端接点
126保护层
128焊料凸块
130字符
200步骤(制备一基板于其上表面使具有一晶粒容纳凹槽)
202步骤(黏着一晶粒于晶粒容纳凹槽内)
204步骤(形成一第一介电层于基板上)
206步骤(形成导电接触面于焊垫表面上)
208步骤(形成一重布层于焊垫上方)
210步骤(形成一第二介电层于重布层之上)
212步骤(形成一标示层与散热层于第二介电层之上)
214步骤(形成一保护层于基板下表面以覆盖导电线路)
216步骤(焊接一复数个焊料凸块于终端接点)
具体实施方式
本发明将以较佳之实施例及观点加以详细叙述，而此类叙述系解释本发明之结构及程序，只用以说明而非用以限制本发明之申请专利范围。因此，除说明书中之较佳实施例之外，本发明亦可广泛实行于其它实施例。
图1为一根据本发明所述，半导体组件封装，其具有一标示结构100之基板尺寸芯片尺寸封装(PSP-CSP)之剖面图，其具有一标示结构100之封装中，其包含一基板102、一晶粒容纳凹槽114、一通孔124、一黏着材料104、一晶粒106、复数个焊垫108、一第一介电层110、接触面导电层112、一重布层(RDL)116、一第二介电层118、一金属标示层120、一散热层121、一导通线路122、保护层126以及复数个焊料凸块128。
于图1中此基板102具有一晶粒容纳凹槽114，其形成于基板102之上表面以容纳一晶粒106。复数个通孔结构124被制成，由基板102之上表面至下表面贯通基板102。此复数个通孔结构124被填入导电物质以作为电性导通，此终端接点125形成于基板102下表面之下方，且藉由此通孔结构124连结，此导通线路122(导线电路)被设置于此基板102之下表面之上。
进一步，一晶粒106具有复数个焊垫108黏着于晶粒容纳芯片114，且此焊垫108被形成于此晶粒106上表面，于形成重布层(RDL)之前，此焊垫108之表面为露出。于形成此第一介电层110于此晶粒106以及此基板102上之后，此第一介电层110之部分区域被移除，以露出焊垫108之表面与通孔结构124，其接口传导层112被填入此焊垫108与此通孔结构124之露出表面，以作为电性之相互连结。接着此重布层116被形成于接口导电层112与此第一介电层110之上。亦即此接口导电层112形成于焊垫108与此通孔结构124之上表面，为此重布层116覆盖，且此重布层116可连结此接口导电层112其形成于焊垫108与通孔结构124之表面上。
下一步骤，一第二介电层118被形成于此第一介电层110之上，以覆盖此重布层116。紧接着此金属标示层120被形成于此第二介电层118，且接着此散热层121被形成于此金属标示层120之上。复数个焊料凸块128被形成于终端接点120之上，且此复数个焊料凸块108可藉由连接焊垫108经过通孔结构124形成电性导通。
于一实施例中，此封装具有一标示结构100，其进一步包含一黏着材料104填入并覆盖此晶粒容纳凹槽114以固着此晶粒106。
于一实施例中，此基板102之材料包含为环氧树脂型，FR5、FR4、B一三氮树脂(Bismaleimide triazine，BT)，亦可为金属、合金、硅、陶瓷或印刷电路板。其合金进一步可包含合金42其为较佳例示，其成分为铁、镍合金，其膨胀系数使其适合加入于具微小电子线路之硅芯片中，其组成成分为42％镍与58％铁。其合金成分亦可为柯华合金(Kovar)，其组成为29％镍、17％钴与54％铁。
于一实施例中，此第一介电层110与第二介电层118之材料，可包含苯环丁烯(BCB)、硅氧烷高分子(SINR)或聚亚酰胺(PI)。此重布层116之材料其构成为合金，其可包含钛/铜/金之合金或钛/铜/镍/金合金。
于一实施例中，此金属标示层120之材料包含金属，以作为电磁辐射干扰之保护。须知本发明所揭露之材料，仅用于叙述而非用以限制本发明。
于一实施例中，此散热层121之材料，其可包含分子散热风扇(molecular cooling fan)于金属标示层120上，以增强散热。
参照图2，其为一根据本发明之半导体组件标示结构封装之上视图，其中基板尺寸封装-芯片尺寸封装(PSP-CSP)，具有一标示金属层100。标示结构100之封装进一步包含进一步可包含一字型、一文字、一字符、一图案或商标130，标志于此结构100之上表面。
于一实施例中，本发明进一步包含一讯号接地，其连结至金属标示层120上，作为接地屏蔽与散热之用。
根据本发明所述之观点，当完成PSP-CSP之增层结构，一种子金属层溅镀于此第二介电层118之上，此亦即，此种子金属层溅镀于此结构之上表面，此种子金属层可包含钛/铜。下一步骤涂布光阻(图中未显示)于此种子金属层上，且对光阻作光微影以形成此复数个字符130。一铜/金电镀于标示结构封装100之表面，其铜/金薄膜厚度约为6-20微米较佳。接着将光阻层自标示结构封装100之上表面除去，此种子金属层可/但不限于用湿式蚀刻方式除去。接着涂布散热材料121(分子散热风扇较佳)，于金属标示层120，其散热层121之厚度约为10微米。
接着此金属标示层120与散热层121形成于标示结构封装100之上表面，换言之，具有标示结构之封装100之上表面为金属标示层120与散热层121所覆盖，一金膜或可镀于金属标示层120上，且不可覆盖此复数个金属标示层120。须注意者，其它之金属材质亦可被用来镀于金属标示层120之上。
于一实施例中，此复数个特征字符、字、图案或商标，包含但不限定于，各种商标、图案或标志。
根据本发明之观点，本发明进一步提供一方法，形成一具有标示结构封装100，图3显示根据本发明所述之一标示结构封装100形成方式之流程图，其步骤叙述如下。
于步骤200首先备妥一基板102其具有一晶粒容纳凹槽114形成于此基板之上表面，且具一通孔结构124，其中具有终端接点125形成于通孔结构124，且此基板102包含一导电线路122形成于此基板之上表面。接着步骤202将一晶粒106粘着于此晶粒容纳凹槽114，且此晶粒106具有复数个焊垫108形成于上。于步骤204将一第一介电层110覆盖于基板102与此晶粒106之上，并露出焊垫108以及通孔结构124。步骤206将导电接触面112布于焊垫108与通孔结构124之露出面上。
紧接着于步骤208，一重布层116形成于焊垫108与通孔结构124之上，以相互连接。于步骤210，一第二介电层118形成此重布层116之上。接着步骤212，一金属标示层120与一散热层121形成于此第二介电层118之上。于步骤214，一保护层126形成于此基板102之下表面，以覆盖此导电线路122。接着步骤216，一复数个焊料凸块128焊接于终端接点125。
须知本发明中所示之结构，不限于上述之材料与布置，其结构中材料与布置，可根据不同之需求作调整。
根据本发明之观点，本发明提供一金属标示结构，其可保护结构不受电磁辐射干扰，且具于组件之上表面具有较好之外观。进一步本发明提供一扇出型态结构，其可连接至地线作为散热，且亦可增进接地屏蔽效能。本发明进一步提供一新型结构，其具有微小化之芯片尺寸封装结构面积。更进一步，本发明提供一金属标示层结构与方法，其可保护此组件之重布层(RDL)电路。故而本发明揭露一超薄芯片尺寸封装结构与方法，可提供不同于习知技艺之效果，且解决习知技艺之问题，此方法可用于晶圆或面板工业，且亦可经调整并实施于其它相关应用。
上述叙述系为本发明之较佳实施例。此领域之技艺者应得以领会其系用以说明本发明而非用以限定本发明所主张之专利权利范围。其专利保护范围当视后附之申请专利范围及其等同领域而定。凡熟悉此领域之技艺者，在不脱离本专利精神或范围内，所作之更动或润饰，均属于本发明所揭示精神下所完成之等效改变或设计，且应包含在下述之申请专利范围内。

Claims (10)

1.一半导体组件封装，其特征在于：所述半导体组件封装，具有一标示结构，包含：
一基板其具有一晶粒容纳凹槽于其上表面，且其结构中具有一通孔结构形成贯通，且具有一终端接点形成于此基板之下表面，以及导电线路形成于此基板之下表面；
一晶粒黏着于此晶粒容纳凹槽且具有一复数个焊垫于其上；
一第一介电层形成于此晶粒与此基板上，且露出此焊垫与此通孔之表面；
一重布层形成于此第一介电层以耦合此焊垫与此通孔结构；
一第二介电层形成于此第一介电层与此重布层线路；且一金属标示层形成于此第二介电层。
2.根据权利要求1所述的半导体组件封装，其特征在于：进一步包含复数个焊料凸块形成于此终端接点上，其中此复数个焊料凸块可藉由此通孔结构，作为此焊垫间电性传导。
3.根据权利要求1所述的半导体组件封装，其特征在于：其中可包含一种子金属层溅镀于此第一与第二介电层之上。
4.根据权利要求1所述的半导体组件封装，其特征在于：进一步包含一散热层于此金属标示层上。
5.根据权利要求1所述的半导体组件封装，其特征在于：其中此金属标示层之材料其包含金属以保护此封装不受电磁辐射干扰。
6.根据权利要求1所述的半导体组件封装，其特征在于：进一步可包含一讯号接地连接至此金属标示层，以作为接地屏蔽与散热。
7.一制作半导体组件封装之方法，其特征在于：所述制作半导体组件封装之方法，具有一标示结构之方法，其包含：制备一具有晶粒容纳凹槽之基板，其形成于基板之上表面，以及一通孔结构通过此基板，其中具有一终端接点于通孔结构之下方，且此基板包含一导电线路形成于此基板之下表面；
黏着一晶粒于此容纳凹槽中，其中晶粒上具有复数个焊垫；
形成一第一介电层于此基板上且此晶粒露出焊垫与通孔结构；
形成一重布层于此第一介电层之上，以连结焊垫与此通孔结构；
形成一第二介电层于此重布层之上；
形成一金属标示层于此第二介电层之上。
8.根据权利要求7所述的制作半导体组件封装之方法，其特征在于：进一步可包含一涂布一散热材料于此金属标示层之步骤。
9.根据权利要求7所述的制作半导体组件封装之方法，其特征在于：进一步可包含一讯号接地连接至此金属标示层之步骤。
10.根据权利要求7所述的制作半导体组件封装之方法，其特征在于：其中可包含一种子金属层溅镀于此第一与第二介电层上之步骤。
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