CN101176195B - 用于混合取向衬底的改进非晶化/模板化再结晶方法 - Google Patents
用于混合取向衬底的改进非晶化/模板化再结晶方法 Download PDFInfo
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- CN101176195B CN101176195B CN2006800167944A CN200680016794A CN101176195B CN 101176195 B CN101176195 B CN 101176195B CN 2006800167944 A CN2006800167944 A CN 2006800167944A CN 200680016794 A CN200680016794 A CN 200680016794A CN 101176195 B CN101176195 B CN 101176195B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02609—Crystal orientation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Optics & Photonics (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/142,646 | 2005-06-01 | ||
| US11/142,646 US7291539B2 (en) | 2005-06-01 | 2005-06-01 | Amorphization/templated recrystallization method for hybrid orientation substrates |
| PCT/US2006/019417 WO2006130360A2 (en) | 2005-06-01 | 2006-05-18 | Improved amorphization/templated recrystallization method for hybrid orientation substrates |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101176195A CN101176195A (zh) | 2008-05-07 |
| CN101176195B true CN101176195B (zh) | 2010-06-02 |
Family
ID=37482138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006800167944A Expired - Fee Related CN101176195B (zh) | 2005-06-01 | 2006-05-18 | 用于混合取向衬底的改进非晶化/模板化再结晶方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (5) | US7291539B2 (enExample) |
| EP (1) | EP1886342A4 (enExample) |
| JP (1) | JP4959690B2 (enExample) |
| CN (1) | CN101176195B (enExample) |
| TW (1) | TW200710997A (enExample) |
| WO (1) | WO2006130360A2 (enExample) |
Families Citing this family (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7442629B2 (en) | 2004-09-24 | 2008-10-28 | President & Fellows Of Harvard College | Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate |
| US7057256B2 (en) | 2001-05-25 | 2006-06-06 | President & Fellows Of Harvard College | Silicon-based visible and near-infrared optoelectric devices |
| US7291539B2 (en) * | 2005-06-01 | 2007-11-06 | International Business Machines Corporation | Amorphization/templated recrystallization method for hybrid orientation substrates |
| US7396407B2 (en) * | 2006-04-18 | 2008-07-08 | International Business Machines Corporation | Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates |
| KR100782497B1 (ko) * | 2006-11-20 | 2007-12-05 | 삼성전자주식회사 | 얇은 응력이완 버퍼패턴을 갖는 반도체소자의 제조방법 및관련된 소자 |
| US9034102B2 (en) * | 2007-03-29 | 2015-05-19 | United Microelectronics Corp. | Method of fabricating hybrid orientation substrate and structure of the same |
| US20080248626A1 (en) * | 2007-04-05 | 2008-10-09 | International Business Machines Corporation | Shallow trench isolation self-aligned to templated recrystallization boundary |
| US7846803B2 (en) * | 2007-05-31 | 2010-12-07 | Freescale Semiconductor, Inc. | Multiple millisecond anneals for semiconductor device fabrication |
| US7642197B2 (en) * | 2007-07-09 | 2010-01-05 | Texas Instruments Incorporated | Method to improve performance of secondary active components in an esige CMOS technology |
| FR2918792B1 (fr) * | 2007-07-10 | 2010-04-23 | Soitec Silicon On Insulator | Procede de traitement de defauts d'interface dans un substrat. |
| US20090057816A1 (en) * | 2007-08-29 | 2009-03-05 | Angelo Pinto | Method to reduce residual sti corner defects generated during spe in the fabrication of nano-scale cmos transistors using dsb substrate and hot technology |
| JP2009111074A (ja) * | 2007-10-29 | 2009-05-21 | Toshiba Corp | 半導体基板 |
| US8043947B2 (en) * | 2007-11-16 | 2011-10-25 | Texas Instruments Incorporated | Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate |
| EP2065921A1 (en) * | 2007-11-29 | 2009-06-03 | S.O.I.T.E.C. Silicon on Insulator Technologies | Method for fabricating a semiconductor substrate with areas with different crystal orienation |
| WO2009095813A1 (en) * | 2008-01-28 | 2009-08-06 | Nxp B.V. | A method for fabricating a dual-orientation group-iv semiconductor substrate |
| US8211786B2 (en) | 2008-02-28 | 2012-07-03 | International Business Machines Corporation | CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication |
| US7541629B1 (en) | 2008-04-21 | 2009-06-02 | International Business Machines Corporation | Embedded insulating band for controlling short-channel effect and leakage reduction for DSB process |
| US7943479B2 (en) * | 2008-08-19 | 2011-05-17 | Texas Instruments Incorporated | Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flow |
| US20100200896A1 (en) * | 2009-02-09 | 2010-08-12 | International Business Machines Corporation | Embedded stress elements on surface thin direct silicon bond substrates |
| US7897447B2 (en) * | 2009-02-24 | 2011-03-01 | Texas Instruments Incorporated | Use of in-situ HCL etch to eliminate by oxidation recrystallization border defects generated during solid phase epitaxy (SPE) in the fabrication of nano-scale CMOS transistors using direct silicon bond substrate (DSB) and hybrid orientation technology (HOT) |
| FR2942674B1 (fr) * | 2009-02-27 | 2011-12-16 | Commissariat Energie Atomique | Procede d'elaboration d'un substrat hybride par recristallisation partielle d'une couche mixte |
| US8193616B2 (en) * | 2009-06-29 | 2012-06-05 | Kabushiki Kaisha Toshiba | Semiconductor device on direct silicon bonded substrate with different layer thickness |
| WO2011004474A1 (ja) * | 2009-07-08 | 2011-01-13 | 株式会社 東芝 | 半導体装置及びその製造方法 |
| US9673243B2 (en) | 2009-09-17 | 2017-06-06 | Sionyx, Llc | Photosensitive imaging devices and associated methods |
| US9911781B2 (en) | 2009-09-17 | 2018-03-06 | Sionyx, Llc | Photosensitive imaging devices and associated methods |
| US9028924B2 (en) | 2010-03-25 | 2015-05-12 | Novellus Systems, Inc. | In-situ deposition of film stacks |
| US8741394B2 (en) | 2010-03-25 | 2014-06-03 | Novellus Systems, Inc. | In-situ deposition of film stacks |
| US8692198B2 (en) | 2010-04-21 | 2014-04-08 | Sionyx, Inc. | Photosensitive imaging devices and associated methods |
| US20120146172A1 (en) | 2010-06-18 | 2012-06-14 | Sionyx, Inc. | High Speed Photosensitive Devices and Associated Methods |
| CN102569394B (zh) * | 2010-12-29 | 2014-12-03 | 中芯国际集成电路制造(北京)有限公司 | 晶体管及其制作方法 |
| US20130168693A1 (en) * | 2011-02-15 | 2013-07-04 | Sumitomo Electric Industries, Ltd. | Protective-film-attached composite substrate and method of manufacturing semiconductor device |
| US9496308B2 (en) | 2011-06-09 | 2016-11-15 | Sionyx, Llc | Process module for increasing the response of backside illuminated photosensitive imagers and associated methods |
| US20130016203A1 (en) | 2011-07-13 | 2013-01-17 | Saylor Stephen D | Biometric imaging devices and associated methods |
| WO2013120093A1 (en) * | 2012-02-10 | 2013-08-15 | Sionyx, Inc. | Low damage laser-textured devices and associated methods |
| US8652951B2 (en) * | 2012-02-13 | 2014-02-18 | Applied Materials, Inc. | Selective epitaxial germanium growth on silicon-trench fill and in situ doping |
| US9064764B2 (en) | 2012-03-22 | 2015-06-23 | Sionyx, Inc. | Pixel isolation elements, devices, and associated methods |
| KR102025441B1 (ko) * | 2012-04-06 | 2019-09-25 | 노벨러스 시스템즈, 인코포레이티드 | 증착 후 소프트 어닐링 |
| US9117668B2 (en) | 2012-05-23 | 2015-08-25 | Novellus Systems, Inc. | PECVD deposition of smooth silicon films |
| US9388491B2 (en) | 2012-07-23 | 2016-07-12 | Novellus Systems, Inc. | Method for deposition of conformal films with catalysis assisted low temperature CVD |
| JP6466346B2 (ja) | 2013-02-15 | 2019-02-06 | サイオニクス、エルエルシー | アンチブルーミング特性を有するハイダイナミックレンジcmos画像センサおよび関連づけられた方法 |
| WO2014151093A1 (en) | 2013-03-15 | 2014-09-25 | Sionyx, Inc. | Three dimensional imaging utilizing stacked imager devices and associated methods |
| US8895415B1 (en) | 2013-05-31 | 2014-11-25 | Novellus Systems, Inc. | Tensile stressed doped amorphous silicon |
| US9209345B2 (en) | 2013-06-29 | 2015-12-08 | Sionyx, Inc. | Shallow trench textured regions and associated methods |
| US9490161B2 (en) * | 2014-04-29 | 2016-11-08 | International Business Machines Corporation | Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same |
| US9666493B2 (en) | 2015-06-24 | 2017-05-30 | International Business Machines Corporation | Semiconductor device structure with 110-PFET and 111-NFET curent flow direction |
| RU2641508C2 (ru) * | 2016-07-01 | 2018-01-17 | федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский национальный исследовательский университет информационных технологий, механики и оптики" (Университет ИТМО) | Способ изготовления устройства микротехники в объеме пластины фоточувствительного стекла |
| JP6547702B2 (ja) * | 2016-07-26 | 2019-07-24 | 信越半導体株式会社 | 半導体装置の製造方法及び半導体装置の評価方法 |
| US10147609B2 (en) | 2016-12-15 | 2018-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor epitaxy bordering isolation structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1319252A (zh) * | 1998-09-25 | 2001-10-24 | 旭化成株式会社 | 半导体衬底及其制造方法、和使用它的半导体器件及其制造方法 |
| US6825102B1 (en) * | 2003-09-18 | 2004-11-30 | International Business Machines Corporation | Method of improving the quality of defective semiconductor material |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4385937A (en) | 1980-05-20 | 1983-05-31 | Tokyo Shibaura Denki Kabushiki Kaisha | Regrowing selectively formed ion amorphosized regions by thermal gradient |
| JPS60154548A (ja) | 1984-01-24 | 1985-08-14 | Fujitsu Ltd | 半導体装置の製造方法 |
| US4768076A (en) | 1984-09-14 | 1988-08-30 | Hitachi, Ltd. | Recrystallized CMOS with different crystal planes |
| US4816893A (en) | 1987-02-24 | 1989-03-28 | Hughes Aircraft Company | Low leakage CMOS/insulator substrate devices and method of forming the same |
| JPS63311718A (ja) * | 1987-06-15 | 1988-12-20 | Hitachi Ltd | ヘテロ構造単結晶半導体薄膜の製造方法 |
| JPH01162376A (ja) | 1987-12-18 | 1989-06-26 | Fujitsu Ltd | 半導体装置の製造方法 |
| JPH01162362A (ja) | 1987-12-18 | 1989-06-26 | Fujitsu Ltd | 半導体装置の製造方法 |
| JPH02170577A (ja) * | 1988-12-23 | 1990-07-02 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
| JPH04188612A (ja) * | 1990-11-19 | 1992-07-07 | Canon Inc | 結晶成長方法及び該方法によって得られた結晶物品 |
| JP3017860B2 (ja) | 1991-10-01 | 2000-03-13 | 株式会社東芝 | 半導体基体およびその製造方法とその半導体基体を用いた半導体装置 |
| US5888872A (en) | 1997-06-20 | 1999-03-30 | Advanced Micro Devices, Inc. | Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall |
| JP4521542B2 (ja) | 1999-03-30 | 2010-08-11 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体基板 |
| US6214653B1 (en) * | 1999-06-04 | 2001-04-10 | International Business Machines Corporation | Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate |
| US6404038B1 (en) | 2000-03-02 | 2002-06-11 | The United States Of America As Represented By The Secretary Of The Navy | Complementary vertical bipolar junction transistors fabricated of silicon-on-sapphire utilizing wide base PNP transistors |
| JP2003092399A (ja) * | 2001-09-18 | 2003-03-28 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| JP3782021B2 (ja) | 2002-02-22 | 2006-06-07 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、半導体基板の製造方法 |
| US6902962B2 (en) | 2003-04-04 | 2005-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon-on-insulator chip with multiple crystal orientations |
| US7329923B2 (en) | 2003-06-17 | 2008-02-12 | International Business Machines Corporation | High-performance CMOS devices on hybrid crystal oriented substrates |
| US20050116290A1 (en) * | 2003-12-02 | 2005-06-02 | De Souza Joel P. | Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers |
| US7285473B2 (en) * | 2005-01-07 | 2007-10-23 | International Business Machines Corporation | Method for fabricating low-defect-density changed orientation Si |
| US7060585B1 (en) | 2005-02-16 | 2006-06-13 | International Business Machines Corporation | Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization |
| US7291539B2 (en) * | 2005-06-01 | 2007-11-06 | International Business Machines Corporation | Amorphization/templated recrystallization method for hybrid orientation substrates |
-
2005
- 2005-06-01 US US11/142,646 patent/US7291539B2/en not_active Expired - Fee Related
-
2006
- 2006-04-18 US US11/406,122 patent/US7547616B2/en not_active Expired - Fee Related
- 2006-05-18 EP EP06770646A patent/EP1886342A4/en not_active Withdrawn
- 2006-05-18 WO PCT/US2006/019417 patent/WO2006130360A2/en not_active Ceased
- 2006-05-18 JP JP2008514682A patent/JP4959690B2/ja not_active Expired - Fee Related
- 2006-05-18 CN CN2006800167944A patent/CN101176195B/zh not_active Expired - Fee Related
- 2006-05-30 TW TW095119177A patent/TW200710997A/zh unknown
-
2007
- 2007-10-12 US US11/871,694 patent/US7704852B2/en not_active Expired - Fee Related
-
2008
- 2008-04-04 US US12/062,749 patent/US7691733B2/en not_active Expired - Fee Related
-
2010
- 2010-04-26 US US12/767,261 patent/US7960263B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1319252A (zh) * | 1998-09-25 | 2001-10-24 | 旭化成株式会社 | 半导体衬底及其制造方法、和使用它的半导体器件及其制造方法 |
| US6825102B1 (en) * | 2003-09-18 | 2004-11-30 | International Business Machines Corporation | Method of improving the quality of defective semiconductor material |
Also Published As
| Publication number | Publication date |
|---|---|
| US20080108204A1 (en) | 2008-05-08 |
| JP4959690B2 (ja) | 2012-06-27 |
| US7291539B2 (en) | 2007-11-06 |
| CN101176195A (zh) | 2008-05-07 |
| US7960263B2 (en) | 2011-06-14 |
| US7704852B2 (en) | 2010-04-27 |
| US7691733B2 (en) | 2010-04-06 |
| JP2008543081A (ja) | 2008-11-27 |
| US20100203708A1 (en) | 2010-08-12 |
| US7547616B2 (en) | 2009-06-16 |
| TW200710997A (en) | 2007-03-16 |
| US20080286917A1 (en) | 2008-11-20 |
| US20060276011A1 (en) | 2006-12-07 |
| EP1886342A4 (en) | 2011-06-15 |
| US20060275971A1 (en) | 2006-12-07 |
| EP1886342A2 (en) | 2008-02-13 |
| WO2006130360A2 (en) | 2006-12-07 |
| WO2006130360A3 (en) | 2007-06-14 |
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