CN101132667A - 印刷电路板的布局 - Google Patents
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Abstract
一种适于接合到集成电路装置的印刷电路板的布局。此布局包含:第一金属层,其配置在第一绝缘层中;以及第二金属层,其配置在第一绝缘层上方的第二绝缘层中。第一金属层与第二金属层通过填充有导电材料的多个接触窗而彼此连接,且经排列以在印刷电路的接垫结构区和线结构区中实质上彼此平行。已连接的第一金属层和第二金属层用以作为从印刷电路板到所接合的集成电路装置的信号路径,以改进电力供应的驱动能力。
Description
技术领域
本发明涉及一种用于增强从印刷电路板到所接合的集成电路的信号路径的驱动能力的布局(layout)。更确切地说,本发明是有关于一种从印刷电路板到所接合的集成电路的信号路径的布局,其通过减小布局的电容来改进集成电路的驱动能力。
背景技术
玻璃覆晶(Chip-on-Glass,COG)产品需要不同的电力供应以便向整合至COG产品中的电路提供电源。然而,对于缩减集成电路(integrated circuitIC)的尺寸而言,缩减IC布局导致电力线结构的宽度不够宽而不足以提供足够的驱动能力,或导致其被破坏。举例而言,图1绘示COG产品的布局,其包含电力供应部分110和接合在电力供应部分110上的电路部分120。如果线结构的一部分(例如,如标号112所表示)中发生破坏,且此破坏的线结构用以向电路部分120供应电源,那么这将导致电力供应的失效。
在另一情况下,如果线结构的宽度受到限制,且不能足够宽以提供充分的驱动能力,那么这也将导致电力供应失效。如图1所示,如果线结构用以向显示器提供伽马驱动参考电压(gamma driving reference voltage,GVDD)、栅极驱动器供电电压(VGH)或源极驱动器供电电压(AVDD)和其他用于显示的电压,那么线结构的驱动能力是显示器的重要问题。如果电力线的宽度太小(例如,11微米),那么由于电力线的驱动能力不足而将发生成品率损失。
发明内容
本发明提出一种改进从印刷电路板到所接合的IC装置的信号路径的驱动能力的新颖结构。
在一实施例中,本发明介绍一种适于接合到集成电路装置的印刷电路板的布局。此布局包含:第一金属层,其配置在第一绝缘层中,以及第二金属层,其配置在第一绝缘层上方的第二绝缘层中。第一金属层与第二金属层通过填充有导电材料的多个接触孔而彼此连接,且经排列以在印刷电路的接垫结构区和线结构区中实质上彼此平行。已连接的第一金属层和第二金属层用以作为从印刷电路板到所接合的集成电路装置的信号路径。
在上述的印刷电路板的布局中,印刷电路板是柔性印刷电路板。
在上述的印刷电路板的布局中,接触孔的导电材料与第二金属层的材料相同。
在上述的印刷电路板的布局中,还包含栅绝缘层,且第一金属层配置在栅绝缘层上。
在上述的印刷电路板的布局中,在接垫结构区中,第二金属层为曝露,且铟锡氧化物(ITO)层配置在第二金属层上。
在上述的印刷电路板的布局中,第一绝缘层是层间介电层。
在上述的印刷电路板的布局中,第二绝缘层是平坦化层。
为让本发明之上述和其他目的、特征和优点能更明显易懂,下文特举优选实施例,并配合附图,作详细说明如下。
附图说明
图1是COG产品的布局的方块图,其包含电力供应部分和接合在电力供应部分上的电路部分。
图2A和图2B分别绘示包含至少接垫结构200A和线结构部分200B的FPC(柔性印刷电路)板的已知布局结构的横截面图。
图3A和图3B分别绘示一实施例的印刷电路板的布局结构的横截面图。附图标记说明
40:接触窗
110:电力供应部分
112:线结构的一部分
120:电路部分
200A:接垫结构
200B:线结构部分
210:栅绝缘层
212:接垫结构区
220:层间介电层
222:第一金属层
230:平坦化层
232:第二金属层
240:铟锡氧化物层
300:柔性印刷电路板
300A:接垫结构
300B:线结构部分
310:栅绝缘层
312:接垫结构区
320:层间介电层
322:第一金属层
330:平坦化层
332:第二金属层
340:铟锡氧化物层
具体实施方式
请参看2A和图2B,其分别绘示包含至少接垫结构200A和线结构部分200B的柔性印刷电路板(Flexible Printed Circuit,FPC)的已知布局结构的横截面图。在现有技术中,FPC板视需要具有多个接垫结构和线结构。FPC接垫结构200A包含形成在多个堆叠绝缘层之间的第一金属层222和第二金属层232。如图2A所示,第一金属层222(称为“metal 1 layer”且表示为“M1”)在接垫结构区212内由层间介电(inter-layer dielectric,ILD)层220所覆盖并形成在栅绝缘(gate insulation,GI)层210上。第二金属层232(称为“metal2 layer”且表示为“M2”)形成在平坦化(planarization,PLN)层230中。FPC接垫结构200A进一步包含在第二金属层232上方的铟锡氧化物(IndiumTin Oxide,ITO)层240。线结构部分200B包含线结构,其为耦合到电力供应以提供电力的图案化第二金属层(M2)232。
当FPC板接合到集成电路装置(例如,驱动器)的接垫时。从电力供应到所连接的IC装置的信号路径经由第二金属线(M2)232,而不是第一金属线222。如果为了缩减尺寸的设计而将第二金属线(M2)232的宽度限制为预限值,那么这将导致驱动能力出现某些问题。为了避免此问题,本发明提出一种改进从FPC板到所接合的IC装置的线结构的驱动能力的新颖结构。
请参看3A和图3B,其分别绘示一实施例的印刷电路板300(例如,柔性印刷电路(FPC)板)的布局结构的横截面图。FPC板300至少包含接垫结构300A和线结构部分300B。FPC板300视需要具有用于接合到集成电路装置的多个接垫结构,和用于向所接合的集成电路装置提供电力供应的多个线结构。然而,为便于解释,本实施例介绍一个接垫结构300A和一个线结构部分300B。
在图3A中,FPC接垫结构300A包含形成在多个堆叠绝缘层之间的第一金属层322和第二金属层332。第一金属层322(称为“metal 1 layer”且表示为“M1”)例如由钼(Mo)材料制成。第一金属层322由层间介电(ILD)层320所覆盖并形成在栅绝缘(GI)层310上,但不限于仅形成在接垫结构区312内。第二金属层332(称为“metal 2 layer”且表示为“M2”)由钼/铝/钼(Mo/Al/Mo)材料堆叠所形成并形成在平坦化(PLN)层330中。FPC接垫结构300A进一步包含第二金属层332上方的铟锡氧化物(ITO)层340
线结构部分300B包含线结构,其为耦合到电力供应以提供电力的图案化第二金属层(M2)332。第一金属层322和第二金属层332经排列而彼此电性耦合,且在从FPC板300到所接合的集成电路装置的整个信号路径中布局成彼此平行。也就是说,在接垫结构区312与其他区域中,第一金属层322与第二金属层332通过填充有与第二金属层332材料相同的多个接触窗而彼此电耦合。过程如下。在栅绝缘(GI)层310上形成第一金属层322。接着,在第一金属层322上形成ILD层320。接着,例如通过光刻工艺(photolithography process)与掩模图案化ILD层320,以形成接触窗40,其曝露第一金属层322的一部分。接着,在ILD层320上形成第二金属层332,并填充在接触窗40中。也就是说,不需要另外的材料来填充接触窗40
假定第一金属层322的电阻是R1,且第二金属层332的电阻是R2。从理论的观点来看,如果从FPC板300到所接合的集成电路装置的信号路径仅经由第二金属层332,那么信号路径的电阻R为R2。然而,如果从FPC板300到所接合的集成电路装置的信号路径经由第一金属层322和第二金属层332,那么信号路径的电阻R为R=(R1×R2)/R1+R2。信号路径的电阻R必定小于R2。如果信号路径的电阻显著减小,那么从FPC板300到所接合的集成电路装置的信号路径的驱动能力也得到显著改进和增强。
虽然本发明已以优选实施例披露如上,然其并非用以限定本发明,任何本领域的技术人员,在不脱离本发明之精神和范围内,当可作些许之更动与润饰,因此本发明的保护范围当视权利要求所界定者为准。
Claims (7)
1.一种印刷电路板的布局,适于接合到集成电路装置上,该印刷电路板的布局包括:
第一金属层,配置于第一绝缘层中;以及
第二金属层,配置于该第一绝缘层上方的一第二绝缘层中,其中该第一金属层与该第二金属层通过填充导电材料所形成的多个接触窗而彼此连接,且经排列以在该印刷电路的接垫结构区和线结构区中实质上彼此平行,其中已连接的该第一金属层和该第二金属层用以作为从该印刷电路板到所接合的该集成电路装置的信号路径。
2.如权利要求1所述的印刷电路板的布局,其中该印刷电路板是柔性印刷电路板。
3.如权利要求1所述的印刷电路板的布局,其中该接触窗的该导电材料与该第二金属层的材料相同。
4.如权利要求1所述的印刷电路板的布局,更包括一栅绝缘层,且该第一金属层配置在该栅绝缘层上。
5.如权利要求1所述的印刷电路板的布局,其中在该接垫结构区中,该第二金属层为曝露,且铟锡氧化物层配置在该第二金属层上。
6.如权利要求1所述的印刷电路板的布局,其中该第一绝缘层是层间介电层。
7.如权利要求1所述的印刷电路板的布局,其中该第二绝缘层是平坦化层。
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US11/508,057 US7615706B2 (en) | 2006-08-21 | 2006-08-21 | Layout of a printed circuit board |
US11/508,057 | 2006-08-21 |
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CN101132667A true CN101132667A (zh) | 2008-02-27 |
CN100548086C CN100548086C (zh) | 2009-10-07 |
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US (1) | US7615706B2 (zh) |
CN (1) | CN100548086C (zh) |
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TW201044284A (en) * | 2009-06-09 | 2010-12-16 | Egis Technology Inc | Image sensing device adapted to flat surface design |
KR101710862B1 (ko) | 2009-08-05 | 2017-02-28 | 씬 필름 일렉트로닉스 에이에스에이 | 인쇄된 전자장치를 위한 인쇄-적합 디자인 및 레이아웃 |
US9651585B2 (en) | 2013-12-18 | 2017-05-16 | National Instruments Corporation | Via layout techniques for improved low current measurements |
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US5339217A (en) * | 1993-04-20 | 1994-08-16 | Lambda Electronics, Inc. | Composite printed circuit board and manufacturing method thereof |
US20030213617A1 (en) * | 2002-05-20 | 2003-11-20 | Subramanian Karthikeyan | Method and structure of a reducing intra-level and inter-level capacitance of a semiconductor device |
CN2532661Y (zh) | 2002-03-12 | 2003-01-22 | 威盛电子股份有限公司 | 供封装件固接于印刷电路板的弹性介质体 |
JP4170033B2 (ja) * | 2002-07-15 | 2008-10-22 | 株式会社 日立ディスプレイズ | 液晶表示装置 |
TW594168B (en) | 2003-04-11 | 2004-06-21 | Toppoly Optoelectronics Corp | Liquid crystal display panel |
US7459781B2 (en) * | 2003-12-03 | 2008-12-02 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
-
2006
- 2006-08-21 US US11/508,057 patent/US7615706B2/en not_active Expired - Fee Related
- 2006-12-29 CN CN200610170463.8A patent/CN100548086C/zh not_active Expired - Fee Related
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US20080041616A1 (en) | 2008-02-21 |
CN100548086C (zh) | 2009-10-07 |
US7615706B2 (en) | 2009-11-10 |
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