CN101124672A - 非易失性半导体存储装置 - Google Patents
非易失性半导体存储装置 Download PDFInfo
- Publication number
- CN101124672A CN101124672A CNA2005800484776A CN200580048477A CN101124672A CN 101124672 A CN101124672 A CN 101124672A CN A2005800484776 A CNA2005800484776 A CN A2005800484776A CN 200580048477 A CN200580048477 A CN 200580048477A CN 101124672 A CN101124672 A CN 101124672A
- Authority
- CN
- China
- Prior art keywords
- diffusion layer
- transistor
- nonvolatile semiconductor
- memory
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000009792 diffusion process Methods 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims description 18
- 108010041952 Calmodulin Proteins 0.000 claims description 15
- 102000000584 Calmodulin Human genes 0.000 claims description 14
- 230000001413 cellular effect Effects 0.000 claims description 8
- 239000002784 hot electron Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000013500 data storage Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000004043 responsiveness Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
Description
Claims (9)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2005/002550 WO2006087796A1 (ja) | 2005-02-18 | 2005-02-18 | 不揮発性半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101124672A true CN101124672A (zh) | 2008-02-13 |
CN101124672B CN101124672B (zh) | 2014-07-30 |
Family
ID=36916212
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200580048477.6A Expired - Fee Related CN101124672B (zh) | 2005-02-18 | 2005-02-18 | 非易失性半导体存储装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7486533B2 (zh) |
JP (1) | JP4679569B2 (zh) |
CN (1) | CN101124672B (zh) |
WO (1) | WO2006087796A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108364955A (zh) * | 2012-08-30 | 2018-08-03 | 美光科技公司 | 具有通过控制栅极的连接件的存储器阵列 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7042047B2 (en) * | 2004-09-01 | 2006-05-09 | Micron Technology, Inc. | Memory cell, array, device and system with overlapping buried digit line and active area and method for forming same |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US9553048B1 (en) * | 2015-09-04 | 2017-01-24 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method of semiconductor device |
CN108806751B (zh) * | 2017-04-26 | 2021-04-09 | 中芯国际集成电路制造(上海)有限公司 | 多次可程式闪存单元阵列及其操作方法、存储器件 |
JP7143326B2 (ja) * | 2017-12-20 | 2022-09-28 | タワー パートナーズ セミコンダクター株式会社 | 半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5274588A (en) * | 1991-07-25 | 1993-12-28 | Texas Instruments Incorporated | Split-gate cell for an EEPROM |
US5406514A (en) * | 1991-12-21 | 1995-04-11 | Kawasaki Steel Corporation | Semiconductor memory |
JP2805667B2 (ja) * | 1991-12-24 | 1998-09-30 | 川崎製鉄株式会社 | 半導体記憶装置 |
JP3450467B2 (ja) * | 1993-12-27 | 2003-09-22 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
KR100246782B1 (ko) * | 1996-08-30 | 2000-03-15 | 김영환 | 메모리 셀 어레이 |
CN100359601C (zh) * | 1999-02-01 | 2008-01-02 | 株式会社日立制作所 | 半导体集成电路和非易失性存储器元件 |
US7020018B2 (en) * | 2004-04-22 | 2006-03-28 | Solid State System Co., Ltd. | Nonvolatile memory device and method for fabricating the same |
-
2005
- 2005-02-18 WO PCT/JP2005/002550 patent/WO2006087796A1/ja not_active Application Discontinuation
- 2005-02-18 CN CN200580048477.6A patent/CN101124672B/zh not_active Expired - Fee Related
- 2005-02-18 JP JP2007503535A patent/JP4679569B2/ja not_active Expired - Fee Related
-
2007
- 2007-08-16 US US11/889,775 patent/US7486533B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108364955A (zh) * | 2012-08-30 | 2018-08-03 | 美光科技公司 | 具有通过控制栅极的连接件的存储器阵列 |
US11398489B2 (en) | 2012-08-30 | 2022-07-26 | Micron Technology, Inc. | Memory array having connections going through control gates |
CN108364955B (zh) * | 2012-08-30 | 2022-11-29 | 美光科技公司 | 具有通过控制栅极的连接件的存储器阵列 |
Also Published As
Publication number | Publication date |
---|---|
CN101124672B (zh) | 2014-07-30 |
JP4679569B2 (ja) | 2011-04-27 |
US20070296017A1 (en) | 2007-12-27 |
JPWO2006087796A1 (ja) | 2008-07-03 |
US7486533B2 (en) | 2009-02-03 |
WO2006087796A1 (ja) | 2006-08-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081024 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20081024 Address after: Tokyo, Japan, Japan Applicant after: Fujitsu Microelectronics Ltd. Address before: Kanagawa Applicant before: Fujitsu Ltd. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: SUOSI FUTURE CO., LTD. Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20150511 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150511 Address after: Kanagawa Patentee after: Co., Ltd. Suo Si future Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140730 Termination date: 20170218 |
|
CF01 | Termination of patent right due to non-payment of annual fee |