CN101123248A - 具有改进的热性能的半导体封装 - Google Patents

具有改进的热性能的半导体封装 Download PDF

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CN101123248A
CN101123248A CNA2006101720471A CN200610172047A CN101123248A CN 101123248 A CN101123248 A CN 101123248A CN A2006101720471 A CNA2006101720471 A CN A2006101720471A CN 200610172047 A CN200610172047 A CN 200610172047A CN 101123248 A CN101123248 A CN 101123248A
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lead
chip adhesive
wires
many
semiconductor packages
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张晓天
张衍国
李文清
黄品豪
刘凯
孙明
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Alpha and Omega Semiconductor Ltd
Alpha and Omega Semiconductor Inc
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Abstract

本发明涉及一种复合半导体封装，该封装包括具有第一和第二芯片粘合区的引线框架，且第一和第二芯片粘合区之间具有大侧向分离，粘合到第一芯片粘合区的第一器件，粘合到第二芯片粘合区的第二器件，连接到第一芯片粘合区的多条第一引线，连接到第二芯片粘合区的多条第二引线，以及覆盖引线框架，第一和第二器件以及多条第一和第二引线的至少一部分的密封材料。该封装可以是具有共漏MOSFET对和IC的TSSOP－8复合封装。

Description

具有改进的热性能的半导体封装
技术领域
本发明总体涉及一种半导体封装，更具体地涉及一种经改进的封装热性能的引线框架结构的TSSOP-8(Thin Shrink Small Outline Package，薄型缩小尺寸外型封装)半导体封装。
背景技术
随着诸如蜂窝型通信产品，便携式数字助理和笔记本电脑的移动设备的不断增长的应用，各个电子元件和器件的尺寸，重量和成本成为对于成功设计的关键因素。通过提供具有与分立器件封装相同的小封装形式因素的复合器件或共封装器件，将多个电子器件集成到单个半导体封装中已经被用于上述目的。
在技术上已知将一对共漏结构的功率MOSFET(金属氧化物半导体场效应晶体管)与一个集成电路(IC)一起封装到TSSOP-8封装中。图1显示了一种这样的封装100，该封装100包括第一功率MOSFET 105，以共漏结构耦合到第一功率MOSFET 105的第二功率MOSFET 105，和IC 115。第一和第二功率MOSFET以及IC 115被显示粘合到单引线框架区120上。常规上第一和第二功率MOSFET 105和110用导电环氧树脂粘合到引线框架区120，而IC 115可用非导电环氧树脂粘合。可以设置多条引线125用以将封装100连接到印刷电路板(PCB)上。引线125可以延伸到密封材料体130外并提供向功率MOSFET的源极和栅极的接触区域和IC接触区域的连接。
与诸如封装100的复合器件或共封装器件的设计相关的问题是封装100内产生的热量可能负面影响第一和第二功率MOSFET 105和110以及IC 115的运行。通常，第一和第二功率MOSFET 105和110被设计成在具有150℃的上限的温度范围中运行，而IC 115被设计成在具有85℃的上限的温度范围中运行。在现有技术中已经产生了考虑到热传导和热发散的各种方案。
参考图2，半导体封装200具有与引线框架区220熔合的引线205和210。所显示的结构提供了通过引线205和210的热发散路径，该热发散路径降低了半导体封装200的温度。对于热发散和热传导问题的其他解决方案包括将MOSFET和IC粘合到分开的引线框架区(未显示)。在该结构中，由MOSFET产生的热量在一定程度上与具有低于MOSFET的温度上限的IC隔绝。
半导体封装200显示了超过半导体封装100的经改进的热性能。在半导体封装100中，MOSFET的热阻被测量为213℃/W，IC的热阻被测量为208℃/W。当0.16W的功率被施加到MOSFET上时，MOSFET的温度被测量为59.1℃，IC的温度被测量为58.3℃。作为对照，半导体封装200的MOSFET的热阻被测量为210℃/W，IC的热阻被测量为206℃/W。当0.16W的功率被施加到MOSFET上时，MOSFET的温度被测量为58.6℃，IC的温度被测量为57.9℃，显示了半导体封装200的经改进的热性能。
虽然现有技术中已经实现了封装热性能的改进，但仍有对于具有经改进的热性能的复合TSSOP-8半导体封装的持续需要，还有对于具有附加的热发散路径的封装的需要。
发明内容
本发明的目的在于提供一种具有改进的热性能的半导体封装，尤其是TSSOP-8半导体封装。根据本发明提供的TSSOP-8半导体封装，其包括粘合到第一引线框架芯片区的共漏MOSFET对和粘合到第二引线框架芯片区的IC。第一和第二引线芯片框架区设置成互相分离一定距离以允许两者之间的密封材料数量增加，从而提供该封装的经改进的热性能。此外，一对引线被熔合到第一引线框架区，一条引线被熔合到第二引线框架区，以提供封装中的附加的热发散路径。
根据本发明的一个方面，半导体封装包括具有第一和第二芯片粘合区并且第一和第二芯片粘合区具有两者之间的大侧向分离的引线框架，粘合到第一芯片粘合区的第一器件，粘合到第二芯片粘合区的第二器件，连接到第一芯片粘合区的多条第一引线，连接到第二芯片粘合区的多条第二引线，以及覆盖引线框架，第一和第二器件以及该多条第一和第二引线的至少一部分的密封材料。
根据本发明的另一方面，TSSOP-8复合半导体封装包括引线框架，粘合到引线框架的第一芯片粘合区的共漏MOSFET对，粘合到引线框架的第二芯片粘合区的IC，连接到第一芯片粘合区的多条第一引线，连接到第二芯片粘合区的多条第二引线，以及覆盖引线框架，共漏MOSFET对，IC和多条第一和第二引线的至少一部分的密封材料，其中第一和第二芯片粘合区互相侧向分开一定距离，并且设置在第一和第二芯片粘合区之间的密封材料提供两者之间的热发散。
根据本发明的另一方面，TSSOP-8复合半导体封装包括具有第一和第二芯片粘合区的引线框架，粘合到第一芯片粘合区的第一器件，粘合到第二芯片粘合区的第二器件，连接到第一芯片粘合区的多条第一引线，连接到第二芯片粘合区的多条第二引线，以及覆盖引线框架，第一和第二器件和该多条第一和第二引线的至少一部分的密封材料，其中多条第一引线中的一部分引线被熔合到第一芯片粘合区，多条第二引线中的一条引线被熔合到第二芯片粘合区。
附图说明
图1是背景技术中的TSSOP-8半导体封装的示意图；
图2是背景技术中的另一种TSSOP-8半导体封装的示意图；
图3是本发明提供的TSSOP-8半导体封装的示意图；
图4是本发明提供的TSSOP-8半导体封装的具体实施例的示意图。
具体实施方式
为更好地理解本发明，以下结合图1-图4，详细说明本发明的较佳实施例，使得本发明的各种技术特征和技术效果对于本领域的技术人员将更显而易见。
本发明涉及了一种具有经改进的热性能的TSSOP-8半导体封装。通过提供具有设置成互相分离一定距离以允许两者之间的密封材料数量增加的第一和第二引线框架芯片区的封装而实现经改进的热性能。由于密封材料包括具有差导热性的材料，所增加数量的密封材料提供了分别粘合到第一和第二引线框架芯片区的共漏MOSFET和IC之间的热障。另外，熔合的引线提供了封装中的附加的热发散路径。
参考图3，图中显示的复合TSSOP-8半导体封装300包括以共漏结构耦合的一对MOSFET 305和310。MOSFET 305和310可以导电地粘合到第一引线框架芯片区320。IC 315可以粘合到第二引线框架芯片区330。第一和第二引线框架芯片区320和330的边缘可以通过减小第二引线框架芯片区330的尺寸而设置成互相之间有一定的距离“d”。密封材料390可覆盖MOSFET305和310，IC 315，连接导线以及第一和第二引线框架芯片区320和330以提供封装主体。密封材料390的数量可以使MOSFET 305和310与IC 315分开以提供MOSFET 305和310与IC 315之间的热障。由具有差导热性的材料构成的密封材料390的数量可用于提供MOSFET 305和310与IC 315之间的热发散屏障。
多条引线340可从密封材料390延伸用于连接到PCB。引线340a和340b可以熔合到第一引线框架芯片区320从而提供热发散路径。引线340c可以熔合到第二引线框架芯片区330从而提供另一条热发散路径。最后，源键合区域350a和350b可以增加面积，以能够使用附加的源键合导线360从而进一步减少封装300内产生热量。
半导体封装300显示了超过先有技术的半导体封装100和200的经改进的热性能。在半导体封装300中，MOSFET的热阻被测量为197℃/W，IC的热阻被测量为142℃/W。当0.16W的功率被施加到MOSFET时，MOSFET的温度被测量为56.5℃，IC的温度被测量为47.7℃。因此，半导体封装300实现了超过先有技术设计的经改进的热性能。
图4显示了一种根据本发明的复合TSSOP-8半导体封装400的替代实施例。作为与半导体封装300的对照，半导体封装400包括互相移位常规距离的第一和第二引线框架芯片区410和420。引线430a和430b可熔合到第一引线框架芯片区410，引线430c可熔合到第二引线框架芯片区420。在半导体封装400中，MOSFET的热阻被测量为196℃/W，IC的热阻被测量为162℃/W。当0.16W的功率被施加到MOSFET时，MOSFET的温度被测量为56.4℃，IC的温度被测量为50.9℃。这些结果确认了设置在半导体封装300的第一和第二引线框架芯片区320和330之间的经增加的距离“d”的效果，提高了封装中的热发散。
本发明的复合TSSOP-8半导体封装提供了具有经改进的热性能的封装。封装中的MOSFET和IC之间的经增加的密封材料的数量提供了该器件之间的热障。熔合到引线框架芯片粘合区的多条引线提供了附加的热发散路径。最后，经增加面积的源键合区域能够通过使用附加的键合导线进一步减少封装内产生热量。
应该理解的是，本发明在其应用中不限于上文叙述中阐明或附图中所示的功能性元件的细节和对这些元件的各种设置。本发明能够有其他的实施例并且以各种方式实施和进行。还有，应该理解的是，本文采用的措辞和术语以及摘要是为了叙述的目的，不应被认为是对本发明的限制。上文涉及了本发明的优选实施例，并且可以进行各种修改而不背离由附后的权利要求阐明的本发明的精神和范围。
因此，本领域的技术人员将理解，本发明引以为基础的概念可以被容易地利用为实施本发明的各种目的的其他方法和系统的设计基础。因此，重要的是，权利要求被认为包括不背离本发明的精神和范围的各种这样的等效结构。

Claims (14)

1.一种半导体封装，其特征在于，该半导体封装包括：
具有第一和第二芯片粘合区的引线框架，该第一和第二芯片粘合区之间具有大侧向分离；
粘合到第一芯片粘合区的第一器件；
粘合到第二芯片粘合区的第二器件；
连接到第一芯片粘合区的多条第一引线；
连接到第二芯片粘合区的多条第二引线；和
覆盖引线框架，第一和第二器件以及多条第一和第二引线的至少一部分的密封材料。
2.如权利要求1所述的半导体封装，其特征在于，所述的第一器件为共漏金属氧化物半导体场效应晶体管对。
3.如权利要求1所述的半导体封装，其特征在于，所述的第二器件为集成电路。
4.如权利要求1所述的半导体封装，其特征在于，所述的多条第一引线中的一部分引线被熔合到第一芯片粘合区。
5.如权利要求1所述的半导体封装，其特征在于，所述的多条第二引线中的一条引线被熔合到第二芯片粘合区。
6.如权利要求1所述的半导体封装，其特征在于，该半导体封装进一步还包括在密封材料中设置的增加了面积的源键合区域。
7.一种TSSOP-8复合半导体封装，其特征在于，该半导体封装包括：
引线框架；
粘合到引线框架的第一芯片粘合区的共漏金属氧化物半导体场效应晶体管对；
粘合到引线框架的第二芯片粘合区的集成电路；
连接到第一芯片粘合区的多条第一引线；
连接到第二芯片粘合区的多条第二引线；和
覆盖引线框架，共漏金属氧化物半导体场效应晶体管对，集成电路以及多条第一和第二引线的至少一部分的密封材料；以及
所述的第一和第二芯片粘合区互相侧向分开一定的距离，并且设置在第一和第二芯片粘合区之间的密封材料提供两个粘合区之间的热障。
8.如权利要求7所述的TSSOP-8复合半导体封装，其特征在于，所述的多条第一引线中的一对引线被熔合到第一芯片粘合区。
9.如权利要求7所述的TSSOP-8复合半导体封装，其特征在于，所述的多条第二引线中的一条引线被熔合到第二芯片粘合区。
10.如权利要求7所述的TSSOP-8复合半导体封装，其特征在于，该半导体封装进一步包括一对设置在密封材料内的源键合区域，该对源键合区域具有增加的面积以容纳增加数量的键合导线。
11.一种TSSOP-8复合半导体封装，其特征在于，该半导体封装包括：
具有第一和第二芯片粘合区的引线框架；
粘合到第一芯片粘合区的第一器件；
粘合到第二芯片粘合区的第二器件；
连接到第一芯片粘合区的多条第一引线，该多条第一引线中的一部分引线被熔合到第一芯片粘合区；
连接到第二芯片粘合区的多条第二引线，该多条第二引线中的一条引线被熔合到第二芯片粘合区；和
覆盖引线框架，第一和第二器件以及多条第一和第二引线的至少一部分的密封材料。
12.如权利要求11所述的TSSOP-8复合半导体封装，其特征在于，所述的第一器件包括共漏金属氧化物半导体场效应晶体管对。
13.如权利要求11所述的TSSOP-8复合半导体封装，其特征在于，所述的第二器件包括集成电路。
14.如权利要求11所述的TSSOP-8复合半导体封装，其特征在于，该半导体封装进一步包括设置在密封材料内的一对源键合区域，该对源键合区域具有增加的面积以容纳增加数量的键合导线。
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