CN101097367A - Liquid crystal display and method for fabricating the same - Google Patents

Liquid crystal display and method for fabricating the same Download PDF

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Publication number
CN101097367A
CN101097367A CNA2006101563926A CN200610156392A CN101097367A CN 101097367 A CN101097367 A CN 101097367A CN A2006101563926 A CNA2006101563926 A CN A2006101563926A CN 200610156392 A CN200610156392 A CN 200610156392A CN 101097367 A CN101097367 A CN 101097367A
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China
Prior art keywords
pixel portion
contact hole
circuit part
pattern
film
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Granted
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CNA2006101563926A
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Chinese (zh)
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CN100592180C (en
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金荣柱
李锡宇
朴秀婷
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LG Display Co Ltd
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LG Philips LCD Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Abstract

A liquid crystal display and a method for fabricating the same are disclosed. The method for fabricating a liquid crystal display includes preparing an insulating substrate defining a TFT region of a pixel portion, forming an active layer on the substrate to cover the TFT region of the pixel region, forming a gate electrode of the pixel portion on the active layer, forming a source region of the pixel portion and a drain region of the pixel portion in the active layer at both sides of the gate electrode of the pixel portion, forming a passivation film having first and second contact holes on the substrate having the drain region of the pixel portion, the first and second contact holes respectively exposing the source region of the pixel portion and the drain region of the pixel portion, sequentially forming a transparent conductive film and a metal film on the passivation film, and selectively etching the metal film and the transparent conductive film to form a source electrode pattern of the pixel portion/a source electrode of the pixel portion, which are sequentially deposited to cover the first contact hole, and a drain electrode pattern of the pixel portion/a drain electrode of the pixel portion, which are sequentially deposited to cover the second contact hole.

Description

LCD and manufacture method thereof
Disclosed content is involved in the No.10-2006-0061669 of korean patent application formerly and the No.10-2006-124001 of on June 30th, 2006 and submission on Dec 7th, 2006 among the present invention, is incorporated herein its full content as a reference.
Technical field
The present invention relates to a kind of LCD and manufacture method thereof, more specifically, relate to a kind of by reducing LCD and the manufacture method thereof that number of masks is simplified manufacturing process's step and improved output.
Background technology
In advanced information society, obtain paying attention to as the display of information transmission media.The key of research and development display is, slim body low to energy consumption, in light weight and demand that picture quality is high.As the LCD (LCD) of the main flow device in the flat-panel monitor (FPD), its performance can satisfy the demand and can carry out large-scale production.Therefore, made various new products based on LCD, and LCD as an alternative the critical piece of cathode ray tube (CRT) be widely used.
Usually, LCD shows required image according to image information by the transmittance that provides data-signal respectively to a plurality of liquid crystal displays that are arranged as matrix shape and control a plurality of liquid crystal displays.
LCD mainly uses the driven with active matrix pattern, and wherein amorphous silicon film transistor (a-SiTFT) is used on-off element, to drive the liquid crystal of pixel portion.
As the theory that LeComber created of 1979 Britain, since 1986, amorphous silicon film transistor has been applied to 3 " the liquid crystal mobile television in.Recently, developed 50 " or bigger large scale thin film transistor (TFT) LCD.Especially, because amorphous silicon film transistor satisfies the low temperature process step of using low-cost insulated substrate, therefore actively used.
Yet, because amorphous silicon film transistor 1cm 2The electron mobility of/Vsec, it is higher than to use in the high speed operation peripherals of 1MHz at needs and has restriction, like this, launched at using the research of integrated pixel portion and driving circuit section simultaneously on glass substrate of polysilicon (poly-Si) thin film transistor (TFT), wherein the field-effect mobility of polycrystalline SiTFT is higher than the field-effect mobility of amorphous silicon film transistor.
Owing to developed lcd color tv from nineteen eighty-two, polycrystalline SiTFT has been used in the small-sized module such as camcorder.Because polycrystalline SiTFT has the advantage of low sensitivity and high field effect mobility, so can on substrate, directly make driving circuit.
The increase of mobility can improve the operating frequency of the driving circuit section that is used for definite driving number of pixels.It makes display better.Equally, owing to can reduce the distortion of transmission signals by the duration of charging that reduces the pixel portion signal voltage, so might expect the improvement of picture quality.
In addition, compare, owing to polycrystalline SiTFT can be driven by the voltage less than 10V, so it has the advantage of low energy consumption with amorphous silicon film transistor with 25V high driving voltage.
To describe the structure of LCD with reference to figure 1 in detail hereinafter.
Fig. 1 is LCD in the prior art, the LCD of integrated drive electronics on array base palte particularly, structural plan figure.
As shown in Figure 1, LCD comprise colour filtering chip basic board 5, array base palte 10 and be formed at colour filtering chip basic board 5 and array base palte 10 between the liquid crystal layer (not shown).
Array base palte 10 comprises pixel portion 35 and driving circuit section 30, wherein pixel portion 35 is arranged as the image display area of matrix form for unit pixel, and driving circuit section 30 comprises data drive circuit 31 and grid driving circuit 32, and its periphery along pixel portion 35 is provided with.Though it is not shown, the pixel portion 35 of array base palte 10 comprises with vertical and horizontal direction and is arranged on many grid lines on the substrate 10 and data line to limit a plurality of pixel regions, be formed on grid line and the data line a plurality of thin film transistor (TFT)s at part place that intersect, and be formed at the pixel electrode in the pixel region.
Each thin film transistor (TFT) applies as on-off element or block signal voltage flows into pixel electrode, and the field effect transistor (FET) for using the electric field controls electric current to flow.
The driving circuit section 30 of array base palte 10 is positioned at the periphery of array base palte 10 pixel portion 35 more outstanding than colour filtering chip basic board 5.Data drive circuit 31 is positioned at the long limit of outstanding array base palte 10 and grid driving circuit 32 is positioned at the minor face of outstanding array base palte 10.
At this moment, in data drive circuit 31 and grid driving circuit 32, use thin film transistor (TFT) as complementary metal oxide semiconductor (CMOS) (CMOS) structure of converter correctly to export an input signal.
CMOS is a kind of integrated circuit of MOS structure of the thin film transistor (TFT) that is used for driving circuit section, this driving circuit section needs high speed signal to handle, CMOS needs n channel thin-film transistor and p channel thin-film transistor, and has other speed of intergrade and density feature corresponding to NMOS and PMOS.
Grid driving circuit 32 and data drive circuit 31 provide sweep signal and data-signal through grid line and data line to pixel electrode respectively.Because circuit 32 is connected with external signal input end (not shown) with 31, thereby it exports pixel electrode to through external signal input end control external signal input and with it.
In addition, the pixel portion 35 of colour filtering chip basic board 5 comprises the color filter (not shown) of Show Color, and the public electrode (not shown) that is formed on the comparative electrode that is used as pixel electrode in the substrate 10.
Have as above that the colour filtering chip basic board 5 and the array base palte 10 of structure have the box gap, so that it is spaced from each other by the wadding (not shown).Colour filtering chip basic board 5 and array base palte 10 are bonded to each other to form unit LCD plate by the seal pattern (not shown) that is formed on pixel portion 35 peripheries.At this moment, substrate 5 and 10 is bonded to each other by the bonding mark that is formed in colour filtering chip basic board 5 or the array base palte 10.
Because aforementioned LCD with driving circuit uses polycrystalline SiTFT, thereby it has the characteristics of excellent device property, preferable image quality, outstanding and low energy consumption.
Yet, should have n channel thin-film transistor and the p channel thin-film transistor that is formed on the single substrate owing to have the LCD of driving circuit, thereby its manufacturing process's step is more complicated more than manufacturing process's step of the amorphous silicon film transistor that only forms the single type raceway groove.
When manufacturing comprises the array base palte of thin film transistor (TFT), need repeatedly photo-mask process.
Photo-mask process comprises that the pattern transfer by will being printed on mask forms the series of processes step of required pattern to the substrate that deposits film, and wherein this series of processes step comprises coating, exposure and the developing procedure step of photoresist.Like this, because photo-mask process reduced output and increased the possibility of the thin film transistor (TFT) with defective, so can go wrong.
Especially,, increase, then increased the manufacturing cost of LCD accordingly if therefore be used for the number of masks of process because it is very expensive to be designed for the mask that forms pattern.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of LCD and manufacture method thereof, it has reduced number of masks to simplify manufacturing process's step and to improve output.
In order to realize these and other advantage and according to purpose of the present invention, as concrete and broad sense is described, provide a kind of method of making LCD here, comprising: the insulated substrate in the TFT zone of preparation qualification pixel portion; On substrate, form active layer to cover the TFT zone of pixel portion; On active layer, form the grid of pixel portion; The place, grid both sides that is positioned at pixel portion in active layer forms the source region of pixel portion and the drain region of pixel portion; Form the passivating film with first contact hole and second contact hole on the substrate in the drain region with pixel portion, described first contact hole and second contact hole expose the source region of pixel portion and the drain region of pixel portion respectively; Order forms nesa coating and metal film on passivating film; And metal film and nesa coating are forming the source electrode of sequential aggradation with the source electrode pattern/pixel portion of the pixel portion that covers first contact hole under the etching selectively, and sequential aggradation is with the drain electrode of the drain pattern/pixel portion of the pixel portion that covers second contact hole.
In another aspect of this invention, provide a kind of LCD, it comprises: by the insulated substrate of the TFT area limiting of pixel portion; Be formed on the described substrate active layer with the TFT zone that covers pixel portion; Be formed on the grid of the pixel portion on the described active layer; In active layer, be formed on the source region of pixel portion at grid both sides places of pixel portion and the drain region of pixel portion; Be formed on the substrate in the drain region with pixel portion and have the passivating film of first contact hole and second contact hole, described first contact hole and second contact hole expose the source region of pixel portion and the drain region of pixel portion respectively; Be deposited in order on the described passivating film source electrode, and be deposited in order on the described passivating film drain electrode with the drain pattern/pixel portion of the pixel portion that covers second contact hole with the source electrode pattern/pixel portion of the pixel portion that covers first contact hole.
In conjunction with the accompanying drawings, ensuing about detailed description of the present invention in, above-mentioned and other purposes of the present invention, characteristics, aspect and advantage will be more readily apparent from.
Description of drawings
Accompanying drawing provides further understanding of the present invention, and it is included in the instructions and constitutes the part of instructions, embodiments of the present invention is described and is used from elaboration principle of the present invention with instructions one.
In the accompanying drawings:
Fig. 1 is the planimetric map with existing LCD structure of driving circuit;
Fig. 2 is the partial plan according to the LCD array base palte of first embodiment of the invention;
Fig. 3 A to 3I is a sectional view of making process along the order that the line II-II ' among Fig. 2 extracts;
Fig. 4 is the partial plan according to the LCD array base palte of second embodiment of the invention;
Fig. 5 A to 5K is the sectional view that extracts along the line III-III ' among Fig. 4;
Fig. 6 is the planimetric map according to the pad portion of the LCD array base palte of second embodiment of the invention; And
Fig. 7 A to 7F is the sectional view that extracts along the line IV-IV ' among Fig. 6.
Embodiment
Describe preferred implementation of the present invention with reference to the accompanying drawings in detail.
Fig. 2 is the partial plan according to the LCD array base palte of first embodiment of the invention.Particularly, Fig. 2 has represented to comprise a pixel of the thin film transistor (TFT) of pixel portion.
Though actual LCD comprises M * N the pixel that is formed by N bar grid line and M bar data line, wherein grid line and data line intersect, and for brief description, have represented a pixel among Fig. 2.
As shown in Figure 2, comprise with vertical and horizontal direction according to the array base palte 110 of first embodiment of the invention and to be arranged on the substrate 110 grid line 116 and data line 117 with the qualification pixel region, be arranged on grid line 116 and data line 117 intersect the part thin film transistor (TFT), and the pixel electrode 118 that is formed in the pixel region and is connected with thin film transistor (TFT), its public electrode (not shown) together with colour filtering chip basic board drives the liquid crystal (not shown).
Thin film transistor (TFT) comprises the grid 121 that is connected with grid line 116, the source electrode 122 that is connected with data line, and the drain electrode 123 that is connected with pixel electrode 118.Thin film transistor (TFT) also comprises and uses the gate voltage be provided to grid 121 to form active patterns 124 ' at the source electrode 122 and the conducting channel between 123 that drains.
At this moment, the active patterns 124 ' of first embodiment is formed by polysilicon membrane, and part active patterns 124 ' extends to pixel region with the stored pattern 124 of forming first memory capacitance together with concentric line 108 " be connected.In other words, the concentric line 108 that is formed in the pixel region is identical with grid line 116 directions basically, and by inserting the stored pattern 124 that the first dielectric film (not shown) is overlapped in its below " to form first memory capacitance.At this moment, form the stored pattern 124 of first embodiment by the polysilicon membrane of storage doping formation active patterns 124 ' through independent mask process ".
Source electrode 122 and the drain electrode 123 first contact hole 140a and the second contact hole 140b source region and the drain region that are electrically connected on active patterns 124 ' in being respectively formed at first dielectric film and the second dielectric film (not shown).Equally,, and will partly drain and 123 extend to pixel region and be electrically connected on pixel electrode 118 forming segment data line 117 along a direction extension source electrode 122 with the 3rd contact hole 140 in being formed on the 3rd dielectric film (not shown).
At this moment, by inserting second dielectric film, the part drain electrode 123 that extends to pixel region is overlapped in the concentric line 108 of its below to form second memory capacitance.
Manufacturing process's step of above-mentioned array base palte is described with reference to figure 3A to 3I hereinafter.
Fig. 3 A to 3I is a sectional view of making process along the order that the line II-II ' among Fig. 2 extracts.The explanation that Fig. 3 A to 3I is exemplary have a manufacturing process of array base palte of the pixel portion of n channel TFT.
As shown in Figure 3A, form on such as the substrate 110 of the transparent insulation material of glass silicon thin film and then to its crystallization to form polysilicon membrane.At this moment, substrate 110 is limited by pixel portion and circuit part (not shown), and wherein pixel portion is divided into n channel TFT zone and storage area, and circuit part is divided into n channel TFT zone and p channel TFT zone.Then, this polysilicon membrane of etching is to form polysilicon film pattern 124, and it comprises active patterns and stored pattern (first mask process).At this moment, cushion 111 is clipped between substrate 110 and the polysilicon film pattern 124.
Shown in Fig. 3 B, polysilicon film pattern 124 carries out part by the independent mask (not shown) of photoresist and covers mixing, thereby forms stored pattern 124 ".The part polysilicon membrane 124 that is covered by photoresist forms active patterns 124 ' (second mask process).
Shown in Fig. 3 C, the first dielectric film 115a and first conducting film are formed on the whole surface of substrate 100 in proper order, and then selectively etching first conducting film going up the grid 121 that forms first conducting film at active patterns 124 ', and simultaneously at stored pattern 124 " go up the concentric line (the 3rd mask process) that forms first conducting film.
First conducting film is formed by low-resistance opaque conductive material, as aluminium (Al), Al alloy, tungsten (W), copper (Cu), chromium (Cr) and molybdenum (Mu), thereby forms grid 121 and concentric line 108.At this moment, in pixel region, by inserting the first dielectric film 115a, concentric line 108 is overlapped in the stored pattern 124 of its below " to form first memory capacitance.
Shown in Fig. 3 D, on substrate, form first barrier film 170 with grid 121 and concentric line 108.This first barrier film 170 is carried out composition with the whole surface of the array base palte 110 of covering pixel portion and the n channel TFT zone and the exposure p channel TFT zone of circuit part.Wherein, circuit part is not shown.Then, use first barrier film 170 as mask with the p channel TFT zone of highly doped p+ ion implantation circuit part to form p+ source region and drain region (not shown) (the 4th mask process).
Shown in Fig. 3 E, remove first barrier film.Subsequently, on substrate, form second barrier film 170 ' with p+ source region and drain region.Second barrier film 170 ' is carried out composition to cover the p channel TFT zone of circuit part, the part n channel TFT zone of pixel/circuit part, and storage area.Then, use second barrier film 170 ' highly doped n+ ion to be implanted the active patterns 124 ' of pixel portion, thereby in the active patterns 124 ' of pixel portion, form n+ source region 124a and drain region 124b (the 5th mask process) as mask.
Shown in Fig. 3 F, remove second barrier film 170 ', and then light dope n-ion is implanted the whole surface of the substrate 110 of having removed second barrier film, thereby form lightly doped drain (LDD) district 124I.In Fig. 3 F, Reference numeral 124c is illustrated in the channel region that forms conducting channel between source region 124a and the drain region 124b.In more detail, forming LDD district 124I between source region 124a and the channel region 124c and between drain region 124b and the channel region 124c.Simultaneously, though not shown, in the n of pixel portion channel TFT zone, form in the LDD district 124I, also with in the n channel TFT zone of n-ion implantation circuit part with formation LDD district.
Then, after the second dielectric film 115b is deposited on the whole surface of the substrate 110 with LDD district 124I, the first dielectric film 115a and the second dielectric film 115b are removed to form the first contact hole 140a and the second contact hole 140b by part, wherein the first contact hole 140a partly exposes source region 124a, and the second contact hole 140b partly exposes drain region 124b (the 6th mask process).
Shown in Fig. 3 G, on the whole surface of substrate 100, form second conducting film and be etched with formation then selectively and be electrically connected on the source electrode 122 of source region 124a and also form the drain electrode 123 (the 7th mask process) that is electrically connected on drain region 124b through the second contact hole 140b through the first contact hole 140a.
At this moment, the part source electrode 122 that extends pixel portion along a direction is to form data line 117, and by inserting the second insulation course 115b, the concentric line 108 that the part drain electrode 123 of pixel portion is extended to pixel region and be overlapped in its below is to form second memory capacitance.
Shown in Fig. 3 H, the 3rd insulation course 115c is deposited on the whole surface of substrate 110 and is etched with selectively then and form the 3rd contact hole 140c (the 8th mask process) that part exposes drain electrode 123.
Shown in Fig. 3 I, on the whole surface of the substrate 110 that is formed with the 3rd dielectric film 115c, form the 3rd conducting film, and be etched with formation is electrically connected on drain electrode 123 through the 3rd contact hole 140c pixel electrode 118 (the 9th mask process) then selectively.
The 3rd conducting film can be formed by the transparent conductive material with excellent transmissivity, and for example indium tin oxide (ITO) or indium-zinc oxide (IZO) are to form pixel electrode 118.
As mentioned above, in first embodiment of the present invention, form active patterns and storage electrode by polysilicon membrane, and be that stored pattern is stored doping, thereby can make the TFT of pixel portion and circuit part by whole nine mask process by the single-wheel mask process.
Fig. 4 is the planimetric map according to the LCD array base palte part of second embodiment of the invention.
As shown in Figure 4, comprise with vertical and horizontal direction setting grid line 213G and data line 240 according to the insulated substrate 201 of second embodiment of the invention with the qualification pixel region.Insulated substrate 201 is corresponding to array base palte.Be formed on the part that grid line 213G and data line 240 intersect as the thin film transistor (TFT) (TFT) of switching device, and be formed in the pixel region and be electrically connected on TFT as the drain pattern 219P2 of the pixel portion of pixel electrode, this pixel electrode drives the liquid crystal (not shown) together with the public electrode (not shown) of colour filtering chip basic board (not shown).
TFT comprises the grid 213G2 of pixel portion and the source electrode 221S1 and the drain electrode 221D1 of pixel portion, and wherein grid 213G2 is connected in grid line 213G, and source electrode 221S1 is connected in data line 240 with drain electrode 221D1.This TFT also comprises the first active layer 205P1A that uses the gate voltage that is provided to grid 213G2 and form conducting channel between source electrode 221S1 and drain electrode 221D1.The first active layer 205P1A is divided into the source region 205P1AS of pixel region and the drain region 205P1AD of pixel region.The part first active layer 2305P1A extends to pixel region (definite is storage area), and storage electrode 205S is formed on the extension of the first active layer 2305P1A.
In pixel region, form concentric line 213C along the basic direction identical with grid line 213G.Thereby by between concentric line 213C and storage electrode 205S, inserting the gate insulating film (not shown) concentric line 213C is overlapped in storage electrode 205S and forms memory capacitance.Concentric line 213C can carry out composition by the film identical with grid 213G.
The passivating film (not shown) is arranged on the substrate with concentric line 213C3.Form the first contact hole 215H1 and the second contact hole 215H2 in passivating film and gate insulating film, wherein the first contact hole 215H1 exposes the source region 205P1AS of the first active layer 205P1A and the drain region 205P1AD that the second contact hole 215H2 exposes pixel portion.Source electrode 221S1 and drain electrode 221D1 are electrically connected on source region 205P1AS and the drain region 205P1AD of the first active layer 205P1A respectively through the first contact hole 215H1 and the second contact hole 215H2.
The source electrode pattern 219P1 of pixel portion is inserted between source electrode 221S1 and the source region 205P1AS.Equally, drain pattern 219P2 is inserted between drain electrode 221D1 and the drain region 205P1AD.The drain pattern 219P2 of pixel portion is set to run parallel to pixel region.At this moment, the drain pattern 219P2 of pixel portion is corresponding to pixel electrode.
In other words, source electrode pattern 219P1 and drain pattern 219P2 are separately positioned on the source electrode 221S1 of pixel portion and the drain electrode 221D1 below of pixel portion.With identical film the drain pattern 219P2 of pixel portion and the source electrode pattern 219P1 of pixel portion are carried out composition.With nesa coating drain pattern 219P2 and source electrode pattern 219P1 are carried out composition.
Fig. 5 A to 5K is the sectional view that extracts along the line III-III ' among Fig. 4; Fig. 7 A to 7F is the sectional view that extracts along the line IV-IV ' among Fig. 6.Hereinafter, will describe the method for making LCD according to second embodiment of the invention in detail with reference to figure 5A to 5K and Fig. 7 A to 7F.
Shown in Fig. 5 A and 7A, preparation insulated substrate 201.In insulated substrate 201, limit pixel portion, circuit part, grid pad portion and potted line part respectively, wherein pixel portion is divided into n raceway groove (or p raceway groove) TFT zone and storage area, and circuit part is divided into n channel TFT zone and p channel TFT zone.Pixel portion can have n channel TFT and p channel TFT.For easy, next will the n channel TFT zone of pixel portion be described.Equally, circuit part can have n channel TFT and p channel TFT to form the CMOS structure.
Next, order forms cushion 203 and polysilicon film 205 on insulated substrate 201.Form polysilicon film 205 in the deposition mode identical with the crystalizing amorphous silicon film.Then, on substrate, form first barrier film 231 with polysilicon film 205.At this moment, first barrier film is formed the cover part active layer, this active layer is formed at respectively in the p channel TFT zone of the n channel TFT zone of n channel TFT zone, circuit part of pixel portion and circuit part.
Shown in Fig. 5 B, use first barrier film to come the etching polysilicon film forming the first poly-silicon pattern 205P1, the second poly-silicon pattern 205P2 and the 3rd poly-silicon pattern 205P3 of polysilicon film as mask, this first poly-silicon pattern 205P1, the second poly-silicon pattern 205P2 and the 3rd poly-silicon pattern 205P3 are formed at respectively in the p channel TFT zone of the n channel TFT zone of n channel TFT zone, circuit part of pixel portion and circuit part (first mask process).
Shown in Fig. 5 C, remove first barrier film.Subsequently, on substrate, form second barrier film 233 with first poly-silicon pattern, second poly-silicon pattern and the 3rd poly-silicon pattern.At this moment, second barrier film 233 is formed part first poly-silicon pattern that covers in the first poly-silicon pattern 205P1, the second poly-silicon pattern 205P2 and the 3rd poly-silicon pattern 205P3 and the exposure storage area.Then, use second barrier film 233 foreign ion to be doped in the substrate to form storage electrode 205S as mask.The first poly-silicon pattern 205P1A except that storage electrode 205S is corresponding to the active layer in the n channel TFT zone of pixel portion, the second poly-silicon pattern 205P2 is corresponding to the active layer in the n channel TFT zone of circuit part, and the 3rd poly-silicon pattern is corresponding to the active layer in p channel TFT zone.At this moment, the active layer in the active layer in the active layer in the n channel TFT zone of pixel portion, the n channel TFT zone of circuit part and the p channel TFT zone of circuit part is expressed as first active layer respectively, second active layer and the 3rd active layer (second mask process).
Shown in Fig. 5 D, remove second barrier film.Order forms gate insulating film 207, first metal film 213 and the 3rd barrier film 235 on the substrate with the first poly-silicon pattern 205P1, the second poly-silicon pattern 205P2 and the 3rd poly-silicon pattern 205P3.At this moment, gate insulating film 207 can be silicon oxide film (SiO 2).Equally, the 3rd barrier film 235 is formed n channel TFT zone and the part p channel TFT zone that covers pixel portion, circuit part.Then, use the 3rd barrier film 235 as the first grid 213G1 (three mask process) of mask etching first metal film with circuit part in the p of circuit part channel TFT zone.At this moment, because the n channel TFT zone of pixel portion and circuit part covered by second barrier film 233, so first metal film in the n channel TFT zone of pixel portion and circuit part is not patterned and maintain the original state.In addition, carve the etching work procedure that operation is carried out first metal film to wet.Thereby the first grid 231G1 of circuit part can be crossed etching at sidepiece.Remove the 3rd barrier film.Then, the substrate of first grid 213G1 with circuit part being carried out p+ mixes.As a result, in the 3rd active layer 205P3, form the first source region 205P3S of circuit part and the drain region 205P3D of circuit part.
Shown in Fig. 5 E, on the substrate of the drain region 205P3D of first source region 205P3S with circuit part and circuit part, form the 4th barrier film 237.At this moment, the 4th barrier film 237 forms the part and the p channel TFT zone of second grid in the n channel TFT zone of a part, circuit part of the concentric line of cover gate and pixel portion.
Shown in Fig. 5 F and Fig. 7 A, use remaining first metal film of the 3rd barrier film 237 etchings to form concentric line 213C and grid line with grid 213G2 of pixel portion.Simultaneously, in the n of circuit part channel TFT zone, form the second grid 213G2 of circuit part and in the grid welding disking area, form the first metal layer pattern 213G4 (the 4th mask process).At this moment, with wet the quarter remaining first metal film is carried out etching.As a result, etching can be crossed in its side of the grid 213G2 of pixel portion and circuit part concentric line 213C and second grid 213G3.
Then, the substrate with the 4th barrier film is carried out the n+ ion doping.The result, in the first active layer 205P1A of the down either side of the grid 213G2 of pixel portion, form the source region 205P1AS of pixel portion and the drain region 205P1AD of pixel portion, and in the active layer 205P2 of the down either side of the grid 213G3 of circuit part, form second source region 205P2S of circuit part and the second drain region 205P2D of circuit part.
Shown in Fig. 5 F, remove the 3rd barrier film, and use the grid 213G2 of pixel portion and the second grid 213G3 of circuit part LDD doping (n-) to be carried out on the whole surface of substrate then as mask.As a result, in the first active layer 205P1A, form a LDD district 205P1AL, and in the second active layer 205P2, form the 2nd LDD district 205P2L.It is identical with the CD deviation that wets that the one LDD district 205P1AL and the 2nd LDD district 205P2L form, and can be under the situation of no independent mask obtain an above-mentioned LDD district 205P1AL and the 2nd LDD district 205P2L by being mixed in the whole surface of substrate.
Shown in Fig. 5 G and 7B, on substrate, form passivating film 215 with a LDD district 205P1AL and the 2nd LDD district 205P2L.Silicon oxide film (SiO with the predefined procedure deposition 2) and silicon nitride film (SiN X) can be used as passivating film 221.At this moment, form passivating film 215 with following method: at the depositing silicon oxidation film with after carrying out activation annealing, the depositing silicon nitride film also carries out hydrogenation annealing (first method).Selectable, can following method form passivating film 215: order forms silicon oxide film and silicon nitride film and anneal then (second method).If form passivating film 215, can carry out the activation of silicon oxide film and the hydrogenation of silicon nitride film simultaneously by once annealing by second method.
Simultaneously, single silicon nitride film can be used as passivating film 215.As mentioned above, the present invention adopts and comprises the structure of silicon nitride film as passivating film 215.Like this, silicon nitride film can be used as the hydrogen source that carries out hydrogenation.
Yet, as mentioned above, if adopt silicon oxide film (SiO 2)/silicon nitride film (SiN X) structure or single silicon nitride film (SiN X) structure as passivating film 215, then compare with silicon oxide film with specific inductive capacity of 3.9 with same deposition thickness, specific inductive capacity and each unit area that silicon nitride film has 6.5-7.0 have higher electric capacity.Therefore, grid line and increase of the electrical effect between the data line and therefore signal delay increase in the above and below that is arranged at passivating film 215 respectively, thus can be in generation problem aspect high speed operation and the high resolving power.
In order to address the above problem, passivating film 215 can form silicon oxide film (SiO 2)/silicon nitride film (SiN X)/silicon oxide film (SiO 2) three-decker, the silicon oxide film that wherein has low-k is deposited on the silicon nitride film.If passivating film 215 adopts silicon oxide film (SiO 2)/silicon nitride film (SiN X)/silicon oxide film (SiO 2) three-decker, then the electric capacity of its each unit area is silicon oxide film (SiO less than the structure with same deposition thickness 2)/silicon nitride film (SiN X) or structure be silicon nitride film (SiN X).As a result, the electrical effect between grid line and data line reduce and therefore signal delay reduce, thereby can realize high speed operation or high resolving power.
Next, use single mask (not shown) etch passivation film and gate insulating film to form the first contact hole 215H1, the second contact hole 215H2, the 3rd contact hole 215H3, the 4th contact hole 215H4, the 5th contact hole 215H5 and the 6th contact hole 215H6 and opening portion 215O (the 5th mask process).The first contact hole 215H1 and the second contact hole 215H2 expose the source region 205P1AS and the drain region 205P1AD of pixel portion.Equally, second source region 205P2S of the 3rd contact hole 215H3 and the 4th contact hole 215H4 exposed circuits part and the second drain region 205P2D of circuit part.First source region 205P3S of the 5th contact hole 215H5 and the 6th contact hole 215H6 exposed circuits part and the first drain region 205P3D of circuit part.Opening portion 215O exposes the first metal layer pattern 213G4.
Next, on substrate, form isolating metal film 217 with contact hole 215H1,215H2,215H3,215H4,215H5 and 215H6 and opening portion 215O.At this moment, the molybdenum film is used as isolating metal film 217.In addition, isolating metal film 217 has the thickness of 300  to 700 , is preferably 500 .Then, deposition of barrier film 239 on substrate with isolating metal film 217.At this moment,, be preferably 2.0 μ m, then come deposition of barrier film 239 to the thickness of 1.0 μ m, be preferably 0.8 μ m with 0.5 μ m if passivating film has the thickness of 1.5 μ m to 2.5 μ m.
Shown in Fig. 5 H and 7C, form the 4th barrier film 239P by ashing barrier film 239.At this moment, form the 4th barrier film 239P being retained among the first contact hole 215H1, the second contact hole 215H2, the 3rd contact hole 215H3, the 4th contact hole 215H4, the 5th contact hole 215H5 and the 6th contact hole 215H6 and the opening portion 215O, and expose the upper surface of passivating film 215.Then,, carves by the substrate with the 4th barrier film 239P the isolating metal film of removing selectively on the passivating film 215 by being wet.As a result, form isolating metal film figure 217P to cover the first contact hole 215H1, the second contact hole 215H2, the 3rd contact hole 215H3, the 4th contact hole 215H4, the 5th contact hole 215H5 and the 6th contact hole 215H6 and opening portion 215O.At this moment, according to the thickness (＞2.0 μ m) of passivating film 215, isolating metal film figure 217P can form the bottom that covers the first contact hole 215H1, the second contact hole 215H2, the 3rd contact hole 215H3, the 4th contact hole 215H4, the 5th contact hole 215H5 and the 6th contact hole 215H6.Isolating metal film figure 217P is used for improving the contact resistance of the first drain region 205P3D of the first source region 205P3S of the second drain region 205P2S, circuit part of the second source region 205P2S, the circuit part of drain region 205PA1D, the circuit part of source region 205PA1S, the pixel portion of the nesa coating that will form thereafter, pixel portion and circuit part.
Shown in Fig. 5 I and 7D, remove the 4th barrier film, and on substrate, form nesa coating 219, second metal film 211 and dielectric film 233 then with isolating metal film figure 217P.Then, on substrate, use slit or half-tone mask (not shown) to form the 5th barrier film 241 with dielectric film 223.At this moment, the 5th barrier film 241 forms covering corresponding to the part of opening portion 215O and the first contact hole 215H1, the second contact hole 215H2, the 3rd contact hole 215H3, the 4th contact hole 215H4, the 5th contact hole 215H5 and the 6th contact hole 215H6 and make the n channel TFT zone of the p channel TFT zone of n channel TFT zone, circuit part of circuit part and pixel portion be thicker than the storage area and the grid pad portion of pixel portion.
Shown in Fig. 5 J and 7E, use the 5th barrier film as wet dielectric film, second metal film and the nesa coating carved of mask.Next, ashing the 6th barrier film also exposes dielectric film and second metal film (the 6th mask process) by the 5th barrier film pattern 241P of ashing then.As a result, in the n of pixel portion channel TFT zone, form the second insulating pattern 223P2 of sequential aggradation with the drain electrode 221D1/ pixel portion of the drain pattern 219P2/ pixel portion of the first insulating pattern 223P1 of the source electrode 221S1/ pixel portion of the source electrode pattern 219P1/ pixel portion of the pixel portion that covers the first contact hole 215H1 and the second contact hole 215H2 and pixel portion.Simultaneously, form the second insulating pattern 223P4 of sequential aggradation with the second drain electrode 221D2/ circuit part of the second drain pattern 219P4/ circuit part of the first insulating pattern 223P3 of the second source electrode 221S2/ circuit part of the second source electrode pattern 219P3/ circuit part of the circuit part that covers the 3rd contact hole 215H3 and the 4th contact hole 215H4 and circuit part.In addition, in the p of circuit part channel TFT zone, form the four insulating pattern 223P6 of sequential aggradation with the first drain electrode 221D3/ circuit part of the first drain pattern 219P6/ circuit part of the 3rd insulating pattern 223P5 of the first source electrode 221S3/ circuit part of the first source electrode pattern 219P5/ circuit part of the circuit part that covers the 5th contact hole 215H5 and the 6th contact hole 215H6 and circuit part.At this moment, the drain pattern 219P2 of pixel portion can be a pixel electrode.Simultaneously, in pad portion, form electrically conducting transparent film figure 219P7 to cover opening portion 215O.Electrically conducting transparent film figure 219P7 is connected with the first metal layer pattern 219G4 through opening portion 215O.
Simultaneously, the 4th insulating pattern 223P6 of the 3rd insulating pattern 223P5 of the second insulating pattern 223P4 of the first insulating pattern 223P3 of the second insulating pattern 223P2 of the first insulating pattern 223P1 of pixel portion, pixel portion, circuit part, circuit part, circuit part and circuit part is used for the electric capacity between box bonding process minimizing public electrode and colour filtering chip basic board.Therefore, can avoid liquid crystal retardation.
Shown in Fig. 5 K and 7F, remove the 5th barrier film of ashing and in the potted line part, form potted line 225 then.
As mentioned above, in second embodiment of the present invention, the process of making LCD comprises formation active layer (first mask process), form storage electrode (second mask process), in the p of circuit part channel TFT zone, form the first grid of circuit part, form the grid of pixel portion, the second grid of public electrode and circuit part (the 4th mask process), in passivating film, form contact hole and opening portion (the 5th mask process), and form by first drain electrode and the electrically conducting transparent film figure (the 6th mask process) of the first drain pattern/circuit part of first source electrode of first source electrode pattern/circuit part of second drain electrode of the second drain pattern/circuit part of second source electrode of second source electrode pattern/circuit part of the drain electrode of the drain pattern/pixel portion of the source electrode of the source electrode pattern/pixel portion of the pixel portion of sequential aggradation and pixel portion and circuit part and circuit part and circuit part and circuit part.Therefore, can compare the CMOS structure that realizes six masks in high aperture.
Has following advantage according to LCD of the present invention and manufacture method thereof.
Use single mask to form pixel electrode and source/drain by the diffraction exposure process.Therefore, reduce the number of masks that is used to make thin film transistor (TFT), and reduced manufacturing process's step and manufacturing cost thus.
In the present invention, because the electrically conducting transparent film figure is formed in the periphery of potted line part and grid pad portion, the defective that is caused by corrosion can be minimized thus.
Because the present invention can implement in many ways under the situation that does not break away from the spirit and scope of the present invention, therefore be understandable that above-mentioned embodiment is not limited to the content in the above-mentioned explanation, unless special the qualification, but it can spirit and scope defined by the claims be explained, and therefore, the invention is intended to cover improvement and modification within all scopes that fall into appended claims and equivalent thereof.

Claims (36)

1, a kind of method of making LCD comprises:
Preparation is limited with the insulated substrate in the TFT zone of pixel portion;
On substrate, form active layer to cover the TFT zone of pixel portion;
On active layer, form the grid of pixel portion;
The grid both sides that are positioned at pixel portion in active layer form the source region of pixel portion and the drain region of pixel portion;
Form the passivating film with first contact hole and second contact hole on the substrate in the drain region with pixel portion, described first contact hole and second contact hole expose the source region of pixel portion and the drain region of pixel portion respectively;
Order forms nesa coating and metal film on passivating film; And
Metal film and nesa coating are forming the source electrode of sequential aggradation with the source electrode pattern/pixel portion of the pixel portion that covers first contact hole under the etching selectively, and sequential aggradation is with the drain electrode of the drain pattern/pixel portion of the pixel portion that covers second contact hole.
2, method according to claim 1 is characterized in that, also is included in before the grid that forms pixel portion having on the substrate of active layer and forms gate insulating film.
3, method according to claim 1 is characterized in that, forms passivating film by deposition and hydrogenation annealing silicon nitride film on deposition and activation annealing silicon oxide film and the silicon oxide film in this activation on the substrate in the drain region with pixel portion.
4, method according to claim 1, it is characterized in that, by forming silicon oxide film and silicon nitride film and behind this silicon oxide film of annealing and silicon nitride film, carry out the activation of described silicon oxide film simultaneously and the hydrogenation of silicon nitride film forms described passivating film having on the substrate in drain region order.
5, method according to claim 1 is characterized in that, by forming silicon oxide film, silicon nitride film and silicon oxide film and form described passivating film having on the substrate in drain region order.
6, method according to claim 1 is characterized in that, also is included in to form the isolating metal pattern of filling in described first contact hole and second contact hole after forming described passivating film.
7, method according to claim 6, it is characterized in that, by form on the passivating film isolating metal film with cover described first contact hole and second contact hole, have deposition of barrier film on the substrate of isolating metal film, the described barrier film of ashing forms described isolating metal pattern to form to expose the isolating metal film and remain in the isolating metal film that barrier film pattern in described first contact hole and second contact hole, etching expose by the barrier film pattern and remove this barrier film pattern.
8, method according to claim 7 is characterized in that, described isolating metal film is formed by the molybdenum film.
9, method according to claim 7 is characterized in that, the thickness of described isolating metal film is 0.5 μ m to 0.1 μ m.
10, method according to claim 1 is characterized in that, forms the drain electrode of the drain pattern/pixel portion of the source electrode of source electrode pattern/pixel portion of described pixel portion and pixel portion by the diffraction exposure of using single mask.
11, method according to claim 1 is characterized in that, also is included in the described metal film of formation and forms dielectric film afterwards on this metal film.
12, method according to claim 11, it is characterized in that, also be included in before described metal film of etching and the nesa coating, the described dielectric film of etching is to form second insulating pattern of pixel portion in first insulating pattern that forms pixel portion on the source electrode of pixel portion and the drain electrode in pixel portion selectively.
13, a kind of method of making LCD comprises:
The preparation insulated substrate, described insulated substrate is limited with TFT zone, the grid welding disking area of pixel portion and is arranged on the TFT zone of pixel portion and the potted line zone between the grid welding disking area;
On substrate, form active layer to cover the TFT zone of pixel region;
On active layer, form the grid of pixel portion;
Form the grid pad in source region that forms pixel portion on the active layer and while on the grid welding disking area at substrate;
The place, grid both sides that is positioned at pixel portion in active layer forms the source region of pixel portion and the drain region of pixel portion;
On the substrate in drain region, form passivating film with first contact hole and second contact hole and opening portion with pixel portion, described first contact hole and second contact hole expose the source region of pixel portion and the drain region of pixel portion respectively, and described opening portion exposes described grid pad;
Order forms nesa coating and metal film on passivating film; And
Selectively under the etching metal film and nesa coating with form sequential aggradation with the source electrode of the source electrode pattern/pixel portion of the pixel portion that covers first contact hole, sequential aggradation with the drain electrode of the drain pattern/pixel portion of the pixel portion that covers second contact hole and sequential aggradation metal film pattern with the electrically conducting transparent film figure/pad portion of the pad portion that covers opening portion and potted line zone.
14, method according to claim 13, it is characterized in that, also be included in after the metal film pattern of the electrically conducting transparent film figure/pad portion that forms pad portion, the metal film pattern of this pad portion of etching to be exposing described potted line zone selectively, and forms potted line in described potted line zone.
15, method according to claim 13, it is characterized in that, by the expose metal film pattern of electrically conducting transparent film figure/pad portion of the drain electrode of drain pattern/pixel portion of the source electrode of source electrode pattern/pixel portion of forming described pixel portion and pixel portion and pad portion of the diffraction that uses single mask.
16, a kind of method of making LCD comprises:
The preparation insulated substrate, described insulated substrate is limited with the TFT zone and the circuit part of pixel portion, and described circuit part is divided into n channel TFT zone and p channel TFT zone;
In same plane, on described substrate, form first active layer, second active layer and TFT zone, n channel TFT zone and the p channel TFT zone of the 3rd active layer to cover pixel portion respectively;
On the 3rd active layer, form the first grid of pixel portion;
Place, the first grid both sides digital communication that is positioned at circuit part in the 3rd active layer forms first source region of circuit part and first drain region of circuit part;
On first active layer and second active layer, form the grid of pixel portion and the second grid of circuit part;
The grid both sides place that is positioned at pixel portion in first active layer forms the source region of pixel portion and the drain region of pixel portion, and the place, second grid both sides that is positioned at circuit part simultaneously in second active layer forms second source region of circuit part and second drain region of circuit part;
Form the passivating film with first contact hole, second contact hole, the 3rd contact hole, the 4th contact hole, the 5th contact hole and the 6th contact hole on the substrate in second drain region with circuit part, described first contact hole, second contact hole, the 3rd contact hole, the 4th contact hole, the 5th contact hole and the 6th contact hole expose the source region of pixel portion, the drain region of pixel portion, second source region of circuit part, second drain region of circuit part, first source region of circuit part and first drain region of circuit part respectively;
Order forms nesa coating and metal film on passivating film; And
Affiliated metal film of etching and nesa coating are to form sequential aggradation to cover first selectively, the source electrode of the source electrode pattern/pixel portion of the pixel portion of the 3rd and the 5th contact hole, the first source electrode pattern of second source electrode of second source electrode pattern/circuit part of circuit part and first source electrode pattern/circuit part of circuit part, and form sequential aggradation simultaneously to cover second, the drain electrode of the drain pattern/pixel portion of the pixel portion of the 4th and the 6th contact hole, first drain electrode of second drain pattern of second drain pattern of circuit part/circuit part and the first drain pattern/circuit part of circuit part.
17, method according to claim 16 is characterized in that, also is included in the described passivating film of formation and forms the isolating metal pattern of filling in described first contact hole and second contact hole afterwards.
18, method according to claim 17, it is characterized in that, by form on the passivating film isolating metal film with cover described first contact hole and second contact hole, have deposition of barrier film on the substrate of isolating metal film, the described barrier film of ashing forms the barrier metal pattern to form to expose the isolating metal film and remain in the isolating metal film that barrier film pattern in described first contact hole and second contact hole, etching expose by the barrier film pattern and remove this barrier film pattern.
19, method according to claim 18 is characterized in that, described isolating metal film is that the molybdenum film of 0.5 μ m to 0.1 μ m forms by thickness.
20, method according to claim 16, it is characterized in that exposing to forming by first of the first drain pattern/circuit part of second drain pattern of the second drain pattern/circuit part of the drain electrode of the drain pattern/pixel portion of the first source electrode pattern of first source electrode pattern/circuit part of second source electrode of second source electrode pattern/circuit part of the source electrode of the source electrode pattern/pixel portion of the pixel portion of sequential aggradation, circuit part, circuit part, pixel portion, circuit part and circuit part by the diffraction that uses single mask drains.
21, a kind of LCD comprises:
The insulated substrate that is limited by the TFT zone of pixel portion;
Be formed on the described substrate active layer with the TFT zone that limits pixel portion;
Be formed on the grid of the pixel portion on the described active layer;
In described active layer, be formed on the source region of pixel portion of grid both sides of pixel portion and the drain region of pixel portion;
Be formed on the substrate in the drain region with pixel portion and have the passivating film of first contact hole and second contact hole, described first contact hole and second contact hole expose the source region of pixel portion and the drain region of pixel portion respectively;
Be deposited in order on the described passivating film with the source electrode of the source electrode pattern/pixel portion of the pixel portion that covers first contact hole and be deposited in order on the described passivating film drain electrode with the drain pattern/pixel portion of the pixel portion that covers second contact hole.
22, LCD according to claim 21 is characterized in that, also comprises being deposited on the gate insulating film on the described source electrode and being deposited on second insulating pattern in the described drain electrode.
23, LCD according to claim 21 is characterized in that, also comprises the gate insulating film between the grid that is inserted in described active layer and pixel portion.
24, LCD according to claim 21 is characterized in that, described passivating film is by monolayer silicon nitride film (SiN x), the silicon oxide film (SiO of sequential aggradation 2)/silicon nitride film (SiN x) and the silicon oxide film (SiO of sequential aggradation 2)/silicon nitride film (SiN x)/silicon oxide film (SiO 2) one of them formation.
25, LCD according to claim 21, it is characterized in that, also comprise be formed in described first contact hole and second contact hole and be inserted in the source region of pixel portion and the source electrode pattern between and the drain region of pixel portion and the isolating metal pattern between the drain pattern.
26, LCD according to claim 25 is characterized in that, described isolating metal pattern is formed by the molybdenum film.
27, LCD according to claim 21 is characterized in that, the drain pattern of the source electrode pattern/pixel portion of described pixel portion is formed by nesa coating, and the drain electrode of the source electrode/pixel portion of described pixel portion is formed by metal film.
28, LCD according to claim 21 is characterized in that, the drain pattern of described pixel portion is a pixel electrode.
29, a kind of LCD comprises:
Insulated substrate, its TFT zone, grid welding disking area and be arranged on the TFT zone of pixel portion and the potted line area limiting between the grid welding disking area by pixel portion;
Be formed on the described substrate active layer with the TFT zone that covers described pixel portion;
Be respectively formed on the grid welding disking area on the described substrate and active layer on grid and grid pad;
In active layer, be positioned at the source region of pixel portion at grid both sides places of pixel portion and the drain region of pixel portion;
The passivating film that on the substrate in drain region, has first contact hole and second contact hole and opening portion with pixel portion, described first contact hole and second contact hole expose the source region of pixel portion and the drain region of pixel portion respectively, and described opening portion exposes described grid pad;
Sequential aggradation with the source electrode of the source electrode pattern/pixel portion of the pixel portion that covers first contact hole, sequential aggradation with the drain electrode of the drain pattern/pixel portion of the pixel portion that covers second contact hole and the electrically conducting transparent film figure that covers the pad portion in opening portion and potted line zone.
30, LCD according to claim 29, it is characterized in that, also comprise be formed in first contact hole and second contact hole and be inserted in the source region of pixel portion and the source electrode pattern between and the drain region of pixel portion and the isolating metal pattern between the drain pattern.
31, LCD according to claim 30 is characterized in that, described isolating metal pattern is formed by the molybdenum film.
32, LCD according to claim 29, it is characterized in that, the electrically conducting transparent film figure of the source electrode pattern of described pixel portion, the drain pattern of pixel portion and pad portion is formed by nesa coating, and the drain electrode of the source electrode of described pixel portion and pixel portion is formed by metal film.
33, a kind of LCD comprises:
Insulated substrate, its TFT zone and circuit part by pixel portion limits, and described circuit part is divided into n channel TFT zone and p channel TFT zone;
First active layer on the same plane of described substrate, second active layer and the 3rd active layer, thus TFT zone, n channel TFT zone and the p channel TFT zone of pixel portion covered respectively;
Be respectively formed at the grid of the pixel portion on described first active layer, second active layer and the 3rd active layer and second and first grid of circuit part;
Be formed on the source region of pixel portion at the grid both sides place that is positioned at pixel portion in first active layer and the drain region of pixel portion, be formed on second source region of circuit part at the second grid both sides place that is positioned at circuit part in second active layer and second drain region of circuit part, and be formed on first source region of circuit part at the place, first grid both sides that is positioned at circuit part in the 3rd active layer and first drain region of circuit part;
Be formed on the passivating film on the substrate in first drain region with circuit part, described passivating film has first contact hole, second contact hole, the 3rd contact hole, the 4th contact hole, the 5th contact hole and the 6th contact hole in first drain region of first source region of second drain region, circuit part of second source region, the circuit part of drain region, the circuit part of the source region that exposes pixel portion respectively, pixel portion and circuit part; And
Be deposited in order on the described passivating film source electrode with the source electrode pattern/pixel portion of the pixel portion that covers first contact hole, deposit drain electrode in succession with the drain pattern/pixel portion of the pixel portion that covers second contact hole, sequential aggradation is with second source electrode of second source electrode pattern/circuit part of the circuit part that covers the 3rd contact hole, sequential aggradation is with second drain electrode of the second drain pattern/circuit part of the circuit part that covers the 4th contact hole, sequential aggradation is with first source electrode of first source electrode pattern/circuit part of the circuit part that covers the 5th contact hole, and sequential aggradation is with first drain electrode of the first drain pattern/circuit part of the circuit part that covers the 6th contact hole.
34, LCD according to claim 33, it is characterized in that, also comprise being filled in described first contact hole, second contact hole, the 3rd contact hole, the 4th contact hole, in the 5th contact hole and the 6th contact hole and be inserted in respectively between the source electrode pattern of the source region of pixel portion and pixel portion, between the drain region of pixel portion and the drain pattern of pixel portion, between the second source electrode pattern of second source region of circuit part and circuit part, between second drain region of circuit part and second drain pattern of circuit part, between the first source electrode pattern of first source region of circuit part and circuit part and the isolating metal pattern between first drain pattern of first drain region of circuit part and circuit part.
35, LCD according to claim 34 is characterized in that, described isolating metal pattern is formed by the molybdenum film.
36, LCD according to claim 33, it is characterized in that, second drain pattern of second source electrode pattern/circuit part of the drain pattern of the source electrode pattern/pixel portion of described pixel portion, circuit part, and first drain pattern of first source electrode pattern/circuit part of circuit part forms by nesa coating, and first drain electrode of the first source electrode/circuit part of second drain electrode of the second source electrode/circuit part of the drain electrode of the source electrode/pixel portion of described pixel portion, circuit part and circuit part is formed by metal film.
CN200610156392A 2006-06-30 2006-12-29 Liquid crystal display and method for fabricating the same Expired - Fee Related CN100592180C (en)

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