CN103972242B - A kind of manufacture method of array base palte, display device and array base palte - Google Patents
A kind of manufacture method of array base palte, display device and array base palte Download PDFInfo
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Abstract
The present invention relates to Display Technique field, disclose the manufacture method of a kind of array base palte, display device and array base palte, to improve yields and the reliability of product.This array base palte includes multiple gate pad, each gate pad includes: be positioned at the grid layer on underlay substrate, it is positioned at the gate insulator on described grid layer, it is positioned at the first transparency conducting layer on described gate insulator, it is positioned at the passivation layer on described first transparency conducting layer, and it is positioned at the second transparency conducting layer on described passivation layer, wherein, described grid layer includes gate solder region；Described gate insulator offers at least one first via being positioned at above described gate solder region；Described first transparency conducting layer is by each first via and described gate solder region conductive contact；Described passivation layer offers at least one second via, and described second transparency conducting layer is by each second via and described first transparency conducting layer conductive contact.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to the system of a kind of array base palte, display device and array base palte
Make method.
Background technology
At present, array base palte, as the Important Components of liquid crystal indicator, waited in module group assembling, environmental simulation test
Cheng Zhong, needs to be scanned the test of signal and data signal by its gate pad and source-drain electrode weld pad array substrate, with
Ensure the reliability of its electrology characteristic.
As it is shown in figure 1, the gate pad of existing array base palte includes the most successively: the grid layer being positioned on underlay substrate
10, gate insulator 11, source-drain electrode layer 13, passivation layer 14 and the second transparency conducting layer 15, wherein, grid layer 10 includes welding
Region, source-drain electrode layer 13 includes the source-drain electrode being positioned at above welding region, and gate insulator 11 includes making the second transparency conducting layer
15 include making the second transparency conducting layer 15 conduct electricity with source-drain electrode with the weld pad via 111 ' of welding region conductive contact, passivation layer 14
The passivation layer via hole 141 ' of contact.As can be seen from Figure, in the making and transportation of liquid crystal indicator, electrolyte pole
Easily infiltrate into the welding region of grid layer by second transparency conducting layer at weld pad via 111 ' place and corrode grid layer, Jin Erying
Ring the electric property of gate pad of array base palte, cause the reliability of product to reduce and even lost efficacy, especially transparent lead when second
When electric layer is indium tin oxide layer, owing to the hole of indium tin oxide layer self is relatively big, compactness is poor, and drawbacks described above is more serious.
Summary of the invention
The invention provides the manufacture method of a kind of array base palte, display device and array base palte, in order to improve product
Yields and reliability.
The array base palte that the present invention provides, including multiple gate pad, each described gate pad includes: be positioned at substrate
Grid layer on substrate, is positioned at the gate insulator on described grid layer, is positioned at first on described gate insulator
Transparency conducting layer, is positioned at the passivation layer on described first transparency conducting layer, and it is saturating to be positioned at second on described passivation layer
Bright conductive layer, wherein,
Described grid layer includes gate solder region；Described gate insulator offers and is positioned on described gate solder region
At least one first via of side；Described first transparency conducting layer is led with described gate solder region by each first via
Electrical contact；Described passivation layer offers at least one second via, and described second transparency conducting layer passes through each second via
With described first transparency conducting layer conductive contact.
In technical solution of the present invention, owing to the second transparency conducting layer of array base palte is by being positioned at above gate insulator
The first transparency conducting layer and gate solder region conductive contact, and not directly and gate solder region conductive contact, therefore, i.e.
Make the second transparency conducting layer at electrolyte cross the second via and the first transparency conducting layer that infiltration, the first transparency conducting layer to occur
The gate insulator of lower section can be effectively prevented electrolyte and infiltrate into grid layer further and the corrosion that causes grid layer, thus
The corrosion condition that effectively prevent gate pad occurs, and then improves yields and the reliability of product.
Further, described gate pad is the gate pad of integrated circuit, and the gate pad of described integrated circuit is also wrapped
Include between described first transparency conducting layer and described passivation layer and include being positioned at the source and drain above described gate solder region
The source-drain electrode layer of pole, at least one second via described does not exposes described source-drain electrode layer.
Preferably, this array base palte also includes multiple source-drain electrode weld pad, and each described source-drain electrode weld pad includes: be positioned at institute
State the first transparency conducting layer on gate insulator, be positioned at the source-drain electrode layer on described first transparency conducting layer, be positioned at institute
State the passivation layer on source-drain electrode layer, and be positioned at the second transparency conducting layer on described passivation layer, wherein,
Described source-drain electrode layer includes that source-drain electrode welding region, described passivation layer offer at least one and do not expose described source and drain
3rd via of pole layer, described second transparency conducting layer is led with described first transparency conducting layer by the 3rd via each described
Electrical contact.
Preferably, described first transparency conducting layer includes indium tin oxide layer, and/or, described second transparency conducting layer includes
Indium tin oxide layer.
Present invention also offers a kind of display device, including: the array base palte described in aforementioned arbitrary technical scheme.Due to this
In display device, the second transparency conducting layer in the gate pad of array base palte is saturating by being positioned at first above gate insulator
Bright conductive layer and gate solder region conductive contact, and not direct and gate solder region conductive contact, it is possible to be effectively prevented
On array base palte, the corrosion condition of each gate pad occurs, so the yields of this display device and reliability are higher.
The present invention also provides for the manufacture method of a kind of display floater, including:
Underlay substrate is formed the figure of the grid layer including gate solder region；
Formed on the figure of described grid layer include being positioned at above described gate solder region at least one first
The figure of the gate insulator of via；
Formed on the figure of described gate insulator and led with described gate solder region by each first via
The figure of the first transparency conducting layer of electrical contact；
The figure of the passivation layer including at least one the second via is formed on the figure of described first transparency conducting layer；
Formed on the figure of described passivation layer and conducted electricity with described first transparency conducting layer by each second via
The figure of the second transparency conducting layer of contact.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of prior art array base palte；
Fig. 2 is the array base palte one embodiment of the present invention plan structure schematic diagram near integrated circuit region；
Fig. 3 is the cross-section structure enlarged diagram of an embodiment at A in the array base palte shown in Fig. 2；
Fig. 4 is the cross-section structure enlarged diagram of another embodiment at A in the array base palte shown in Fig. 2；
Fig. 5 is the array base palte one embodiment of the present invention plan structure schematic diagram away from integrated circuit region；
Fig. 6 is the cross-section structure enlarged diagram of the array base palte shown in Fig. 5；
Fig. 7 is the cross-section structure enlarged diagram of an embodiment at B in the array base palte shown in Fig. 2；
Fig. 8 is the schematic flow sheet of the manufacture method of one embodiment of the invention array base palte.
Reference:
10-grid layer 11-gate insulator 111-the first via
12-the first transparency conducting layer 13-source-drain electrode layer 14-passivation layer
141-the second via 142-the 3rd via
15-the second transparency conducting layer 16-integrated circuit
111 '-weld pad via 141 '-passivation layer via hole
Detailed description of the invention
In order to improve yields and the reliability of product, embodiments provide a kind of array base palte, display device
And the manufacture method of array base palte.In this array base palte, gate pad includes the most successively: be positioned on underlay substrate
Include the grid layer in gate solder region, gate insulator, the first transparency conducting layer, passivation layer, and, the second electrically conducting transparent
Layer, gate insulator offers and is positioned at above gate solder region and makes the first transparency conducting layer to connect with gate solder region conduction
At least one first via touched；Passivation layer offers at least one and makes the second transparency conducting layer and the first transparency conducting layer conduction
Second via of contact.Second transparency conducting layer is by being positioned at the first transparency conducting layer above gate insulator and gate solder
Zone conducts current contacts, and not direct and gate solder region conductive contact, it is possible to it is effectively prevented on array base palte each grid
The corrosion condition of weld pad occurs, thus improves yields and the reliability of product.
The technical scheme that various embodiments of the present invention provide is illustrated below with reference to accompanying drawing.It should be noted that this
The feature such as relative distance between each functional film layer shown in bright accompanying drawing or thickness does not represent real distance and thickness, is only
For the present invention is described, it is not used in the restriction present invention.
As shown in Fig. 2～Fig. 6, wherein, Fig. 2 is the array base palte one embodiment of the present invention vertical view near integrated circuit region
Structural representation；Fig. 3 is the cross-section structure enlarged diagram of an embodiment at A in the array base palte shown in Fig. 2；Fig. 4 is that Fig. 2 shows
The cross-section structure enlarged diagram of another embodiment at A in the array base palte gone out；Fig. 5 is that array base palte one embodiment of the present invention is remote
Plan structure schematic diagram from integrated circuit region；Fig. 6 is the cross-section structure enlarged diagram of the array base palte shown in Fig. 5.
The array base palte that first embodiment of the invention is provided, including multiple gate pad, each gate pad includes:
Be positioned at the grid layer 10 on underlay substrate, be positioned at the gate insulator 11 on grid layer 10, be positioned at gate insulator 11 it
On the first transparency conducting layer 12, be positioned at the passivation layer 14 on the first transparency conducting layer 12, and be positioned on passivation layer 14
The second transparency conducting layer 15, wherein,
Grid layer 10 includes gate solder region；Gate insulator 11 offers and is positioned at above gate solder region at least
One the first via 111；First transparency conducting layer 12 is by each the first via 111 and gate solder region conductive contact；
Passivation layer 14 offers at least one second via 141, and the second transparency conducting layer 15 is by each second via 141 and first
Transparency conducting layer 12 conductive contact.
In the array base palte that the present embodiment provides, gate insulator 11 offers and is positioned at above gate solder region at least
One the first via 111, the first gate solder region, via 111 exposed portion so that the first transparency conducting layer 12 is by first
Via 111 and the gate solder region conductive contact of gate pad；Passivation layer 14 offers at least one second via 141, the
Two transparency conducting layers 15 pass through the second via 141 and the first transparency conducting layer 12 conductive contact being positioned on gate insulator 11,
Being staggeredly located of the first via 111 offered on the second via 141 that i.e. passivation layer 14 is offered and gate insulator 11.
In the manufacturing process of array base palte, owing to the second transparency conducting layer 15 of array base palte is by being positioned at gate insulator
The first transparency conducting layer 12 above layer 11 and gate solder region conductive contact, and directly do not connect with gate solder region conduction
Touch, therefore, even if oozing occur in the second transparency conducting layer 15 at electrolyte cross the second via 141 and the first transparency conducting layer 12
Thoroughly, the gate insulator 11 below the first transparency conducting layer 12 can be effectively prevented electrolyte and infiltrate into grid layer 10 further
And cause the corrosion of grid layer 10, thus the corrosion condition that effectively prevent gate pad occurs, and then improve the good of product
Product rate and reliability；
Further, the array base palte that the present embodiment provides can also be effectively prevented product in client owing to operation lack of standardization is led
The situation causing product corrosion occurs, and uses the array base palte that the present embodiment provides so that product is in production process and fortune simultaneously
The storage time during defeated is longer and is not susceptible to product corrosion, especially uses the cutting technique of open design, product when product
When product use antivacuum packaging or penetrate into interiors of products electrolyte (such as steam etc.) in transportation, the effect above is particularly
Substantially.
The quantity of the first via 111 does not limits, and can be one, it is also possible to for multiple, with reference to shown in Fig. 4, when the first via
When the quantity of 111 is multiple, it is possible to effectively increase the first transparency conducting layer 12 and the contact area in gate solder region, first
Transparency conducting layer 12 and the contact area of the second transparency conducting layer 15, thus reduce resistivity, and then decrease test signal
Line loss, further increases the reliability of product.
Gate pad generally includes the gate pad of the integrated circuit in the region being located close to integrated circuit 16 (in Fig. 2
Shown A) and the gate pad (as shown in Figure 5) in integrated circuit 16 region away from array base palte.
Shown in Fig. 2 and Fig. 3, when the gate pad in the present embodiment is located close to the integrated circuit 16 of array base palte
During (such as S/W tests circuit) region, when i.e. gate pad is the gate pad of integrated circuit, the gate pad of integrated circuit is also
Including between the first transparency conducting layer 12 and passivation layer 14 and include the source being positioned at the source-drain electrode above gate solder region
Drain electrode layer 13, at least one second via 141 does not exposes source-drain electrode layer 13.
Test circuit 16 output test signal to source-drain electrode, source-drain electrode and the first transparency conducting layer 12 conductive contact, first
The transparency conducting layer 12 first via 111 and the gate solder region conductive contact by gate insulator 11 so that test signal
Layer is changed to the gate solder region of grid layer 10 through the first transparency conducting layer 12 from source-drain electrode, and from the second transparency conducting layer 15
Output, and then realize the electrical performance testing of product.
As shown in Figure 5 and Figure 6, when the grid that the gate pad in the present embodiment is the test circuit region away from array base palte
During the weld pad of pole, test signal inputs (such as saturating by the conductive salient point of flexible circuit board and second from the second transparency conducting layer 15
The upper surface conductive contact of bright conductive layer 15), test signal passes through the second transparency conducting layer 15 and the first transparency conducting layer 12
Transport to the welding region of grid layer 10, and export from welding region, thus realize the electrical performance testing of product.
Array base palte the most also includes multiple source-drain electrode weld pad, due to the exposure sources used in array base palte manufacturing process
Limited resolution, multiple source-drain electrode weld pads and gate pad interval arrange.
In order to improve reliability and the yields of product further, as shown in Figure 2 and Figure 7, state embodiment before this invention
On the basis of, additionally provide the second embodiment, in a second embodiment, each source-drain electrode weld pad includes: be positioned at gate insulator
The first transparency conducting layer 12 on layer 11, is positioned at the source-drain electrode layer 13 on the first transparency conducting layer 12, is positioned at source-drain electrode layer
Passivation layer 14 on 13, and it is positioned at the second transparency conducting layer 15 on passivation layer 14, wherein,
Source-drain electrode layer 13 includes that source-drain electrode welding region, passivation layer 14 offer at least one and do not expose the of source-drain electrode layer
Three vias 142, the second transparency conducting layer 15 is by each the 3rd via 142 and first transparency conducting layer 12 conductive contact.
Source-drain electrode weld pad can be the source-drain electrode weldering in integrated circuit (such as S/W the tests circuit) region near array base palte
Pad, it is also possible to the source-drain electrode for the integrated circuit region (the such as array base palte marginal position to box) away from array base palte welds
Pad.This enforcement is illustrated below with the source-drain electrode weld pad example that source-drain electrode weld pad is the integrated circuit region near array base palte
Example.
During as it is shown in fig. 7, the array base palte that the present embodiment provides is tested, test circuit output test signal is to source and drain
Pole welding region, it is achieved the electrical performance testing of product.Owing to, in the array base palte that the present embodiment provides, passivation layer 14 offers
At least one does not exposes the 3rd via 142 of source-drain electrode layer, and the second transparency conducting layer 15 is by each the 3rd via 142 and the
One transparency conducting layer 12 conductive contact, in the manufacturing process of array base palte, it is possible to is effectively prevented electrolyte cross the 3rd mistake
The second transparency conducting layer 15 and the first transparency conducting layer 12 at hole 142 occur that infiltration causes the corrosion of source-drain electrode layer, thus
The corrosion condition that effectively prevent source-drain electrode weld pad occurs, and then improves yields and the reliability of product, therefore, this enforcement
The array base palte that example provides can be effectively prevented each gate pad and the corrosion condition of source-drain electrode weld pad of array base palte
Occur, further increase yields and the reliability of product.
It should be noted that in the array base palte of embodiment of the present invention offer, the material of gate insulator 11 can be nitrogen
SiClx, is not specifically limited at this；The position that arranges being positioned at the source-drain electrode above gate solder region does not limits, and can partly be positioned at
In first via 111 of gate insulator 11, it is also possible to be entirely located in outside the first via 111 of gate insulator 11, at this not
It is specifically limited, it is possible to realize the electric property of gate pad；First transparency conducting layer 12 and the second transparency conducting layer 15
Material do not limit, can be, but not limited to tin indium oxide or Graphene, due to tin indium oxide have that light transmission is good, low resistance and resistance to
The advantage of corrosion, therefore the first transparency conducting layer 12 and the second transparency conducting layer 15 preferably employ tin indium oxide.
Based on the array base palte provided in above-described embodiment, the embodiment of the present invention additionally provides a kind of display device, including
The array base palte that above-described embodiment is provided.
In a display device, owing to the second transparency conducting layer in the gate pad of array base palte is by being positioned at gate insulator
The first transparency conducting layer above Ceng and gate solder region conductive contact, and not direct and gate solder region conductive contact,
The corrosion condition that can be effectively prevented each gate pad on array base palte occurs, so the yields of this display device and can
Higher by property.This display device can be: mobile phone, panel computer, television set, display, notebook computer, DPF, leads
Any product with display function or the parts such as boat instrument.
The embodiment of the present invention also provides for the manufacture method of a kind of array base palte, and as shown in Figure 8, Fig. 8 is the present invention one enforcement
The schematic flow sheet of the manufacture method of example array base palte, this manufacture method includes:
Step 801: form the figure of the grid layer including gate solder region on underlay substrate；
The figure forming the grid layer including gate solder region in step 801 can use a patterning processes system
Complete, the work such as patterning processes generally includes base-plate cleaning, film forming, photoresist coat, expose, develop, etch, photoresist lift off
Sequence, i.e. deposition gate metal thin film, employing physical vapour deposition (PVD) mode (such as magnetron sputtering method) film forming usual for metal level,
The figure of the grid layer including gate solder region is formed by wet etching.
Step 802: formed on the figure of grid layer include being positioned at above gate solder region at least one first
The figure of the gate insulator of via；
The most also include due to array base palte being positioned on gate insulator and with relative the having in position, gate solder region
Active layer, therefore, can use a patterning processes to be formed and include being positioned at least one above gate solder region in step 802
The figure of the gate insulator of the first via, specifically includes deposition gate insulator layer film, heavy on gate insulator layer film
Long-pending active layer thin film, non-metallic layer generally uses chemical vapor deposition manner film forming, forms figure by dry etching, etches shape
Become the figure of active layer, and etch to be formed and include being positioned at the gate insulator of at least one the first via above gate solder region
The figure of layer.
Step 803: formed on the figure of gate insulator and led with gate solder region by each the first via
The figure of the first transparency conducting layer of electrical contact；
Step 803 can also use a patterning processes to be formed, and specifically includes deposition the first electrically conducting transparent layer film, etching
Form the figure by each first via Yu the first transparency conducting layer of described gate solder region conductive contact, i.e. etch
The first transparency conducting layer of at least one the first via being positioned at gate insulator is retained during the first electrically conducting transparent layer film.
Step 804: formation includes the passivation layer of at least one the second via on the figure of the first transparency conducting layer
Figure；
Step 804 specifically includes step 8041 and step 8042, wherein,
Step 8041: formed on the figure of the first transparency conducting layer and include being positioned at the gate pad of described integrated circuit
Gate solder region above the figure of source-drain electrode layer of source-drain electrode；For example, it is possible to form source-drain electrode layer by patterning processes
Figure time, etch away the source-drain electrode layer above the gate solder region of the gate pad being located remotely from integrated circuit region, protect
Stay the source-drain electrode layer above the gate solder region of the gate pad in integrated circuit region, with specific reference to the position of source-drain electrode
Determine.
Step 8042: formed on the figure of source-drain electrode layer and include that at least one does not exposes the second via of source-drain electrode layer
The figure of passivation layer；Step 8042 can also use a patterning processes formation to include that at least one does not exposes source-drain electrode layer
The figure of the passivation layer of the second via.
Step 805: formed on the figure of passivation layer and conducted electricity by each the second via and the first transparency conducting layer
The figure of the second transparency conducting layer of contact.
Step 805 can also be used a patterning processes to be formed and be led by each second via and the first transparency conducting layer
The figure of the second transparency conducting layer of electrical contact.
So far, including the gate pad near integrated circuit region and the array of the gate pad away from integrated circuit region
Substrate manufacture completes.
It should be noted that patterning processes generally includes base-plate cleaning, film forming, photoresist coat, expose, develop,
The operations such as etching, photoresist lift off；Employing physical vapour deposition (PVD) mode (such as magnetron sputtering method) film forming usual for metal level,
By wet etching formation figure, and employing chemical vapor deposition manner film forming usual for non-metallic layer, pass through dry etching
Forming figure, following steps reason is identical, repeats no more.In the present invention, patterning processes, photoetching process can be only included, or, bag
Include photoetching process and etch step, can also include simultaneously printing, ink-jet etc. other for the technique forming predetermined pattern；Light
Carving technology, refer to film forming, expose, utilize photoresist, mask plate, the exposure machine etc. of the technical process such as development form figure
Technique.Can be according to the corresponding patterning processes of structure choice formed in the present invention.
When array base palte also includes multiple source-drain electrode weld pad, below by the system of a preferably embodiment array substrate
Illustrating as method, the present invention is not limited to the manufacture method that the following embodiment embodiment of the present invention provides, including:
Step S11: form the figure of the grid layer including gate solder region on underlay substrate；
Step S12: formed on the figure of grid layer include being positioned at above gate solder region at least one first
The figure of the gate insulator of via；
Step S13: formed on the figure of gate insulator and led with gate solder region by each the first via
The figure of the first transparency conducting layer of electrical contact；
When i.e. being formed the figure of the first transparency conducting layer by patterning processes, retain at least one being positioned at gate insulator
The first transparency conducting layer in first via.
Step S14: formed on the figure of the first transparency conducting layer and include source-drain electrode welding region and be positioned at integrated electricity
The figure of the source-drain electrode floor of the source-drain electrode above the gate solder region of the gate pad in region, road；
When i.e. being formed the figure of the first transparency conducting layer by patterning processes, etch away and be located remotely from integrated circuit region
Source-drain electrode layer above the gate solder region of gate pad, retains source-drain electrode welding region and the grid near integrated circuit region
Source-drain electrode layer above the gate solder region of pole weld pad.
Step S15: formed on the figure of source-drain electrode layer and include that at least one does not exposes the second via of source-drain electrode layer
The figure of passivation layer of the 3rd via of source-drain electrode layer welding region is not exposed with at least one；
Step S16: form the figure of the second transparency conducting layer on the figure of passivation layer, the second transparency conducting layer passes through
Each second via and the 3rd via and the first transparency conducting layer conductive contact.
The array base palte made by above-mentioned manufacture method, compared in prior art, the second transparency conducting layer and grid
Welding region, source-drain electrode welding region direct conduction contact, and easily cause the weld pad of array base palte to corrode, and the present invention makes
Method makes the array base palte obtained, and the second transparency conducting layer is by the first transparency conducting layer and gate solder region, source-drain electrode
Welding region conductive contact, not direct and gate solder region, source-drain electrode welding region conductive contact, it is possible to be effectively prevented battle array
On row substrate, the corrosion condition of each weld pad occurs, thus improves yields and the reliability of product；Further, above-mentioned made
Cheng Kezhi, the manufacture method that the present invention provides increase only a gate insulator masking process compared to prior art, therefore
Use the array base palte that the present invention provides, it is possible to the production cost making product is relatively low, is more widely applied.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (6)
1. an array base palte, including multiple gate pad, it is characterised in that each described gate pad includes: be positioned at lining
Grid layer on substrate, is positioned at the gate insulator on described grid layer, is positioned on described gate insulator
One transparency conducting layer, is positioned at the passivation layer on described first transparency conducting layer, and is positioned at second on described passivation layer
Transparency conducting layer, wherein,
Described grid layer includes gate solder region；Described gate insulator offers and is positioned at above described gate solder region
At least one first via；Described first transparency conducting layer is connect with described gate solder region conduction by each first via
Touch；Described passivation layer offers at least one second via, and described second transparency conducting layer passes through each second via and institute
State the first transparency conducting layer conductive contact；
Described array base palte also includes: multiple source-drain electrode weld pads, and each described source-drain electrode weld pad includes: be positioned at described grid exhausted
The first transparency conducting layer on edge layer, is positioned at the source-drain electrode layer on described first transparency conducting layer, is positioned at described source-drain electrode
Passivation layer on Ceng, and it is positioned at the second transparency conducting layer on described passivation layer, wherein,
Described source-drain electrode layer includes that source-drain electrode welding region, described passivation layer offer at least one and do not expose described source-drain electrode layer
The 3rd via, described second transparency conducting layer by each described 3rd via with described first transparency conducting layer conduct electricity connect
Touch.
2. array base palte as claimed in claim 1, it is characterised in that described gate pad is the gate pad of integrated circuit,
The gate pad of described integrated circuit also includes between described first transparency conducting layer and described passivation layer and includes being positioned at
The source-drain electrode layer of the source-drain electrode above described gate solder region, at least one second via described does not exposes described source-drain electrode
Layer.
3. array base palte as claimed in claim 1 or 2, it is characterised in that described first transparency conducting layer includes tin indium oxide
Layer, and/or, described second transparency conducting layer includes indium tin oxide layer.
4. a display device, it is characterised in that include the array base palte as described in claims 1 to 3 is arbitrary.
5. the manufacture method of an array base palte, it is characterised in that including:
Underlay substrate is formed the figure of the grid layer including gate solder region；
At least one first via including being positioned at above described gate solder region is formed on the figure of described grid layer
The figure of gate insulator；
Formed on the figure of described gate insulator and connect with described gate solder region conduction by each first via
The figure of the first transparency conducting layer touched；
The figure of the passivation layer including at least one the second via is formed on the figure of described first transparency conducting layer；
Formed on the figure of described passivation layer by each second via and described first transparency conducting layer conductive contact
The figure of the second transparency conducting layer；
Include being positioned at the figure of the source-drain electrode layer of the source-drain electrode above the gate solder region of the gate pad of integrated circuit being formed
While shape, also form the figure of source-drain electrode welding region；
While formation includes that at least one does not exposes the figure of the passivation layer of the second via of described source-drain electrode layer, also formed
At least one does not exposes the 3rd via of described source-drain electrode layer, and described second transparency conducting layer passes through each described 3rd via
With described first transparency conducting layer conductive contact.
6. the manufacture method of array base palte as claimed in claim 5, it is characterised in that at the figure of described first transparency conducting layer
Form the figure of the passivation layer including at least one the second via on shape, specifically include:
Formed on the figure of described first transparency conducting layer and include being positioned at the gate pad of the gate pad of integrated circuit
The figure of the source-drain electrode layer of the source-drain electrode above territory；
The figure of passivation layer including at least one the second via is formed on the figure of described source-drain electrode layer, described at least one
Individual second via does not exposes described source-drain electrode layer.
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| CN104867924B (en) * | 2015-05-06 | 2018-10-23 | 深圳市华星光电技术有限公司 | TFT display part and preparation method thereof |
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