CN105977267A - Array substrate and manufacture method thereof and display device - Google Patents
Array substrate and manufacture method thereof and display device Download PDFInfo
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- CN105977267A CN105977267A CN201610585610.1A CN201610585610A CN105977267A CN 105977267 A CN105977267 A CN 105977267A CN 201610585610 A CN201610585610 A CN 201610585610A CN 105977267 A CN105977267 A CN 105977267A
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- conductive pattern
- dottle pin
- underlay substrate
- base palte
- array base
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- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000002161 passivation Methods 0.000 claims description 28
- 239000010409 thin film Substances 0.000 claims description 23
- 238000009413 insulation Methods 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 15
- 238000002955 isolation Methods 0.000 abstract 3
- 230000007547 defect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 18
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides an array substrate and a manufacture method thereof and a display device, and belongs to the technical field of display. The manufacture method comprises the following steps: forming an isolation pad pattern at a preset position on a substrate base plate; forming a first conductive pattern on the isolation pad pattern; forming an insulating layer comprising a via hole on the substrate base plate, where the first conductive pattern is formed; and forming a second conductive pattern on the insulating layer, wherein the first conductive pattern is connected with the second conductive pattern through the via hole running through the insulating layer; orthographic projection of the via hole on the substrate base plate and orthographic projection of the isolation pad pattern on the substrate base plate are at least partially overlapped. The technical scheme can prevent the defect of Mura, and improves display effect of the display device.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and preparation method thereof, display dress
Put.
Background technology
In prior art, pixel electrode and the drain electrode of thin film transistor (TFT) on array base palte are positioned at different layers,
The drain electrode of pixel electrode and thin film transistor (TFT) is coated with passivation layer, passivation layer is formed and is conductively connected
Line, conductive connecting connects pixel electrode and the drain electrode of thin film transistor (TFT) by running through the via of passivation layer,
Owing to the thickness of passivation layer is bigger, therefore the degree of depth of via is the biggest, owing to easily occurring at deep hole
Depression, when causing coating alignment film on array base palte, easily easily there is diffusion inequality in alignment film at deep hole,
Cause the problem that display Mura (uneven) occurs in final display product.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of array base palte and preparation method thereof, display device,
It can be avoided that occur that Mura is bad, improve the display effect of display device.
For solving above-mentioned technical problem, embodiments of the invention provide technical scheme as follows:
On the one hand, it is provided that the manufacture method of a kind of array base palte, described manufacture method includes:
Predeterminated position on underlay substrate forms dottle pin figure；
Described dottle pin figure forms the first conductive pattern；
The underlay substrate being formed with described first conductive pattern is formed the insulating barrier including via；
Described insulating barrier is formed the second conductive pattern, described first conductive pattern and described second conductive pattern
Shape connects by running through the via of described insulating barrier, the orthographic projection on described underlay substrate of the described via and institute
State the orthographic projection on described underlay substrate of the dottle pin figure at least partly to overlap.
Further, the orthographic projection on described underlay substrate of the described dottle pin figure exists with the bottom of described via
Orthographic projection on described underlay substrate is completely superposed.
Further, form described dottle pin figure to include:
Grid line, the gate electrode of thin film transistor (TFT) and described dottle pin figure is formed by a patterning processes.
Further, the height of described dottle pin figure is
The embodiment of the present invention additionally provides a kind of array base palte, and described array base palte includes being positioned on underlay substrate
The first conductive pattern, the insulating barrier being positioned on described first conductive pattern, be positioned on described insulating barrier
Two conductive patterns, described first conductive pattern and described second conductive pattern are by running through the mistake of described insulating barrier
Hole connects, it is characterised in that described array base palte also includes:
Being positioned at the dottle pin figure under described first conductive pattern, described dottle pin figure is on described underlay substrate
Orthographic projection at least partly overlaps with the orthographic projection on described underlay substrate of the described via.
Further, the orthographic projection on described underlay substrate of the described dottle pin figure and described via bottom are in institute
The orthographic projection stated on underlay substrate is completely superposed.
Further, the grid line of described dottle pin figure and array base palte and the same layer of gate electrode of thin film transistor (TFT)
Arrange with material.
Further, described first conductive pattern is pixel electrode, and described second conductive pattern is for connecting pixel
The conductive connecting of the drain electrode of electrode and thin film transistor (TFT), described insulating barrier includes passivation layer and gate insulation layer.
Further, described array base palte specifically includes:
Underlay substrate；
It is positioned at the grid line on described underlay substrate, the gate electrode of thin film transistor (TFT) and described dottle pin figure；
It is positioned at the pixel electrode on described dottle pin figure；
Gate insulation layer；
It is positioned at the active layer on described gate insulation layer；
It is positioned at the ohmic contact layer on described active layer；
The source electrode of the thin film transistor (TFT) being positioned on described ohmic contact layer and drain electrode；
Passivation layer, described passivation layer includes the first via and the correspondence described pixel electricity of corresponding described drain electrode
Second via of pole, described second via also extends through described gate insulation layer；
Being positioned at the public electrode on described passivation layer and conductive connecting, described conductive connecting passes through institute respectively
State the first via and described second via connects described drain electrode and described pixel electrode.
The embodiment of the present invention additionally provides a kind of display device, including array base palte as above.
Embodiments of the invention have the advantages that
In such scheme, before forming the first conductive pattern, bottom the first conductive pattern, form dottle pin figure
Shape, this dottle pin figure can the height of padded first conductive pattern, thus reduce via at the first conductive pattern
The degree of depth, so after on array base palte coat alignment film time, it is possible to increase alignment film expansion at via
Dissipate effect, thus it is bad to avoid the occurrence of Mura, improves the display effect of display device.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing array base palte；
Fig. 2 is the structural representation of embodiment of the present invention array base palte.
Reference
1 underlay substrate 2 gate electrode 3 pixel electrode 4 gate insulation layer 5 active layer
6 ohmic contact layer 7 drain electrode 8 passivation layer 9 conductive connectings
10 dottle pin figure 11 source electrodes
Detailed description of the invention
For making embodiments of the invention solve the technical problem that, technical scheme and advantage clearer, below
To be described in detail in conjunction with the drawings and the specific embodiments.
Embodiments of the invention, for easily occurring depression in prior art at deep hole, cause at array base palte
During upper coating alignment film, easily easily there is diffusion inequality in alignment film at deep hole, causes final display product
The problem that display Mura occurs, it is provided that a kind of array base palte and preparation method thereof, display device, it is possible to keep away
Exempt from occur that Mura is bad, improve the display effect of display device.
Embodiment one
The present embodiment provides the manufacture method of a kind of array base palte, and described manufacture method includes:
Predeterminated position on underlay substrate forms dottle pin figure；
Described dottle pin figure forms the first conductive pattern；
The underlay substrate being formed with described first conductive pattern is formed the insulating barrier including via；
Described insulating barrier is formed the second conductive pattern, described first conductive pattern and described second conductive pattern
Shape connects by running through the via of described insulating barrier, the orthographic projection on described underlay substrate of the described via and institute
State the orthographic projection on described underlay substrate of the dottle pin figure at least partly to overlap.
In the present embodiment, before forming the first conductive pattern, bottom the first conductive pattern, form dottle pin figure
Shape, this dottle pin figure can the height of padded first conductive pattern, thus reduce via at the first conductive pattern
The degree of depth, so after on array base palte coat alignment film time, it is possible to increase alignment film expansion at via
Dissipate effect, thus it is bad to avoid the occurrence of Mura, improves the display effect of display device.
Further, the orthographic projection on described underlay substrate of the described dottle pin figure exists with the bottom of described via
Orthographic projection on described underlay substrate is completely superposed, and such dottle pin figure first can either conduct electricity at padded via
The height of figure, does not interferes with again the height of other position the first conductive patterns.
Further, form described dottle pin figure to include:
Grid line, the gate electrode of thin film transistor (TFT) and described dottle pin figure is formed, so by a patterning processes
Dottle pin figure can be formed on the premise of not increasing patterning processes, not improve the production cost of array base palte.
Generally, the degree of depth of via isLeft and right, by the height of dottle pin figure in the present embodiment
It is set toThe degree of depth that so can make via reduces nearly half, so afterwards at array base palte
During upper coating alignment film, it is possible to significantly improve alignment film diffusion effect at via, thus avoid the occurrence of
Mura is bad, improves the display effect of display device.If arranged by the height of dottle pin figure is less,
Then improve the bad DeGrain of Mura, if arranged by the height of dottle pin figure is excessive, be then poised for battle
The structure influence of row substrate is bigger, it will have influence on the yield of array base palte.
Embodiment two
Present embodiments providing a kind of array base palte, described array base palte includes first be positioned on underlay substrate
Conductive pattern, the insulating barrier being positioned on described first conductive pattern, be positioned on described insulating barrier second conduction
Figure, described first conductive pattern and described second conductive pattern are by running through the via of described insulating barrier even
Connect, it is characterised in that described array base palte also includes:
Being positioned at the dottle pin figure under described first conductive pattern, described dottle pin figure is on described underlay substrate
Orthographic projection at least partly overlaps with the orthographic projection on described underlay substrate of the described via.
In the present embodiment, being provided with dottle pin figure bottom the first conductive pattern, this dottle pin figure can be padded
The height of the first conductive pattern, thus reduce the degree of depth of via at the first conductive pattern, so afterwards at array
When coating alignment film on substrate, it is possible to increase alignment film diffusion effect at via, thus avoid the occurrence of
Mura is bad, improves the display effect of display device.
Preferably, the bottom of the orthographic projection on underlay substrate of the dottle pin figure and via on underlay substrate just
Projection is completely superposed, such dottle pin figure can either the height of the first conductive pattern at padded via, again will not
Affect the height of other position the first conductive patterns.
Preferably, the gate electrode of dottle pin figure and the grid line of array base palte and thin film transistor (TFT) is with the same material of layer
Arranging, such dottle pin figure can pass through a patterning processes simultaneously with the gate electrode of grid line and thin film transistor (TFT)
Formed, so can form dottle pin figure on the premise of not increasing patterning processes, not improve array base palte
Production cost.
In specific embodiment, the first conductive pattern is pixel electrode, and the second conductive pattern is for connecting pixel electrode
The conductive connecting of the drain electrode with thin film transistor (TFT), insulating barrier includes passivation layer and gate insulation layer.
Further, described array base palte specifically includes:
Underlay substrate；
It is positioned at the grid line on described underlay substrate, the gate electrode of thin film transistor (TFT) and described dottle pin figure；
It is positioned at the pixel electrode on described dottle pin figure；
Gate insulation layer；
It is positioned at the active layer on described gate insulation layer；
It is positioned at the ohmic contact layer on described active layer；
The source electrode of the thin film transistor (TFT) being positioned on described ohmic contact layer and drain electrode；
Passivation layer, described passivation layer includes the first via and the correspondence described pixel electricity of corresponding described drain electrode
Second via of pole, described second via also extends through described gate insulation layer；
Being positioned at the public electrode on described passivation layer and conductive connecting, described conductive connecting passes through institute respectively
State the first via and described second via connects described drain electrode and described pixel electrode.
Embodiment three
Present embodiments provide a kind of display device, including array base palte as above.Described display device
Can be: LCD TV, liquid crystal display, DPF, mobile phone, panel computer etc. are any has display
The product of function or parts, wherein, described display device also includes flexible PCB, printed circuit board (PCB) and the back of the body
Plate.
Embodiment four
As it is shown in figure 1, existing array base palte includes underlay substrate 1, be positioned at the grid line on underlay substrate 1,
The gate electrode 2 of thin film transistor (TFT) and pixel electrode 3, gate insulation layer 4, be positioned on gate insulation layer 4 is active
Layer 5, the ohmic contact layer 6 being positioned on active layer 5, the thin film transistor (TFT) being positioned on ohmic contact layer 6
Source electrode 11 and drain electrode 7, passivation layer 8, passivation layer 8 include corresponding drain electrode 7 the first via and
Second via of respective pixel electrode 3, the second via also extends through gate insulation layer 4, be positioned on passivation layer 8 with
The conductive connecting 9 that public electrode is arranged with material with layer, conductive connecting 9 is by the first via and second
Via connects drain electrode 7 and pixel electrode 3.Owing to the thickness of passivation layer 8 is bigger, cause the second via
Depth ratio relatively big, depression easily occurs at the second via, when causing coating alignment film on array base palte,
Easily easily there is diffusion inequality in alignment film at the second via, causes final display product display occur
The problem of Mura.
In order to solve the problems referred to above, present embodiments provide the manufacture method of a kind of array base palte, this making side
Method specifically includes following steps:
Step 1, providing a underlay substrate 1, underlay substrate 1 can be quartz base plate or glass substrate.
Underlay substrate 1 deposits grid metal level, is patterned grid metal level forming grid line, thin film transistor (TFT)
Gate electrode 2 and dottle pin figure 10；
Step 2, depositing the first transparency conducting layer on the underlay substrate 1 of step 1, first transparent leads
Electric layer can use ITO or IZO, and the first transparency conducting layer is patterned being formed the figure of pixel electrode 3,
A part for pixel electrode 3 is positioned on dottle pin figure 10, owing to dottle pin figure 10 exists certain height,
Therefore, the part that pixel electrode 3 is positioned on dottle pin figure 10 is the most padded, the thickness of dottle pin figure and grid
The thickness of line and gate electrode 2 is equal, typically existsLeft and right；
Step 3, on the underlay substrate 1 of step 2 deposit gate insulation layer 3, gate insulation layer 3 is permissible
Use silicon oxide or silicon nitride；
Step 4, on the underlay substrate 1 of step 3 deposit one layer of active layer material, to active layer material
Material is patterned being formed with the figure of active layer 5；
Step 5, on the underlay substrate 1 of step 4 deposit one layer of Ohmic contact layer material, to ohm
Contact layer material is patterned being formed the figure of ohmic contact layer 6；
Step 6, on the underlay substrate 1 of step 5 deposit one layer of source and drain metal level, to source and drain metal
Layer is patterned, and forms the source electrode 11 of thin film transistor (TFT), drain electrode 7 and data wire；
Step 7, in deposit passivation layer 8 on the underlay substrate 1 of step 6, passivation layer 8 can use
Silicon oxide or silicon nitride, perform etching passivation layer 8 and gate insulation layer 4, is formed and runs through passivation layer 8
The first via and run through the second via of passivation layer 8 and gate insulation layer 4, wherein, the first via corresponds to
Drain electrode 7 is arranged, and the second via is arranged corresponding to dottle pin figure 10, and the second via is on underlay substrate 1
Orthographic projection be completely superposed with the dottle pin figure 10 orthographic projection on underlay substrate 1；
Owing to the passivation layer 8 at the second via and gate insulation layer 4 are all etched away, therefore, at the second via
Pixel electrode 3 will expose, and owing to dottle pin figure 10 exists certain height, therefore the second mistake
The degree of depth in hole also can reduce, if the thickness sum of passivation layer and gate insulation layer isLeft and right, then
If being not provided with dottle pin figure on underlay substrate, the degree of depth of the second via also will beLeft and right, and
After being provided with dottle pin figure on underlay substrate, the degree of depth of the second via will reduce the thickness of a dottle pin figure
Degree, if the thickness of dottle pin figure existsLeft and right, then the degree of depth of the second via will drop toLeft
The right side, the degree of depth of the second via will reduce half, when coating alignment film on array base palte so afterwards, it is possible to
Improve alignment film diffusion effect at via, thus it is bad to avoid the occurrence of Mura, improves display device
Display effect.
Step 8, depositing the second transparency conducting layer on the underlay substrate 1 of step 7, second transparent leads
Electric layer can use ITO or IZO, is patterned the second transparency conducting layer forming conductive connecting 9
With the figure of public electrode, conductive connecting 9 connects drain electrode 7 and picture by the first via and the second via
Element electrode 3；
The array base palte of the present embodiment as shown in Figure 2, the present embodiment can be formed through above-mentioned steps 1-8
Array base palte bottom pixel electrode, be provided with dottle pin figure, this dottle pin figure can padded pixel electrode
Highly, thus reduce the degree of depth of via at pixel electrode, when coating alignment film on array base palte so afterwards,
Alignment film diffusion effect at via can be improved, thus it is bad to avoid the occurrence of Mura, improve display dress
The display effect put.It addition, the array base palte of the present embodiment is when making, it is not necessary to increase new patterning processes,
Have only to, when forming the figure of gate electrode and grid line, existing grid metal layer mask plate slightly be repaiied
Change, dottle pin figure can be formed while forming gate electrode and grid line, be increased without the production of array base palte
Cost.
The above is the preferred embodiment of the present invention, it is noted that for the common skill of the art
For art personnel, on the premise of without departing from principle of the present invention, it is also possible to make some improvements and modifications,
These improvements and modifications also should be regarded as protection scope of the present invention.
Claims (10)
1. the manufacture method of an array base palte, it is characterised in that described manufacture method includes:
Predeterminated position on underlay substrate forms dottle pin figure；
Described dottle pin figure forms the first conductive pattern；
The underlay substrate being formed with described first conductive pattern is formed the insulating barrier including via；
Described insulating barrier is formed the second conductive pattern, described first conductive pattern and described second conductive pattern
Shape connects by running through the via of described insulating barrier, the orthographic projection on described underlay substrate of the described via and institute
State the orthographic projection on described underlay substrate of the dottle pin figure at least partly to overlap.
The manufacture method of array base palte the most according to claim 1, it is characterised in that described dottle pin
The just throwing on described underlay substrate of the bottom of figure orthographic projection on described underlay substrate and described via
Shadow is completely superposed.
The manufacture method of array base palte the most according to claim 1, it is characterised in that formed described
Dottle pin figure includes:
Grid line, the gate electrode of thin film transistor (TFT) and described dottle pin figure is formed by a patterning processes.
The manufacture method of array base palte the most according to claim 1, it is characterised in that described dottle pin
The height of figure is
5. an array base palte, the first conductive pattern that described array base palte includes being positioned on underlay substrate,
The second conductive pattern be positioned at the insulating barrier on described first conductive pattern, being positioned on described insulating barrier, described
First conductive pattern is connected by running through the via of described insulating barrier with described second conductive pattern, and its feature exists
In, described array base palte also includes:
Being positioned at the dottle pin figure under described first conductive pattern, described dottle pin figure is on described underlay substrate
Orthographic projection at least partly overlaps with the orthographic projection on described underlay substrate of the described via.
Array base palte the most according to claim 5, it is characterised in that described dottle pin figure is described
Orthographic projection on underlay substrate is completely superposed with the orthographic projection on described underlay substrate of the described via bottom.
Array base palte the most according to claim 5, it is characterised in that described dottle pin figure and array
The grid line of substrate and the gate electrode of thin film transistor (TFT) are arranged with material with layer.
Array base palte the most according to claim 5, it is characterised in that described first conductive pattern is
Pixel electrode, described second conductive pattern is being conductively connected of the connection pixel electrode drain electrode with thin film transistor (TFT)
Line, described insulating barrier includes passivation layer and gate insulation layer.
Array base palte the most according to claim 8, it is characterised in that described array base palte specifically wraps
Include:
Underlay substrate；
It is positioned at the grid line on described underlay substrate, the gate electrode of thin film transistor (TFT) and described dottle pin figure；
It is positioned at the pixel electrode on described dottle pin figure；
Gate insulation layer；
It is positioned at the active layer on described gate insulation layer；
It is positioned at the ohmic contact layer on described active layer；
The source electrode of the thin film transistor (TFT) being positioned on described ohmic contact layer and drain electrode；
Passivation layer, described passivation layer includes the first via and the correspondence described pixel electricity of corresponding described drain electrode
Second via of pole, described second via also extends through described gate insulation layer；
Being positioned at the public electrode on described passivation layer and conductive connecting, described conductive connecting passes through institute respectively
State the first via and described second via connects described drain electrode and described pixel electrode.
10. a display device, it is characterised in that include the battle array as according to any one of claim 5-9
Row substrate.
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| CN201610585610.1A CN105977267B (en) | 2016-07-22 | 2016-07-22 | Array substrate and preparation method thereof, display device |
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Cited By (4)
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| CN107093584A (en) * | 2017-05-05 | 2017-08-25 | 上海中航光电子有限公司 | Array base palte, display panel, the preparation method of display device and array base palte |
| CN108108059A (en) * | 2018-01-10 | 2018-06-01 | 京东方科技集团股份有限公司 | A kind of display panel and preparation method thereof and display device |
| US20180219024A1 (en) * | 2016-06-29 | 2018-08-02 | Boe Technology Group Co., Ltd. | Array substrate, manufacturing method thereof and display device |
| WO2022133903A1 (en) * | 2020-12-24 | 2022-06-30 | 京东方科技集团股份有限公司 | Display panel, manufacturing method therefor, and display apparatus |
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| US20140125909A1 (en) * | 2011-10-17 | 2014-05-08 | Boe Technology Group Co., Ltd. | Pixel unit, array substrate, liquid crystal panel and method for manufacturing the array substrate |
| CN103715138A (en) * | 2013-12-31 | 2014-04-09 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method and display device thereof |
| CN104934443A (en) * | 2015-05-04 | 2015-09-23 | 京东方科技集团股份有限公司 | Array substrate, manufacture method thereof, and display device |
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| US20180219024A1 (en) * | 2016-06-29 | 2018-08-02 | Boe Technology Group Co., Ltd. | Array substrate, manufacturing method thereof and display device |
| US10109653B2 (en) * | 2016-06-29 | 2018-10-23 | Boe Technology Group Co., Ltd. | Array substrate, manufacturing method thereof and display device |
| CN107093584A (en) * | 2017-05-05 | 2017-08-25 | 上海中航光电子有限公司 | Array base palte, display panel, the preparation method of display device and array base palte |
| CN108108059A (en) * | 2018-01-10 | 2018-06-01 | 京东方科技集团股份有限公司 | A kind of display panel and preparation method thereof and display device |
| CN108108059B (en) * | 2018-01-10 | 2021-01-29 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
| WO2022133903A1 (en) * | 2020-12-24 | 2022-06-30 | 京东方科技集团股份有限公司 | Display panel, manufacturing method therefor, and display apparatus |
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