CN103972242A - Array substrate, display device and manufacturing method of array substrate - Google Patents

Array substrate, display device and manufacturing method of array substrate Download PDF

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Publication number
CN103972242A
CN103972242A CN201410163006.0A CN201410163006A CN103972242A CN 103972242 A CN103972242 A CN 103972242A CN 201410163006 A CN201410163006 A CN 201410163006A CN 103972242 A CN103972242 A CN 103972242A
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layer
gate
transparent conductive
source
drain
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CN201410163006.0A
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CN103972242B (en
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李卿硕
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Abstract

The invention relates to the technical field of displaying, and discloses an array substrate, a display device and a manufacturing method of the array substrate to enhance the yield and reliability of products. The array substrate comprises a plurality of grid electrode welding pads. Each grid electrode welding pad comprises a grid electrode layer, a grid electrode insulating layer, a first transparent conducting layer, a passivating layer and a second transparent conducting layer, wherein the grid electrode layers are located on a substrate; the grid electrode insulating layers are located on the grid electrode layers; the first transparent conducting layers are located on the grid electrode insulating layers; the passivating layers are located on the first transparent conducting layers; the second transparent conducting layers are located on the passivating layers; the grid electrode layers comprise grid electrode welding areas; each grid electrode insulating layer is provided with at least one first via hole located above the corresponding grid electrode welding area; the first transparent conducting layers make conductive contact with the grid electrode welding areas through all the first via holes; each passivating layer is provided with at least one second via hole, and the second transparent conducting layers make conductive contact with the first transparent conducting layers through all the second via holes.

Description

一种阵列基板、显示装置及阵列基板的制作方法 An array substrate, a display device and a manufacturing method of an array substrate

技术领域 FIELD

[0001] 本发明涉及显示技术领域,特别是涉及一种阵列基板、显示装置及阵列基板的制作方法。 [0001] The present invention relates to display technology, and particularly relates to an array substrate, and a method for manufacturing an array substrate of a display device.

背景技术 Background technique

[0002]目前,阵列基板作为液晶显示装置的重要元器件,在模组组装、环境模拟试验等过程中,需要通过其栅极焊垫和源漏极焊垫对阵列基板进行扫描信号和数据信号的测试,以保障其电学特性的可靠性。 [0002] Currently, as an important component of the array substrate of the liquid crystal display device, the module assembly, and so the process environment simulation test, the pad array substrate requires a scanning signal and a data signal through the gate and the source and drain bonding pads the test, to ensure the reliability of its electrical properties.

[0003] 如图1所示,现有的阵列基板的栅极焊垫通常依次包括:位于衬底基板上的栅极层10、栅极绝缘层11、源漏极层13、钝化层14以及第二透明导电层15,其中,栅极层10包括焊接区域,源漏极层13包括位于焊接区域上方的源漏极,栅极绝缘层11包括使第二透明导电层15与焊接区域导电接触的焊垫过孔111',钝化层14包括使第二透明导电层15与源漏极导电接触的钝化层过孔141'。 [0003] As shown in FIG. 1, the conventional gate pad array substrate typically includes, in order: a gate layer on the base substrate 10, a gate insulating layer 11, source and drain layer 13, passivation layer 14 and a second transparent conductive layer 15, wherein the gate layer 10 includes a welded area, the source-drain layer 13 includes source and drain regions located above the weld, the gate insulating layer 11 comprises a second transparent conductive layer 15 and the conductive welding area bonding pads through the contact hole 111 ', the passivation layer 14 comprising a transparent conductive layer of the second passivation layer 15 in contact with the source-drain conductive vias 141'. 由图中可以看出,在液晶显示装置的制作和运输过程中,电解液极易通过焊垫过孔111'处的第二透明导电层渗透至栅极层的焊接区域并腐蚀栅极层,进而影响阵列基板的栅极焊垫的电学性能,导致产品的可靠性降低甚至失效,尤其当第二透明导电层为氧化铟锡层时,由于氧化铟锡层自身的孔隙较大,致密性较差,上述缺陷更加严重。 As can be seen from the figure, the liquid crystal display production and transport apparatus, the electrolytic solution can easily pass through the pad hole 111 'at a second transparent conductive layer permeable to the welding region of the gate layer and etching the gate layer, thereby affecting the electrical properties of the gate pad array substrate, resulting in reduced reliability of the product or even failure, especially when the second layer is a transparent conductive layer of indium tin oxide, indium tin oxide layer due to the pores itself larger than the denseness the difference between the defect is more serious.

发明内容 SUMMARY

[0004] 本发明提供了一种阵列基板、显示装置及阵列基板的制作方法,用以提高产品的良品率和可靠性。 [0004] The present invention provides an array substrate, and a method for manufacturing an array substrate of a display device, to improve the yield and reliability of products.

[0005] 本发明提供的阵列基板,包括多个栅极焊垫,每一个所述栅极焊垫包括:位于衬底基板之上的栅极层,位于所述栅极层之上的栅极绝缘层,位于所述栅极绝缘层之上的第一透明导电层,位于所述第一透明导电层之上的钝化层,以及位于所述钝化层之上的第二透明导电层,其中, [0005] The present invention provides an array substrate, comprising a plurality of gate pads, each pad of said gate comprising: a gate layer over the base substrate, a gate electrode located over the gate layer, insulating layer, the first transparent conductive layer positioned over the gate insulating layer, located over the first transparent conductive layer is a passivation layer, and a passivation layer located over the second transparent conductive layer, among them,

[0006] 所述栅极层包括栅极焊接区域;所述栅极绝缘层开设有位于所述栅极焊接区域上方的至少一个第一过孔;所述第一透明导电层通过每一个第一过孔与所述栅极焊接区域导电接触;所述钝化层开设有至少一个第二过孔,所述第二透明导电层通过每一个第二过孔与所述第一透明导电层导电接触。 [0006] The gate layer comprises a gate pad region; the gate insulating layer above the gate defines a weld region located at least one first via hole; the first transparent conductive layer is formed by each of the first via conductive contact with the gate pad region; the passivation layer defines at least one second through hole, the second transparent conductive layer is formed by each of the second through hole in contact with the first transparent conductive layer of conductive .

[0007] 在本发明技术方案中,由于阵列基板的第二透明导电层通过位于栅极绝缘层上方的第一透明导电层与栅极焊接区域导电接触,而未直接与栅极焊接区域导电接触,因此,即使电解液穿过第二过孔处的第二透明导电层和第一透明导电层出现渗透,第一透明导电层下方的栅极绝缘层能够有效地防止电解液进一步渗透至栅极层而引起栅极层的腐蚀,从而有效地防止了栅极焊垫的腐蚀情况发生,进而提高产品的良品率和可靠性。 [0007] In the aspect of the present invention, since the second transparent conductive layer of the array substrate through the conductive layer in contact with the conductive gate above the first transparent insulating layer and the gate bonding pad region, without direct contact with the conductive gate pad region Therefore, even when the electrolytic solution passes through the second transparent conductive layer and a first transparent conductive layer through the second penetration holes occurs, a first transparent conductive layer below the gate insulating layer can be effectively prevented further penetration of the electrolyte to the gate etching the gate layer to cause layer, thereby effectively preventing the corrosion of the gate pad occurs, thereby improving yield and reliability of products.

[0008] 进一步的,所述栅极焊垫为集成电路的栅极焊垫,所述集成电路的栅极焊垫还包括位于所述第一透明导电层与所述钝化层之间且包括位于所述栅极焊接区域上方的源漏极的源漏极层,所述至少一个第二过孔未露出所述源漏极层。 [0008] Further, the gate pad of the integrated circuit gate pads, the integrated circuit further comprises a gate pad positioned between said first transparent conductive layer and the passivation layer and comprising the drain layer is located above the gate of the weld region of the source and drain, said at least one second via hole exposing the source and drain layer is not.

[0009] 优选的,该阵列基板还包括多个源漏极焊垫,每一个所述源漏极焊垫包括:位于所述栅极绝缘层之上的第一透明导电层,位于所述第一透明导电层之上的源漏极层,位于所述源漏极层之上的钝化层,以及位于所述钝化层之上的第二透明导电层,其中, [0009] Preferably, the array substrate further includes a plurality of source and drain pads, each of said source and drain pad comprising: a first transparent conductive layer over the gate insulating layer between the first a source and drain layer over the transparent conductive layer, a passivation layer over the source and drain layer, and a passivation layer located over the second transparent conductive layer, wherein,

[0010] 所述源漏极层包括源漏极焊接区域,所述钝化层开设有至少一个未露出所述源漏极层的第三过孔,所述第二透明导电层通过每一个所述第三过孔与所述第一透明导电层导电接触。 [0010] The source-drain layer including a source region of the drain pad, the passivation layer defines at least one through-hole is not exposed to the source and drain of the third layer, the second transparent conductive layer through each of the said third through hole conductive contact with the first transparent conductive layer.

[0011] 优选的,所述第一透明导电层包括氧化铟锡层,和/或,所述第二透明导电层包括氧化铟锡层。 [0011] Preferably, the first transparent conductive layer comprises a layer of indium tin oxide, and / or the second transparent conductive layer include indium tin oxide layer.

[0012] 本发明还提供了一种显示装置,包括:前述任一技术方案所述的阵列基板。 [0012] The present invention further provides a display apparatus, comprising: an array substrate according to any of the preceding aspect. 由于本显示装置中阵列基板的栅极焊垫中的第二透明导电层通过位于栅极绝缘层上方的第一透明导电层与栅极焊接区域导电接触,而未直接与栅极焊接区域导电接触,能够有效地防止阵列基板上各个栅极焊垫的腐蚀情况发生,所以该显示装置的良品率和可靠性较高。 Since the second transparent conductive layer of the gate bonding pad of the present display device of the array substrate through a gate insulating layer positioned above the electrically conductive contact with the first conductive layer and the transparent gate weld region, without direct contact with the conductive gate pad region , corrosion can be effectively prevented on each of the gate pad array substrate occurs, so that a higher yield and reliability of the display device.

[0013] 本发明还提供一种显示面板的制作方法,包括: [0013] The present invention also provides a method of manufacturing a display panel, comprising:

[0014] 在衬底基板上形成包括栅极焊接区域的栅极层的图形; [0014] forming a gate pattern including the gate electrode layer in the weld region on the base substrate;

[0015] 在所述栅极层的图形之上形成包括位于所述栅极焊接区域上方的至少一个第一过孔的栅极绝缘层的图形; [0015] forming a gate insulating layer pattern includes a region above the gate pad via the at least one first pattern on top of the gate layer;

[0016] 在所述栅极绝缘层的图形之上形成通过每一个第一过孔与所述栅极焊接区域导电接触的第一透明导电层的图形; [0016] The first transparent conductive layer pattern is formed through each first through hole conductive contact with the gate weld region over the gate insulating layer pattern;

[0017] 在所述第一透明导电层的图形之上形成包括至少一个第二过孔的钝化层的图形; [0017] forming a passivation layer pattern comprises at least one second via hole pattern on the first transparent conductive layer;

[0018] 在所述钝化层的图形之上形成通过每一个第二过孔与所述第一透明导电层导电接触的第二透明导电层的图形。 [0018] The second transparent conductive layer pattern formed by each of the second through hole in contact with the first transparent conductive layer on the conductive pattern of the passivation layer.

附图说明 BRIEF DESCRIPTION

[0019] 图1为现有技术阵列基板的剖面结构示意图; [0019] FIG. 1 is a schematic cross-sectional structure of the prior art array substrate;

[0020] 图2为本发明阵列基板一实施例靠近集成电路区域的俯视结构示意图; [0020] FIG. 2 is a schematic top view of an integrated circuit structure close to the region of an array substrate according to an embodiment of the invention;

[0021] 图3为图2示出的阵列基板中A处一实施例的剖面结构放大示意图; [0021] FIG. 3 is a diagram illustrating an array substrate of FIG. 2 A cross-sectional structure at an enlarged schematic view of the embodiment;

[0022] 图4为图2示出的阵列基板中A处另一实施例的剖面结构放大示意图; [0022] FIG. 4 is a diagram illustrating an array substrate 2 in the embodiment A cross-sectional structure at another enlarged view;

[0023] 图5为本发明阵列基板一实施例远离集成电路区域的俯视结构示意图; [0023] Fig 5 a schematic view of an embodiment of an array substrate structure of integrated circuit region remote from the top view of the present invention;

[0024] 图6为图5示出的阵列基板的剖面结构放大示意图; [0024] FIG. 6 is a cross-sectional structure of the array substrate shown in FIG. 5 is an enlarged schematic view;

[0025] 图7为图2示出的阵列基板中B处一实施例的剖面结构放大示意图; [0025] FIG. 7 is a diagram illustrating an array substrate B in FIG. 2 a cross-sectional enlarged view of the structure of an example of embodiment;

[0026] 图8为本发明一实施例阵列基板的制作方法的流程示意图。 [0026] Figure 8 a schematic flow chart of the manufacturing method of an array substrate of the embodiment of the present invention.

[0027] 附图标记: [0027] reference numerals:

[0028] 10-栅极层 11-栅极绝缘层111-第一过孔 [0028] 10- 11- gate layer through the gate insulating layer of the first hole 111-

[0029] 12-第一透明导电层13-源漏极层 14-钝化层 [0029] The first transparent conductive layer 12- 13- 14- passivation layer source and drain layers

[0030] 141-第二过孔 142-第三过孔 [0030] 141- 142- third via hole through the second hole

[0031] 15-第二透明导电层16-集成电路 [0031] The second transparent conductive layer 15 16- IC

[0032] 111'-焊垫过孔141'-钝化层过孔具体实施方式 [0032] 111'- bonding pad through the hole of the passivation layer via hole 141'- DETAILED DESCRIPTION

[0033] 为了提高产品的良品率和可靠性,本发明实施例提供了一种阵列基板、显示装置及阵列基板的制作方法。 [0033] In order to improve the yield and reliability of products, embodiments of the present invention provides an array substrate, and a method for manufacturing an array substrate of a display device. 在该阵列基板中,栅极焊垫由下至上依次包括:位于衬底基板之上的包括栅极焊接区域的栅极层、栅极绝缘层、第一透明导电层、钝化层,以及、第二透明导电层,栅极绝缘层开设有位于栅极焊接区域上方且使第一透明导电层与栅极焊接区域导电接触的至少一个第一过孔;钝化层开设有至少一个使第二透明导电层与第一透明导电层导电接触的第二过孔。 In the array substrate, a gate pad at the bottom to top comprising: a base substrate including over the gate layer, a gate insulating layer of the gate bonding pad area, a first transparent conductive layer, a passivation layer, and, the second transparent conductive layer, a gate insulating layer defines a weld region located above the gate and the electrically conductive contact with the first transparent conductive layer and the gate at least a first weld region through hole; passivation layer defines at least a second the transparent conductive layer is in contact with the first transparent conductive layer a second conductive vias. 第二透明导电层通过位于栅极绝缘层上方的第一透明导电层与栅极焊接区域导电接触,而未直接与栅极焊接区域导电接触,能够有效地防止阵列基板上各个栅极焊塾的腐蚀情况发生,从而提闻广品的良品率和可罪性。 The second transparent conductive layer located above the gate insulating layer, the first transparent conductive layer in contact with the gate conductive weld region, without direct contact with the conductive gate pad region, each of the gate can be effectively prevented bonding the array substrate Sook corrosion occurs, thereby improving yield smell broad product and may sin.

[0034] 以下将结合附图具体说明本发明各实施例提供的技术方案。 [0034] The following detailed description in conjunction with the technical solutions provided in the embodiments of the invention the accompanying drawings. 需要说明的是,本发明附图中所示的各功能膜层之间的相对距离或厚度等特征不代表真实的距离和厚度,仅是用于说明本发明,不用于限制本发明。 Incidentally, features, etc. or the relative distance between the thickness of the functional film of the present invention shown in the figures do not represent actual distance and thickness, the present invention is illustrative only, not intended to limit the present invention.

[0035] 如图2〜图6所示,其中,图2为本发明阵列基板一实施例靠近集成电路区域的俯视结构示意图;图3为图2示出的阵列基板中A处一实施例的剖面结构放大示意图;图4为图2示出的阵列基板中A处另一实施例的剖面结构放大示意图;图5为本发明阵列基板一实施例远离集成电路区域的俯视结构示意图;图6为图5示出的阵列基板的剖面结构放大示意图。 [0035] As shown in FIG. 2 ~ 6, wherein the array substrate of FIG 2 a schematic embodiment of an integrated circuit structure close to a top region of the present invention; FIG. 3 is a diagram illustrating an array substrate of an embodiment in FIG. 2 at A an enlarged schematic cross-sectional configuration; FIG. 4 is a cross-sectional structure of the array substrate shown in FIG. 2 of another embodiment of an enlarged schematic view at a; FIG. 5 is an embodiment of the invention, an array substrate a schematic top view of an integrated circuit region remote from the structure; FIG. 6 is a the array substrate cross-sectional structure shown in FIG. 5 is an enlarged schematic view.

[0036] 本发明第一实施例所提供的阵列基板,包括多个栅极焊垫,每一个栅极焊垫包括:位于衬底基板之上的栅极层10,位于栅极层10之上的栅极绝缘层11,位于栅极绝缘层11之上的第一透明导电层12,位于第一透明导电层12之上的钝化层14,以及位于钝化层14之上的第二透明导电层15,其中, [0036] The array substrate according to a first embodiment of the present invention, includes a plurality of gate pads, each gate pad comprising: a gate layer over the base substrate 10, a gate layer over 10 a gate insulating layer 11, a first transparent conductive layer 11 on the gate insulating layer 12, passivation layer 14 located above the first transparent conductive layer 12, and a second transparent layer over the passivation 14 conductive layer 15, wherein,

[0037] 栅极层10包括栅极焊接区域;栅极绝缘层11开设有位于栅极焊接区域上方的至少一个第一过孔111 ;第一透明导电层12通过每一个第一过孔111与栅极焊接区域导电接触;钝化层14开设有至少一个第二过孔141,第二透明导电层15通过每一个第二过孔141与第一透明导电层12导电接触。 [0037] The gate layer 10 comprises a gate pad region; the gate insulating layer 11 defines a weld region located above the gate of the at least one first through hole 111; a first transparent conductive layer 12 through each of the first through hole 111 and the gate conductive contact welding area; passivation layer 14 defines at least one second through hole 141, the second transparent conductive layer 15 with the conductive contact 12 through the first transparent conductive layer, each of the second through hole 141.

[0038] 本实施例提供的阵列基板中,栅极绝缘层11开设有位于栅极焊接区域上方的至少一个第一过孔111,第一过孔111露出部分栅极焊接区域,使得第一透明导电层12通过第一过孔111与栅极焊垫的栅极焊接区域导电接触;钝化层14开设有至少一个第二过孔141,第二透明导电层15通过第二过孔141与位于栅极绝缘层11上的第一透明导电层12导电接触,即钝化层14开设的第二过孔141与栅极绝缘层11上开设的第一过孔111的位置相错。 [0038] The present embodiment provides an array substrate, the gate insulating layer 11 defines at least a first through hole 111 located above the gate region of the welding, the exposed portion 111 via a first weld region of the gate, so that the first transparent conductive layer 12 by soldering a conductive contact with the gate region of the gate pad 111 of the first via hole; passivation layer 14 defines at least one second through hole 141, the second transparent conductive layer 15 through the second via hole 141 and located the first position of the through hole 111 of the opening 141 of the conductive contacts 12 of the first transparent conductive layer on the gate insulating layer 11, i.e., the second passivation layer 14 defines a through hole on the gate insulating layer 11 is staggered.

[0039] 在阵列基板的制作过程中,由于阵列基板的第二透明导电层15通过位于栅极绝缘层11上方的第一透明导电层12与栅极焊接区域导电接触,而未直接与栅极焊接区域导电接触,因此,即使电解液穿过第二过孔141处的第二透明导电层15和第一透明导电层12出现渗透,第一透明导电层12下方的栅极绝缘层11能够有效地防止电解液进一步渗透至栅极层10而引起栅极层10的腐蚀,从而有效地防止了栅极焊垫的腐蚀情况发生,进而提高产品的良品率和可靠性; [0039] In the production process of the array substrate, since the second transparent conductive layer conductive contact array substrate 15 through the first transparent conductive layer located above the gate insulating layer 11 and the gate 12 of the welding area, but not directly to the gate conductive contact welding region, thus, 15 and 12 bleeds through the first transparent conductive layer even when the electrolytic solution passes through the second transparent conductive layer through a second hole 141, the gate insulating layer under the first transparent conductive layer 1211 can be effectively preventing further penetration of the electrolyte layer 10 due to the gate etching the gate layer 10, thereby effectively preventing the corrosion of the gate pad occurs, thereby improving yield and reliability of the product;

[0040] 并且,本实施例提供的阵列基板还能有效地防止产品在客户端由于不规范操作导致产品腐蚀的情况发生,同时采用本实施例提供的阵列基板,使得产品在生产过程以及运输过程中的储存时间更长且不易发生产品腐蚀,尤其当产品采用开口设计的切割工艺、产品采用非真空包装或者在运输过程中渗入产品内部电解液(例如水汽等)时,上述效果尤为明显。 [0040] Further, the array substrate provided according to the present embodiment is also effective in preventing the product since the client abnormal operations lead to the occurrence of corrosion product, while using the array substrate provided by the present embodiment, so that the product in the production process and during transportation the storage time longer and less prone to corrosion products, especially when the product is designed to open the cutting process, vacuum-packed products, or non-electrolyte penetration within the product during transport (e.g., water vapor, etc.), the above effect is particularly evident.

[0041] 第一过孔111的数量不限,可以为一个,也可以为多个,参照图4所示,当第一过孔111的数量为多个时,能够有效地增大第一透明导电层12与栅极焊接区域的接触面积、第一透明导电层12与第二透明导电层15的接触面积,从而降低电阻率,进而减少了测试信号的线路损耗,进一步提闻了广品的可罪性。 [0041] The number of the first through hole 111 is not limited, it may be one, or may be a plurality of reference figure, when the number of the first plurality of vias 111, can be efficiently increased first transparent 4 weld region 12 and the gate contact area between the conductive layer, a first transparent conductive layer 12 and the second transparent conductive layer 15 of the contact area, thereby lowering the resistivity, thereby reducing the loss of the test signal line, further improving the smell wide product sin can be.

[0042] 栅极焊垫通常包括位于靠近集成电路16的区域的集成电路的栅极焊垫(如图2中所示的A)和远离阵列基板的集成电路16区域的栅极焊垫(如图5所示)。 [0042] The gate pad generally includes a pad of an integrated circuit close to the gate region 16 of an integrated circuit (A shown in FIG. 2) and a gate region 16 of the pad remote from the integrated circuit array substrate (e.g. As shown in FIG. 5).

[0043] 结合图2和图3所示,当本实施例中的栅极焊垫位于靠近阵列基板的集成电路16(例如S/W测试电路)区域时,即栅极焊垫为集成电路的栅极焊垫时,集成电路的栅极焊垫还包括位于第一透明导电层12与钝化层14之间且包括位于栅极焊接区域上方的源漏极的源漏极层13,至少一个第二过孔141未露出源漏极层13。 [0043] in conjunction with FIGS. 2 and 3, when the present embodiment gate pad located adjacent the integrated circuit array substrate 16 (e.g., S / W test circuit) of the region, i.e., the gate pad of an integrated circuit the gate pad, the gate pad of the integrated circuit further comprises a first transparent conductive layer and the passivation layer 12 includes a source drain layer is positioned above the source and drain regions 13 between the gate pad 14, at least one The second hole 141 through the source-drain layer 13 is not exposed.

[0044] 测试电路16输出测试信号至源漏极,源漏极与第一透明导电层12导电接触,第一透明导电层12通过栅极绝缘层11的第一过孔111与栅极焊接区域导电接触,使得测试信号从源漏极经过第一透明导电层12换层至栅极层10的栅极焊接区域,并从第二透明导电层15输出,进而实现产品的电学性能测试。 [0044] The test circuit 16 outputs a test signal source to the drain, source and drain contacts 12 electrically conductive with the first transparent conductive layer, a first transparent conductive layer 12 through the gate insulating layer 111 of the first through hole 11 and the gate pad region conductive contact, so that the test signal from the drain of the first transparent conductive layer 12 through the conversion layer to the gate region of the gate solder layer 10, and the output from the second transparent conductive layer 15, thus achieving the electrical performance test product.

[0045] 如图5和图6所示,当本实施例中的栅极焊垫为远离阵列基板的测试电路区域的栅极焊垫时,测试信号从第二透明导电层15输入(例如通过柔性线路板的导电凸点与第二透明导电层15的上表面导电接触),测试信号经过第二透明导电层15和第一透明导电层12传输至栅极层10的焊接区域,并从焊接区域输出,从而实现产品的电学性能测试。 [0045] As shown in FIG. 5 and 6, when the present embodiment gate pad away from the gate pad region of the array substrate of the test circuit, the test signal input from the second transparent conductive layer 15 (e.g., by the conductive bumps of the flexible wiring board and the second transparent conductive layer on the surface of the conductive contact 15), a second test signal transmitted through the transparent conductive layer 15 and the first transparent conductive layer 12 to the welding region of the gate layer 10, and from the welding output area, thereby achieving the electrical performance test of the product.

[0046] 阵列基板通常还包括多个源漏极焊垫,由于阵列基板制作过程中使用的曝光设备的分辨率有限,多个源漏极焊垫与栅极焊垫间隔设置。 [0046] The array substrate typically includes a plurality of source and drain pads, due to the limited resolution of the exposure apparatus using an array substrate production process, a plurality of source and drain pads and the gate pads intervals.

[0047] 为了进一步提闻广品的可罪性与良品率,如图2和图7所不,在本发明如述实施例的基础上,还提供了第二实施例,在第二实施例中,每一个源漏极焊垫包括:位于栅极绝缘层11之上的第一透明导电层12,位于第一透明导电层12之上的源漏极层13,位于源漏极层13之上的钝化层14,以及位于钝化层14之上的第二透明导电层15,其中, [0047] In order to further improve the smell can sin broad product yield, FIGS. 2 and 7 are not, on the basis of the present invention, as described on the embodiment, the second embodiment is also provided, in the second embodiment , each of the source and drain pad comprising: a first transparent conductive layer 12 over the gate insulating layer 11, source and drain layer 13 is positioned above the first transparent conductive layer 12, the layer 13 is located on the source and drain on the passivation layer 14, and a second transparent conductive layer 14 on the passivation layer 15, wherein,

[0048] 源漏极层13包括源漏极焊接区域,钝化层14开设有至少一个未露出源漏极层的第三过孔142,第二透明导电层15通过每一个第三过孔142与第一透明导电层12导电接触。 [0048] The drain layer 13 includes source and drain regions welding, passivation layer 14 defines at least one drain of the third layer is not exposed through the holes 142, 142 through the second transparent conductive layer 15 of each third through hole 12 conductive contact with the first transparent conductive layer.

[0049] 源漏极焊垫可以为靠近阵列基板的集成电路(例如S/W测试电路)区域的源漏极焊垫,也可以为远离阵列基板的集成电路区域(例如阵列基板对盒的边缘位置)的源漏极焊垫。 [0049] The drain pad may be closer to the array integrated circuit substrate (e.g., S / W test circuit) source and drain regions of the pad, or may be an integrated circuit region remote from the array substrate (e.g. the edge of the array substrate cassette position) of the source and drain pads. 下面以源漏极焊垫为靠近阵列基板的集成电路区域的源漏极焊垫例进行说明本实施例。 Below the source drain region of the integrated circuit pad to a source close to the drain pad of the array substrate of the present embodiment will be described with embodiment examples.

[0050] 如图7所示,本实施例提供的阵列基板进行测试时,测试电路输出测试信号至源漏极焊接区域,实现产品的电学性能测试。 [0050] As shown in FIG 7, when the array substrate provided by the test, the test circuit outputs a test signal to the source and drain regions welding present embodiment, and product testing electrical properties. 由于本实施例提供的阵列基板中,钝化层14开设有至少一个未露出源漏极层的第三过孔142,第二透明导电层15通过每一个第三过孔142与第一透明导电层12导电接触,在阵列基板的制作过程中,能够有效地防止电解液穿过第三过孔142处的第二透明导电层15和第一透明导电层12出现渗透而引起源漏极层的腐蚀,从而有效地防止了源漏极焊垫的腐蚀情况发生,进而提高产品的良品率和可靠性,因此,本实施例提供的阵列基板能够有效地防止阵列基板的各个栅极焊垫以及源漏极焊垫的腐蚀情况发生,进一步提闻了广品的良品率和可罪性。 Since the array substrate is provided in this embodiment, the passivation layer 14 defines at least one drain of the third layer is not exposed through hole 142, the second transparent conductive layer 15 through a third through hole 142 and each of the first transparent conductive conductive contact layer 12, the manufacturing process of the array substrate, the electrolyte can be effectively prevented from passing through the second transparent conductive layer 15 and the first transparent conductive layer 142 of the third through hole 12 occurs to cause penetration of the source and drain layer etching, thereby effectively preventing the corrosion of the source and drain pads occurs, thereby improving yield and reliability of products, therefore, the array substrate is provided according to the present embodiment can effectively prevent the respective gate pad and the source pad of the array substrate the drain pad corrosion occurs, the yield is further improved smell and products can be widely sin.

[0051] 需要说明的是,本发明实施例提供的阵列基板中,栅极绝缘层11的材质可以为氮化硅,在此不做具体限定;位于栅极焊接区域上方的源漏极的设置位置不限,可以部分位于栅极绝缘层11的第一过孔111内,也可以全部位于栅极绝缘层11的第一过孔111外,在此不做具体限定,能够实现栅极焊垫的电学性能即可;第一透明导电层12和第二透明导电层15的材质不限,可以但不限于氧化铟锡或石墨烯,由于氧化铟锡具有透光性好、低电阻以及耐腐蚀的优点,因此第一透明导电层12和第二透明导电层15优选采用氧化铟锡。 [0051] Incidentally, the array substrate according to an embodiment of the present invention, the material of the gate insulating layer 11 may be silicon nitride, which is not particularly limited; the source and drain regions located above the gate pad disposed Any position may be partially located in the first hole 111 through the gate insulating layer 11 may be all located outside of the first hole 111 through the gate insulating layer 11, which is not specifically defined, it is possible to achieve a gate pad electrical properties can; material of the first transparent conductive layer 12 and the second transparent conductive layer 15 is not limited, but may be limited to, indium tin oxide or graphene, since the indium tin oxide has good transparency, low resistance and corrosion resistance advantages, the first transparent conductive layer 12 and the second transparent conductive layer 15 is preferably indium tin oxide.

[0052] 基于上述实施例中提供的阵列基板,本发明实施例还提供了一种显示装置,包括上述实施例所提供的阵列基板。 [0052] Based on the array substrate provided in the above embodiment, embodiments of the present invention further provides a display device comprising an array substrate provided in the above-described embodiments.

[0053] 在显示装置中,由于阵列基板的栅极焊垫中的第二透明导电层通过位于栅极绝缘层上方的第一透明导电层与栅极焊接区域导电接触,而未直接与栅极焊接区域导电接触,能够有效地防止阵列基板上各个栅极焊垫的腐蚀情况发生,所以该显示装置的良品率和可靠性较高。 [0053] In the display device, since the second transparent conductive layer of the gate bonding pad of the array substrate through the first transparent conductive layer positioned in contact with the conductive gate pad region of the gate insulating layer above the gate electrode directly without welding area conductive contact, corrosion can be effectively prevented on each of the gate pad array substrate occurs, thus a high yield of the display device and the reliability. 该显示装置可以为:手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。 The display device may be: mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frame, a navigator, and any other product or component having a display function.

[0054] 本发明实施例还提供一种阵列基板的制作方法,如图8所示,图8为本发明一实施例阵列基板的制作方法的流程示意图,该制作方法包括: [0054] Embodiments of the present invention further provides a method for manufacturing an array substrate, as shown in FIG. 8, FIG. 8 is a schematic flowchart of the manufacturing method of an array substrate of the embodiment of the invention, the manufacturing method comprising:

[0055] 步骤801:在衬底基板上形成包括栅极焊接区域的栅极层的图形; [0055] Step 801: forming a gate pattern including a gate layer in the weld region on the base substrate;

[0056] 步骤801中形成形成包括栅极焊接区域的栅极层的图形可以采用一次构图工艺制作完成,构图工艺通常包括基板清洗、成膜、光刻胶涂覆、曝光、显影、刻蚀、光刻胶剥离等工序,即沉积栅极金属薄膜,对于金属层通常采用物理气相沉积方式(例如磁控溅射法)成膜,通过湿法刻蚀形成包括栅极焊接区域的栅极层的图形。 [0056] Step 801 comprises forming a gate pattern the gate layer weld region may take one patterning process finished, the process generally comprises patterning the substrate cleaning, deposition, photoresist coating, exposure, development, etching, photoresist stripping processes, i.e., deposition of the gate metal thin film, the metal layer is generally a physical vapor deposition method (e.g. magnetron sputtering) deposition, forming a gate layer comprises a gate weld region by wet etching graphics.

[0057] 步骤802:在栅极层的图形之上形成包括位于栅极焊接区域上方的至少一个第一过孔的栅极绝缘层的图形; [0057] Step 802: forming a gate pattern including the gate insulating layer above the weld region through the at least one first hole pattern over the gate layer;

[0058] 由于阵列基板通常还包括位于栅极绝缘层之上且与栅极焊接区域位置相对的有源层,因此,步骤802中可以采用一次构图工艺形成包括位于栅极焊接区域上方的至少一个第一过孔的栅极绝缘层的图形,具体包括沉积栅极绝缘层薄膜,在栅极绝缘层薄膜之上沉积有源层薄膜,非金属层通常采用化学气相沉积方式成膜,通过干法刻蚀形成图形,刻蚀形成有源层的图形,并刻蚀形成包括位于栅极焊接区域上方的至少一个第一过孔的栅极绝缘层的图形。 [0058] Since the array substrate further includes a generally opposite the active layer and the gate position of the welding region on the gate insulating layer, and therefore, step 802 may be formed using a patterning process includes a gate electrode over the at least one weld region a first via hole pattern of the gate insulating layer, a gate insulating layer comprises depositing a thin film, the active layer is deposited in a thin film over the gate insulating layer thin, non-metal layer is typically deposited using a chemical vapor deposition manner, by dry etching pattern is formed, etching the active layer pattern is formed, and a gate pattern including at least one weld region above the first insulating layer through hole is etched to form the gate.

[0059] 步骤803:在栅极绝缘层的图形之上形成通过每一个第一过孔与栅极焊接区域导电接触的第一透明导电层的图形; [0059] Step 803: a first transparent conductive layer is formed by each of the first through hole electrically conductive contact with the gate pattern in the weld region on the gate insulating layer pattern;

[0060] 步骤803也可以采用一次构图工艺形成,具体包括沉积第一透明导电层薄膜,刻蚀形成通过每一个第一过孔与所述栅极焊接区域导电接触的第一透明导电层的图形,即刻蚀第一透明导电层薄膜时保留位于栅极绝缘层的至少一个第一过孔内的第一透明导电层。 [0060] Step 803 may be formed using a patterning process, comprises depositing a first transparent conductive layer thin film pattern etched to form a first transparent conductive layer, a first through hole through each conductive contact with the gate weld region , i.e. retained when etching the first transparent conductive layer of the gate insulating film layer of the first transparent conductive layer through the at least one first hole.

[0061] 步骤804:在第一透明导电层的图形之上形成包括至少一个第二过孔的钝化层的图形;[0062] 步骤804具体包括步骤8041和步骤8042,其中, [0061] Step 804: the first pattern is formed on the transparent conductive layer, the passivation layer pattern comprises at least one second via hole; [0062] Step 804 comprises steps 8041 and step 8042, wherein,

[0063] 步骤8041:在第一透明导电层的图形之上形成包括位于所述集成电路的栅极焊垫的栅极焊接区域上方的源漏极的源漏极层的图形;例如,可以通过构图工艺形成源漏极层的图形时,刻蚀掉位于远离集成电路区域的栅极焊垫的栅极焊接区域上方的源漏极层,保留靠近集成电路区域的栅极焊垫的栅极焊接区域上方的源漏极层,具体根据源漏极的位 [0063] Step 8041: forming a gate pattern comprises a solder region over the gate pad of the integrated circuit pad positioned the source-drain source-drain layer over the first pattern of the transparent conductive layer; for example, by when the source and drain patterning process for forming the pattern layer, etching away the gate layer over the source and drain region of the weld area away from the integrated circuit of the gate pad, the gate pad to retain the integrated circuit region near the gate pad layer over the source and drain regions, the source and drain of the specific bit according to

置确定。 Home OK.

[0064] 步骤8042:在源漏极层的图形之上形成包括至少一个未露出源漏极层的第二过孔的钝化层的图形;步骤8042也可以采用一次构图工艺形成包括至少一个未露出源漏极层的第二过孔的钝化层的图形。 [0064] Step 8042: forming a passivation layer pattern comprises at least one source-drain layer is not exposed at the second via hole pattern above the source-drain layer; step 8042 may be formed by one patterning process comprising at least one non- pattern of the passivation layer to expose the source and drain layer of the second via hole.

[0065] 步骤805:在钝化层的图形之上形成通过每一个第二过孔与第一透明导电层导电接触的第二透明导电层的图形。 [0065] Step 805: a second transparent conductive layer pattern formed by each of the second through hole in contact with the first transparent conductive layer on the conductive pattern of the passivation layer.

[0066] 步骤805也可以采用一次构图工艺形成通过每一个第二过孔与第一透明导电层导电接触的第二透明导电层的图形。 [0066] Step 805 may also be formed by each of the second transparent conductive layer via a second transparent conductive layer in contact with the first conductive pattern using a patterning process.

[0067] 至此,包括靠近集成电路区域的栅极焊垫和远离集成电路区域的栅极焊垫的阵列基板制作完成。 [0067] Thus, the integrated circuit comprising a region close to the gate pad and the pad away from the gate array integrated circuit substrate area finished.

[0068] 需要说明的是,一次构图工艺通常包括基板清洗、成膜、光刻胶涂覆、曝光、显影、刻蚀、光刻胶剥离等工序;对于金属层通常采用物理气相沉积方式(例如磁控溅射法)成膜,通过湿法刻蚀形成图形,而对于非金属层通常采用化学气相沉积方式成膜,通过干法刻蚀形成图形,以下步骤道理相同,不再赘述。 [0068] Incidentally, one patterning process generally comprises cleaning the substrate, deposition, photoresist coating, exposure, development, etching and photoresist stripping processes; the metal layer is generally a physical vapor deposition method (e.g. magnetron sputtering) deposition, pattern formed by wet etching, and deposition method for forming a non-metallic chemical vapor layer is generally formed by dry etching pattern, the steps of the same reason, will not be repeated. 在本发明中,构图工艺,可只包括光刻工艺,或,包括光刻工艺以及刻蚀步骤,同时还可以包括打印、喷墨等其他用于形成预定图形的工艺;光刻工艺,是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。 In the present invention, the patterning process may include only a photolithography process, or photolithography process and etching steps including, but also can include a printing process, ink jet and other for forming a predetermined pattern; photolithography process, means a film-forming, exposure and development using the photoresist pattern process and other processes, the mask, an exposure machine or the like. 可根据本发明中所形成的结构选择相应的构图工艺。 Select the appropriate structure patterning process according to the present invention is formed.

[0069] 当阵列基板还包括多个源漏极焊垫时,以下用一个较优的实施例对阵列基板的制作方法进行说明,本发明并不限于下述实施例本发明实施例提供的制作方法,包括: [0069] When the substrate further comprises a plurality of array source and drain pads, a less preferable embodiment of the production method of the array substrate will be described, the present invention is not limited to embodiments of the present invention is prepared following examples provide embodiments of the method, comprising:

[0070] 步骤Sll:在衬底基板上形成包括栅极焊接区域的栅极层的图形; [0070] Step Sll: forming a gate pattern including a gate layer in the weld region on the base substrate;

[0071] 步骤S12:在栅极层的图形之上形成包括位于栅极焊接区域上方的至少一个第一过孔的栅极绝缘层的图形; [0071] Step S12: forming a gate pattern including the gate insulating layer above the weld region through the at least one first hole pattern over the gate layer;

[0072] 步骤S13:在栅极绝缘层的图形之上形成通过每一个第一过孔与栅极焊接区域导电接触的第一透明导电层的图形; [0072] Step S13: a first transparent conductive layer is formed by each of the first through hole electrically conductive contact with the gate pattern in the weld region on the gate insulating layer pattern;

[0073] 即通过构图工艺形成第一透明导电层的图形时,保留位于栅极绝缘层的至少一个第一过孔内的第一透明导电层。 When [0073] i.e. the first transparent conductive layer pattern is formed through a patterning process, a first transparent conductive layer to retain the at least one first through hole of the gate insulating layer.

[0074] 步骤S14:在第一透明导电层的图形之上形成包括源漏极焊接区域和位于集成电路区域的栅极焊垫的栅极焊接区域上方的源漏极的源漏极层的图形; [0074] Step S14: forming a pattern layer comprising source and drain regions and the source and drain welding the integrated circuit gate pad region of the source and drain regions above the gate pad is welded on the first transparent conductive layer pattern ;

[0075] 即通过构图工艺形成第一透明导电层的图形时,刻蚀掉位于远离集成电路区域的栅极焊垫的栅极焊接区域上方的源漏极层,保留源漏极焊接区域和靠近集成电路区域的栅极焊垫的栅极焊接区域上方的源漏极层。 When [0075] i.e. the first transparent conductive layer pattern is formed through a patterning process, etching away the gate layer over the source and drain region of the weld area away from the integrated circuit of the gate pad, and retain the source and drain regions near the weld the source-drain layer over the gate pad region of the gate region of the integrated circuit bonding pad.

[0076] 步骤S15:在源漏极层的图形之上形成包括至少一个未露出源漏极层的第二过孔和至少一个未露出源漏极层焊接区域的第三过孔的钝化层的图形; [0076] Step S15: forming a passivation layer comprises at least one source-drain layer is not exposed and at least one second via hole is not exposed source and drain regions of the third layer pad vias on the source and drain pattern layer graphics;

[0077] 步骤S16:在钝化层的图形之上形成第二透明导电层的图形,第二透明导电层通过每一个第二过孔和第三过孔与第一透明导电层导电接触。 [0077] Step S16: forming a second transparent conductive layer pattern on the pattern of the passivation layer, a second transparent conductive layer is formed by each of the second through hole and a third hole through the first conductive layer and the transparent conductive contact.

[0078] 通过上述制作方法制作的阵列基板,相较于现有技术中,第二透明导电层与栅极焊接区域、源漏极焊接区域直接导电接触,极易导致阵列基板的焊垫发生腐蚀,本发明制作方法制作得到的阵列基板,第二透明导电层通过第一透明导电层与栅极焊接区域、源漏极焊接区域导电接触,未直接与栅极焊接区域、源漏极焊接区域导电接触,能够有效地防止阵列基板上各个焊垫的腐蚀情况发生,从而提高产品的良品率和可靠性;并且,由上述制作过程可知,本发明提供的制作方法相较于现有技术仅增加了一次栅极绝缘层掩膜工艺,因此采用本发明提供的阵列基板,能够使得产品的生产成本较低,应用更加广泛。 [0078] prepared by the above method for manufacturing an array substrate, compared to the prior art, the transparent conductive layer of the gate of the second weld region, source and drain region is in direct conductive contact with the welding, the pad array can easily lead to corrosion of the substrate , the array substrate manufacturing method according to the present invention was prepared, the second transparent conductive layer through the first transparent conductive layer in contact with the gate conductive region welding, the welding source and drain regions, not directly to the gate bonding pad region, the source-drain region of the conductive welding contact corrosion can be effectively prevented respective pads on the array substrate occurs, thereby improving yield and reliability of the product; and, seen from the above manufacturing process, the present invention provides a manufacturing method compared to the prior art only increases a gate insulating layer mask process, so the use of the present invention provides an array substrate, enables lower production costs, more widely.

[0079] 显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。 [0079] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. 这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。 Thus, if these modifications and variations of the present invention fall within the claims of the invention and the scope of equivalents thereof, the present invention intends to include these modifications and variations.

Claims (8)

1.一种阵列基板,包括多个栅极焊垫,其特征在于,每一个所述栅极焊垫包括:位于衬底基板之上的栅极层,位于所述栅极层之上的栅极绝缘层,位于所述栅极绝缘层之上的第一透明导电层,位于所述第一透明导电层之上的钝化层,以及位于所述钝化层之上的第二透明导电层,其中, 所述栅极层包括栅极焊接区域;所述栅极绝缘层开设有位于所述栅极焊接区域上方的至少一个第一过孔;所述第一透明导电层通过每一个第一过孔与所述栅极焊接区域导电接触;所述钝化层开设有至少一个第二过孔,所述第二透明导电层通过每一个第二过孔与所述第一透明导电层导电接触。 An array substrate comprising a plurality of gate pads, characterized in that each of the gate pad comprising: a gate layer over the base substrate, the gate situated over the gate layer a gate insulating layer, a first transparent conductive layer positioned on the gate insulating layer, a passivation layer over the first transparent conductive layer, and a passivation layer located over the second transparent conductive layer wherein said gate layer comprises a gate pad region; the gate insulating layer above the gate defines a weld region located at least one first via hole; the first transparent conductive layer is formed by each of the first via conductive contact with the gate pad region; the passivation layer defines at least one second through hole, the second transparent conductive layer is formed by each of the second through hole in contact with the first transparent conductive layer of conductive .
2.如权利要求1所述的阵列基板,其特征在于,所述栅极焊垫为集成电路的栅极焊垫,所述集成电路的栅极焊垫还包括位于所述第一透明导电层与所述钝化层之间且包括位于所述栅极焊接区域上方的源漏极的源漏极层,所述至少一个第二过孔未露出所述源漏极层。 2. The array substrate according to claim 1, wherein said gate pad is the gate pad of the integrated circuit, the integrated circuit further comprises a gate pad in the first transparent conductive layer the passivation layer and between the source and the drain comprises a gate electrode layer is located above the weld region of the source and drain, said at least one second via hole exposing the source and drain layer is not.
3.如权利要求2所述的阵列基板,其特征在于,还包括多个源漏极焊垫,每一个所述源漏极焊垫包括:位于所述栅极绝缘层之上的第一透明导电层,位于所述第一透明导电层之上的源漏极层,位于所述源漏极层之上的钝化层,以及位于所述钝化层之上的第二透明导电层,其中, 所述源漏极层包括源漏极焊接区域,所述钝化层开设有至少一个未露出所述源漏极层的第三过孔,所述第二透明导电层通过每一个所述第三过孔与所述第一透明导电层导电接触。 The array substrate according to claim 2, characterized in that, further comprising a plurality of source and drain pads, each of said source and drain pad comprising: a first transparent insulating layer over the gate a conductive layer located on the source-drain layer over the first transparent conductive layer, a passivation layer over the source and drain layer, and a second transparent conductive layer located above the passivation layer, wherein , the source-drain layer including a source region of the drain pad, the passivation layer defines at least one through-hole is not exposed to the source and drain of the third layer, the second transparent conductive layer is formed by each of said first three vias contact with the first transparent conductive layer electrically conductive.
4.如权利要求1~3任一所述的阵列基板,其特征在于,所述第一透明导电层包括氧化铟锡层,和/或,所述第二透明导电层包括氧化铟锡层。 The array substrate according to any one of claims 1 to 3, wherein said first conductive layer comprises a transparent layer of indium tin oxide, and / or the second transparent conductive layer include indium tin oxide layer.
5.一种显示装置,其特征在于,包括如权利要求1~4任一所述的阵列基板。 A display device comprising an array substrate according to any one of claims 1 to 4.
6.一种阵列基板的制作方法,其特征在于,包括: 在衬底基板上形成包括栅极焊接区域的栅极层的图形; 在所述栅极层的图形之上形成包括位于所述栅极焊接区域上方的至少一个第一过孔的栅极绝缘层的图形; 在所述栅极绝缘层的图形之上形成通过每一个第一过孔与所述栅极焊接区域导电接触的第一透明导电层的图形; 在所述第一透明导电层的图形之上形成包括至少一个第二过孔的钝化层的图形; 在所述钝化层的图形之上形成通过每一个第二过孔与所述第一透明导电层导电接触的第二透明导电层的图形。 A method of manufacturing an array substrate, comprising: forming a gate pattern including a gate layer weld region on the base substrate; includes forming the gate over the gate layer pattern at least one gate insulating layer pattern of the first via electrode over the weld region; forming a first through hole through each of the first weld region and the gate contact over the conductive pattern of the gate insulating layer pattern of the transparent conductive layer; forming a passivation layer pattern comprises at least one second via hole pattern on the first transparent conductive layer; forming a second via through each pattern on the passivation layer the second transparent conductive layer pattern hole conductive contact with the first transparent conductive layer.
7.如权利要求6所述的阵列基板的制作方法,其特征在于,在所述第一透明导电层的图形之上形成包括至少一个第二过孔的钝化层的图形,具体包括: 在所述第一透明导电层的图形之上形成包括位于所述集成电路的栅极焊垫的栅极焊接区域上方的源漏极的源漏极层的图形; 在所述源漏极层的图形之上形成包括至少一个第二过孔的钝化层的图形,所述至少一个第二过孔未露出所述源漏极层。 7. The method of manufacturing the array substrate of claim 6, wherein the passivation layer pattern comprises forming at least one second via hole pattern on the first transparent conductive layer comprises: at the pattern of the first transparent conductive layer above the source and drain pattern including a source-drain layer over the gate region of the soldering pads of the integrated circuit of the gate is formed; in the source and drain pattern layer pattern is formed on the passivation layer comprises at least one second via hole, said via hole of said at least one second source and drain layer is not exposed.
8.如权利要求7所述的阵列基板的制作方法,其特征在于, 在形成包括位于所述集成电路的栅极焊垫的栅极焊接区域上方的源漏极的源漏极层的图形的同时,还形成源漏极焊接区域的图形; 在形成包括至少一个未露出所述源漏极层的第二过孔的钝化层的图形的同时,还形成至少一个未露出所述源漏极层的第三过孔,所述第二透明导电层通过每一个所述第三过孔与所述第一透明导电层导电接触。 8. The method of fabricating the array substrate of claim 7, wherein the source-drain pattern is formed in the source-drain layer over the gate pad of the integrated circuit region comprises a gate pad Meanwhile, a source-drain pattern is also formed weld region; simultaneously with the formation of the passivation layer pattern comprises at least one of said source and drain of the second layer is not exposed through the hole, also forming at least one of said source and drain electrodes is not exposed the third layer via hole, the second transparent conductive layer is formed by each of the third through hole of the first transparent conductive layer and the conductive contact.
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